51 chan->
base.vblank.offset &= 0x00ffffffffULL;
52 chan->
base.vblank.offset |= data << 32;
54 chan->
base.vblank.offset &= 0xff00000000ULL;
65 chan->
base.vblank.value = *(
u32 *)args;
84 list_add(&chan->
base.vblank.head, &disp->
vblank.list);
85 chan->
base.vblank.crtc = crtc;
86 spin_unlock_irqrestore(&disp->
vblank.lock, flags);
96 return chan->
base.flip(chan->
base.flip_data);
101 nvc0_software_omthds[] = {
102 { 0x0400, nvc0_software_mthd_vblsem_offset },
103 { 0x0404, nvc0_software_mthd_vblsem_offset },
104 { 0x0408, nvc0_software_mthd_vblsem_value },
105 { 0x040c, nvc0_software_mthd_vblsem_release },
106 { 0x0500, nvc0_software_mthd_flip },
111 nvc0_software_sclass[] = {
130 *pobject = nv_object(chan);
134 chan->
base.vblank.channel = nv_gpuobj(parent->
parent)->addr >> 12;
139 nvc0_software_cclass = {
142 .ctor = nvc0_software_context_ctor,
162 *pobject = nv_object(priv);
166 nv_engine(priv)->cclass = &nvc0_software_cclass;
167 nv_engine(priv)->sclass = nvc0_software_sclass;
176 .ctor = nvc0_software_ctor,