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envy24ht.h
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1 #ifndef __SOUND_VT1724_H
2 #define __SOUND_VT1724_H
3 
4 /*
5  * ALSA driver for ICEnsemble VT1724 (Envy24)
6  *
7  * Copyright (c) 2000 Jaroslav Kysela <[email protected]>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22  *
23  */
24 
25 #include <sound/control.h>
26 #include <sound/ac97_codec.h>
27 #include <sound/rawmidi.h>
28 #include <sound/i2c.h>
29 #include <sound/pcm.h>
30 
31 #include "ice1712.h"
32 
33 enum {
34  ICE_EEP2_SYSCONF = 0, /* 06 */
35  ICE_EEP2_ACLINK, /* 07 */
36  ICE_EEP2_I2S, /* 08 */
37  ICE_EEP2_SPDIF, /* 09 */
38  ICE_EEP2_GPIO_DIR, /* 0a */
39  ICE_EEP2_GPIO_DIR1, /* 0b */
40  ICE_EEP2_GPIO_DIR2, /* 0c */
41  ICE_EEP2_GPIO_MASK, /* 0d */
42  ICE_EEP2_GPIO_MASK1, /* 0e */
43  ICE_EEP2_GPIO_MASK2, /* 0f */
44  ICE_EEP2_GPIO_STATE, /* 10 */
45  ICE_EEP2_GPIO_STATE1, /* 11 */
46  ICE_EEP2_GPIO_STATE2 /* 12 */
47 };
48 
49 /*
50  * Direct registers
51  */
52 
53 #define ICEREG1724(ice, x) ((ice)->port + VT1724_REG_##x)
54 
55 #define VT1724_REG_CONTROL 0x00 /* byte */
56 #define VT1724_RESET 0x80 /* reset whole chip */
57 #define VT1724_REG_IRQMASK 0x01 /* byte */
58 #define VT1724_IRQ_MPU_RX 0x80
59 #define VT1724_IRQ_MPU_TX 0x20
60 #define VT1724_IRQ_MTPCM 0x10
61 #define VT1724_REG_IRQSTAT 0x02 /* byte */
62 /* look to VT1724_IRQ_* */
63 #define VT1724_REG_SYS_CFG 0x04 /* byte - system configuration PCI60 on Envy24*/
64 #define VT1724_CFG_CLOCK 0xc0
65 #define VT1724_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */
66 #define VT1724_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */
67 #define VT1724_CFG_MPU401 0x20 /* MPU401 UARTs */
68 #define VT1724_CFG_ADC_MASK 0x0c /* one, two or one and S/PDIF, stereo ADCs */
69 #define VT1724_CFG_ADC_NONE 0x0c /* no ADCs */
70 #define VT1724_CFG_DAC_MASK 0x03 /* one, two, three, four stereo DACs */
71 
72 #define VT1724_REG_AC97_CFG 0x05 /* byte */
73 #define VT1724_CFG_PRO_I2S 0x80 /* multitrack converter: I2S or AC'97 */
74 #define VT1724_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */
75 
76 #define VT1724_REG_I2S_FEATURES 0x06 /* byte */
77 #define VT1724_CFG_I2S_VOLUME 0x80 /* volume/mute capability */
78 #define VT1724_CFG_I2S_96KHZ 0x40 /* supports 96kHz sampling */
79 #define VT1724_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */
80 #define VT1724_CFG_I2S_192KHZ 0x08 /* supports 192kHz sampling */
81 #define VT1724_CFG_I2S_OTHER 0x07 /* other I2S IDs */
82 
83 #define VT1724_REG_SPDIF_CFG 0x07 /* byte */
84 #define VT1724_CFG_SPDIF_OUT_EN 0x80 /*Internal S/PDIF output is enabled*/
85 #define VT1724_CFG_SPDIF_OUT_INT 0x40 /*Internal S/PDIF output is implemented*/
86 #define VT1724_CFG_I2S_CHIPID 0x3c /* I2S chip ID */
87 #define VT1724_CFG_SPDIF_IN 0x02 /* S/PDIF input is present */
88 #define VT1724_CFG_SPDIF_OUT 0x01 /* External S/PDIF output is present */
89 
90 /*there is no consumer AC97 codec with the VT1724*/
91 //#define VT1724_REG_AC97_INDEX 0x08 /* byte */
92 //#define VT1724_REG_AC97_CMD 0x09 /* byte */
93 
94 #define VT1724_REG_MPU_TXFIFO 0x0a /*byte ro. number of bytes in TX fifo*/
95 #define VT1724_REG_MPU_RXFIFO 0x0b /*byte ro. number of bytes in RX fifo*/
96 
97 #define VT1724_REG_MPU_DATA 0x0c /* byte */
98 #define VT1724_REG_MPU_CTRL 0x0d /* byte */
99 #define VT1724_MPU_UART 0x01
100 #define VT1724_MPU_TX_EMPTY 0x02
101 #define VT1724_MPU_TX_FULL 0x04
102 #define VT1724_MPU_RX_EMPTY 0x08
103 #define VT1724_MPU_RX_FULL 0x10
104 
105 #define VT1724_REG_MPU_FIFO_WM 0x0e /*byte set the high/low watermarks for RX/TX fifos*/
106 #define VT1724_MPU_RX_FIFO 0x20 //1=rx fifo watermark 0=tx fifo watermark
107 #define VT1724_MPU_FIFO_MASK 0x1f
108 
109 #define VT1724_REG_I2C_DEV_ADDR 0x10 /* byte */
110 #define VT1724_I2C_WRITE 0x01 /* write direction */
111 #define VT1724_REG_I2C_BYTE_ADDR 0x11 /* byte */
112 #define VT1724_REG_I2C_DATA 0x12 /* byte */
113 #define VT1724_REG_I2C_CTRL 0x13 /* byte */
114 #define VT1724_I2C_EEPROM 0x80 /* 1 = EEPROM exists */
115 #define VT1724_I2C_BUSY 0x01 /* busy bit */
116 
117 #define VT1724_REG_GPIO_DATA 0x14 /* word */
118 #define VT1724_REG_GPIO_WRITE_MASK 0x16 /* word */
119 #define VT1724_REG_GPIO_DIRECTION 0x18 /* dword? (3 bytes) 0=input 1=output.
120  bit3 - during reset used for Eeprom power-on strapping
121  if TESTEN# pin active, bit 2 always input*/
122 #define VT1724_REG_POWERDOWN 0x1c
123 #define VT1724_REG_GPIO_DATA_22 0x1e /* byte direction for GPIO 16:22 */
124 #define VT1724_REG_GPIO_WRITE_MASK_22 0x1f /* byte write mask for GPIO 16:22 */
125 
126 
127 /*
128  * Professional multi-track direct control registers
129  */
130 
131 #define ICEMT1724(ice, x) ((ice)->profi_port + VT1724_MT_##x)
132 
133 #define VT1724_MT_IRQ 0x00 /* byte - interrupt mask */
134 #define VT1724_MULTI_PDMA4 0x80 /* SPDIF Out / PDMA4 */
135 #define VT1724_MULTI_PDMA3 0x40 /* PDMA3 */
136 #define VT1724_MULTI_PDMA2 0x20 /* PDMA2 */
137 #define VT1724_MULTI_PDMA1 0x10 /* PDMA1 */
138 #define VT1724_MULTI_FIFO_ERR 0x08 /* DMA FIFO underrun/overrun. */
139 #define VT1724_MULTI_RDMA1 0x04 /* RDMA1 (S/PDIF input) */
140 #define VT1724_MULTI_RDMA0 0x02 /* RMDA0 */
141 #define VT1724_MULTI_PDMA0 0x01 /* MC Interleave/PDMA0 */
142 
143 #define VT1724_MT_RATE 0x01 /* byte - sampling rate select */
144 #define VT1724_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */
145 #define VT1724_MT_I2S_FORMAT 0x02 /* byte - I2S data format */
146 #define VT1724_MT_I2S_MCLK_128X 0x08
147 #define VT1724_MT_I2S_FORMAT_MASK 0x03
148 #define VT1724_MT_I2S_FORMAT_I2S 0x00
149 #define VT1724_MT_DMA_INT_MASK 0x03 /* byte -DMA Interrupt Mask */
150 /* lool to VT1724_MULTI_* */
151 #define VT1724_MT_AC97_INDEX 0x04 /* byte - AC'97 index */
152 #define VT1724_MT_AC97_CMD 0x05 /* byte - AC'97 command & status */
153 #define VT1724_AC97_COLD 0x80 /* cold reset */
154 #define VT1724_AC97_WARM 0x40 /* warm reset */
155 #define VT1724_AC97_WRITE 0x20 /* W: write, R: write in progress */
156 #define VT1724_AC97_READ 0x10 /* W: read, R: read in progress */
157 #define VT1724_AC97_READY 0x08 /* codec ready status bit */
158 #define VT1724_AC97_ID_MASK 0x03 /* codec id mask */
159 #define VT1724_MT_AC97_DATA 0x06 /* word - AC'97 data */
160 #define VT1724_MT_PLAYBACK_ADDR 0x10 /* dword - playback address */
161 #define VT1724_MT_PLAYBACK_SIZE 0x14 /* dword - playback size */
162 #define VT1724_MT_DMA_CONTROL 0x18 /* byte - control */
163 #define VT1724_PDMA4_START 0x80 /* SPDIF out / PDMA4 start */
164 #define VT1724_PDMA3_START 0x40 /* PDMA3 start */
165 #define VT1724_PDMA2_START 0x20 /* PDMA2 start */
166 #define VT1724_PDMA1_START 0x10 /* PDMA1 start */
167 #define VT1724_RDMA1_START 0x04 /* RDMA1 start */
168 #define VT1724_RDMA0_START 0x02 /* RMDA0 start */
169 #define VT1724_PDMA0_START 0x01 /* MC Interleave / PDMA0 start */
170 #define VT1724_MT_BURST 0x19 /* Interleaved playback DMA Active streams / PCI burst size */
171 #define VT1724_MT_DMA_FIFO_ERR 0x1a /*Global playback and record DMA FIFO Underrun/Overrun */
172 #define VT1724_PDMA4_UNDERRUN 0x80
173 #define VT1724_PDMA2_UNDERRUN 0x40
174 #define VT1724_PDMA3_UNDERRUN 0x20
175 #define VT1724_PDMA1_UNDERRUN 0x10
176 #define VT1724_RDMA1_UNDERRUN 0x04
177 #define VT1724_RDMA0_UNDERRUN 0x02
178 #define VT1724_PDMA0_UNDERRUN 0x01
179 #define VT1724_MT_DMA_PAUSE 0x1b /*Global playback and record DMA FIFO pause/resume */
180 #define VT1724_PDMA4_PAUSE 0x80
181 #define VT1724_PDMA3_PAUSE 0x40
182 #define VT1724_PDMA2_PAUSE 0x20
183 #define VT1724_PDMA1_PAUSE 0x10
184 #define VT1724_RDMA1_PAUSE 0x04
185 #define VT1724_RDMA0_PAUSE 0x02
186 #define VT1724_PDMA0_PAUSE 0x01
187 #define VT1724_MT_PLAYBACK_COUNT 0x1c /* word - playback count */
188 #define VT1724_MT_CAPTURE_ADDR 0x20 /* dword - capture address */
189 #define VT1724_MT_CAPTURE_SIZE 0x24 /* word - capture size */
190 #define VT1724_MT_CAPTURE_COUNT 0x26 /* word - capture count */
191 
192 #define VT1724_MT_ROUTE_PLAYBACK 0x2c /* word */
193 
194 #define VT1724_MT_RDMA1_ADDR 0x30 /* dword - RDMA1 capture address */
195 #define VT1724_MT_RDMA1_SIZE 0x34 /* word - RDMA1 capture size */
196 #define VT1724_MT_RDMA1_COUNT 0x36 /* word - RDMA1 capture count */
197 
198 #define VT1724_MT_SPDIF_CTRL 0x3c /* word */
199 #define VT1724_MT_MONITOR_PEAKINDEX 0x3e /* byte */
200 #define VT1724_MT_MONITOR_PEAKDATA 0x3f /* byte */
201 
202 /* concurrent stereo channels */
203 #define VT1724_MT_PDMA4_ADDR 0x40 /* dword */
204 #define VT1724_MT_PDMA4_SIZE 0x44 /* word */
205 #define VT1724_MT_PDMA4_COUNT 0x46 /* word */
206 #define VT1724_MT_PDMA3_ADDR 0x50 /* dword */
207 #define VT1724_MT_PDMA3_SIZE 0x54 /* word */
208 #define VT1724_MT_PDMA3_COUNT 0x56 /* word */
209 #define VT1724_MT_PDMA2_ADDR 0x60 /* dword */
210 #define VT1724_MT_PDMA2_SIZE 0x64 /* word */
211 #define VT1724_MT_PDMA2_COUNT 0x66 /* word */
212 #define VT1724_MT_PDMA1_ADDR 0x70 /* dword */
213 #define VT1724_MT_PDMA1_SIZE 0x74 /* word */
214 #define VT1724_MT_PDMA1_COUNT 0x76 /* word */
215 
216 
217 unsigned char snd_vt1724_read_i2c(struct snd_ice1712 *ice, unsigned char dev, unsigned char addr);
218 void snd_vt1724_write_i2c(struct snd_ice1712 *ice, unsigned char dev, unsigned char addr, unsigned char data);
219 
220 #endif /* __SOUND_VT1724_H */
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