#include <sound/control.h>
#include <sound/ac97_codec.h>
#include <sound/rawmidi.h>
#include <sound/i2c.h>
#include <sound/pcm.h>
#include "ice1712.h"

Macros
#define	ICEREG1724(ice, x) ((ice)->port + VT1724_REG_##x)

#define	VT1724_REG_CONTROL 0x00 /* byte */

#define	VT1724_RESET 0x80 /* reset whole chip */

#define	VT1724_REG_IRQMASK 0x01 /* byte */

#define	VT1724_IRQ_MPU_RX 0x80

#define	VT1724_IRQ_MPU_TX 0x20

#define	VT1724_IRQ_MTPCM 0x10

#define	VT1724_REG_IRQSTAT 0x02 /* byte */

#define	VT1724_REG_SYS_CFG 0x04 /* byte - system configuration PCI60 on Envy24*/

#define	VT1724_CFG_CLOCK 0xc0

#define	VT1724_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz512 /

#define	VT1724_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz384 /

#define	VT1724_CFG_MPU401 0x20 /* MPU401 UARTs */

#define	VT1724_CFG_ADC_MASK 0x0c /* one, two or one and S/PDIF, stereo ADCs */

#define	VT1724_CFG_ADC_NONE 0x0c /* no ADCs */

#define	VT1724_CFG_DAC_MASK 0x03 /* one, two, three, four stereo DACs */

#define	VT1724_REG_AC97_CFG 0x05 /* byte */

#define	VT1724_CFG_PRO_I2S 0x80 /* multitrack converter: I2S or AC'97 */

#define	VT1724_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */

#define	VT1724_REG_I2S_FEATURES 0x06 /* byte */

#define	VT1724_CFG_I2S_VOLUME 0x80 /* volume/mute capability */

#define	VT1724_CFG_I2S_96KHZ 0x40 /* supports 96kHz sampling */

#define	VT1724_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */

#define	VT1724_CFG_I2S_192KHZ 0x08 /* supports 192kHz sampling */

#define	VT1724_CFG_I2S_OTHER 0x07 /* other I2S IDs */

#define	VT1724_REG_SPDIF_CFG 0x07 /* byte */

#define	VT1724_CFG_SPDIF_OUT_EN 0x80 /Internal S/PDIF output is enabled/

#define	VT1724_CFG_SPDIF_OUT_INT 0x40 /Internal S/PDIF output is implemented/

#define	VT1724_CFG_I2S_CHIPID 0x3c /* I2S chip ID */

#define	VT1724_CFG_SPDIF_IN 0x02 /* S/PDIF input is present */

#define	VT1724_CFG_SPDIF_OUT 0x01 /* External S/PDIF output is present */

#define	VT1724_REG_MPU_TXFIFO 0x0a /byte ro. number of bytes in TX fifo/

#define	VT1724_REG_MPU_RXFIFO 0x0b /byte ro. number of bytes in RX fifo/

#define	VT1724_REG_MPU_DATA 0x0c /* byte */

#define	VT1724_REG_MPU_CTRL 0x0d /* byte */

#define	VT1724_MPU_UART 0x01

#define	VT1724_MPU_TX_EMPTY 0x02

#define	VT1724_MPU_TX_FULL 0x04

#define	VT1724_MPU_RX_EMPTY 0x08

#define	VT1724_MPU_RX_FULL 0x10

#define	VT1724_REG_MPU_FIFO_WM 0x0e /byte set the high/low watermarks for RX/TX fifos/

#define	VT1724_MPU_RX_FIFO 0x20

#define	VT1724_MPU_FIFO_MASK 0x1f

#define	VT1724_REG_I2C_DEV_ADDR 0x10 /* byte */

#define	VT1724_I2C_WRITE 0x01 /* write direction */

#define	VT1724_REG_I2C_BYTE_ADDR 0x11 /* byte */

#define	VT1724_REG_I2C_DATA 0x12 /* byte */

#define	VT1724_REG_I2C_CTRL 0x13 /* byte */

#define	VT1724_I2C_EEPROM 0x80 /* 1 = EEPROM exists */

#define	VT1724_I2C_BUSY 0x01 /* busy bit */

#define	VT1724_REG_GPIO_DATA 0x14 /* word */

#define	VT1724_REG_GPIO_WRITE_MASK 0x16 /* word */

#define	VT1724_REG_GPIO_DIRECTION

#define	VT1724_REG_POWERDOWN 0x1c

#define	VT1724_REG_GPIO_DATA_22 0x1e /* byte direction for GPIO 16:22 */

#define	VT1724_REG_GPIO_WRITE_MASK_22 0x1f /* byte write mask for GPIO 16:22 */

#define	ICEMT1724(ice, x) ((ice)->profi_port + VT1724_MT_##x)

#define	VT1724_MT_IRQ 0x00 /* byte - interrupt mask */

#define	VT1724_MULTI_PDMA4 0x80 /* SPDIF Out / PDMA4 */

#define	VT1724_MULTI_PDMA3 0x40 /* PDMA3 */

#define	VT1724_MULTI_PDMA2 0x20 /* PDMA2 */

#define	VT1724_MULTI_PDMA1 0x10 /* PDMA1 */

#define	VT1724_MULTI_FIFO_ERR 0x08 /* DMA FIFO underrun/overrun. */

#define	VT1724_MULTI_RDMA1 0x04 /* RDMA1 (S/PDIF input) */

#define	VT1724_MULTI_RDMA0 0x02 /* RMDA0 */

#define	VT1724_MULTI_PDMA0 0x01 /* MC Interleave/PDMA0 */

#define	VT1724_MT_RATE 0x01 /* byte - sampling rate select */

#define	VT1724_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */

#define	VT1724_MT_I2S_FORMAT 0x02 /* byte - I2S data format */

#define	VT1724_MT_I2S_MCLK_128X 0x08

#define	VT1724_MT_I2S_FORMAT_MASK 0x03

#define	VT1724_MT_I2S_FORMAT_I2S 0x00

#define	VT1724_MT_DMA_INT_MASK 0x03 /* byte -DMA Interrupt Mask */

#define	VT1724_MT_AC97_INDEX 0x04 /* byte - AC'97 index */

#define	VT1724_MT_AC97_CMD 0x05 /* byte - AC'97 command & status */

#define	VT1724_AC97_COLD 0x80 /* cold reset */

#define	VT1724_AC97_WARM 0x40 /* warm reset */

#define	VT1724_AC97_WRITE 0x20 /* W: write, R: write in progress */

#define	VT1724_AC97_READ 0x10 /* W: read, R: read in progress */

#define	VT1724_AC97_READY 0x08 /* codec ready status bit */

#define	VT1724_AC97_ID_MASK 0x03 /* codec id mask */

#define	VT1724_MT_AC97_DATA 0x06 /* word - AC'97 data */

#define	VT1724_MT_PLAYBACK_ADDR 0x10 /* dword - playback address */

#define	VT1724_MT_PLAYBACK_SIZE 0x14 /* dword - playback size */

#define	VT1724_MT_DMA_CONTROL 0x18 /* byte - control */

#define	VT1724_PDMA4_START 0x80 /* SPDIF out / PDMA4 start */

#define	VT1724_PDMA3_START 0x40 /* PDMA3 start */

#define	VT1724_PDMA2_START 0x20 /* PDMA2 start */

#define	VT1724_PDMA1_START 0x10 /* PDMA1 start */

#define	VT1724_RDMA1_START 0x04 /* RDMA1 start */

#define	VT1724_RDMA0_START 0x02 /* RMDA0 start */

#define	VT1724_PDMA0_START 0x01 /* MC Interleave / PDMA0 start */

#define	VT1724_MT_BURST 0x19 /* Interleaved playback DMA Active streams / PCI burst size */

#define	VT1724_MT_DMA_FIFO_ERR 0x1a /Global playback and record DMA FIFO Underrun/Overrun /

#define	VT1724_PDMA4_UNDERRUN 0x80

#define	VT1724_PDMA2_UNDERRUN 0x40

#define	VT1724_PDMA3_UNDERRUN 0x20

#define	VT1724_PDMA1_UNDERRUN 0x10

#define	VT1724_RDMA1_UNDERRUN 0x04

#define	VT1724_RDMA0_UNDERRUN 0x02

#define	VT1724_PDMA0_UNDERRUN 0x01

#define	VT1724_MT_DMA_PAUSE 0x1b /Global playback and record DMA FIFO pause/resume /

#define	VT1724_PDMA4_PAUSE 0x80

#define	VT1724_PDMA3_PAUSE 0x40

#define	VT1724_PDMA2_PAUSE 0x20

#define	VT1724_PDMA1_PAUSE 0x10

#define	VT1724_RDMA1_PAUSE 0x04

#define	VT1724_RDMA0_PAUSE 0x02

#define	VT1724_PDMA0_PAUSE 0x01

#define	VT1724_MT_PLAYBACK_COUNT 0x1c /* word - playback count */

#define	VT1724_MT_CAPTURE_ADDR 0x20 /* dword - capture address */

#define	VT1724_MT_CAPTURE_SIZE 0x24 /* word - capture size */

#define	VT1724_MT_CAPTURE_COUNT 0x26 /* word - capture count */

#define	VT1724_MT_ROUTE_PLAYBACK 0x2c /* word */

#define	VT1724_MT_RDMA1_ADDR 0x30 /* dword - RDMA1 capture address */

#define	VT1724_MT_RDMA1_SIZE 0x34 /* word - RDMA1 capture size */

#define	VT1724_MT_RDMA1_COUNT 0x36 /* word - RDMA1 capture count */

#define	VT1724_MT_SPDIF_CTRL 0x3c /* word */

#define	VT1724_MT_MONITOR_PEAKINDEX 0x3e /* byte */

#define	VT1724_MT_MONITOR_PEAKDATA 0x3f /* byte */

#define	VT1724_MT_PDMA4_ADDR 0x40 /* dword */

#define	VT1724_MT_PDMA4_SIZE 0x44 /* word */

#define	VT1724_MT_PDMA4_COUNT 0x46 /* word */

#define	VT1724_MT_PDMA3_ADDR 0x50 /* dword */

#define	VT1724_MT_PDMA3_SIZE 0x54 /* word */

#define	VT1724_MT_PDMA3_COUNT 0x56 /* word */

#define	VT1724_MT_PDMA2_ADDR 0x60 /* dword */

#define	VT1724_MT_PDMA2_SIZE 0x64 /* word */

#define	VT1724_MT_PDMA2_COUNT 0x66 /* word */

#define	VT1724_MT_PDMA1_ADDR 0x70 /* dword */

#define	VT1724_MT_PDMA1_SIZE 0x74 /* word */

#define	VT1724_MT_PDMA1_COUNT 0x76 /* word */

Enumerations
enum	{ ICE_EEP2_SYSCONF = 0, ICE_EEP2_ACLINK, ICE_EEP2_I2S, ICE_EEP2_SPDIF, ICE_EEP2_GPIO_DIR, ICE_EEP2_GPIO_DIR1, ICE_EEP2_GPIO_DIR2, ICE_EEP2_GPIO_MASK, ICE_EEP2_GPIO_MASK1, ICE_EEP2_GPIO_MASK2, ICE_EEP2_GPIO_STATE, ICE_EEP2_GPIO_STATE1, ICE_EEP2_GPIO_STATE2 }

Functions
unsigned char	snd_vt1724_read_i2c (struct snd_ice1712 *ice, unsigned char dev, unsigned char addr)

void	snd_vt1724_write_i2c (struct snd_ice1712 *ice, unsigned char dev, unsigned char addr, unsigned char data)

Macro Definition Documentation

#define ICEMT1724	(	ice,
		x
	)	((ice)->profi_port + VT1724_MT_##x)

Definition at line 129 of file envy24ht.h.

#define ICEREG1724	(	ice,
		x
	)	((ice)->port + VT1724_REG_##x)

Definition at line 53 of file envy24ht.h.

#define VT1724_AC97_COLD 0x80 /* cold reset */

Definition at line 151 of file envy24ht.h.

#define VT1724_AC97_ID_MASK 0x03 /* codec id mask */

Definition at line 156 of file envy24ht.h.

#define VT1724_AC97_READ 0x10 /* W: read, R: read in progress */

Definition at line 154 of file envy24ht.h.

#define VT1724_AC97_READY 0x08 /* codec ready status bit */

Definition at line 155 of file envy24ht.h.

#define VT1724_AC97_WARM 0x40 /* warm reset */

Definition at line 152 of file envy24ht.h.

#define VT1724_AC97_WRITE 0x20 /* W: write, R: write in progress */

Definition at line 153 of file envy24ht.h.

#define VT1724_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */

Definition at line 74 of file envy24ht.h.

#define VT1724_CFG_ADC_MASK 0x0c /* one, two or one and S/PDIF, stereo ADCs */

Definition at line 68 of file envy24ht.h.

#define VT1724_CFG_ADC_NONE 0x0c /* no ADCs */

Definition at line 69 of file envy24ht.h.

#define VT1724_CFG_CLOCK 0xc0

Definition at line 64 of file envy24ht.h.

#define VT1724_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */

Definition at line 66 of file envy24ht.h.

#define VT1724_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */

Definition at line 65 of file envy24ht.h.

#define VT1724_CFG_DAC_MASK 0x03 /* one, two, three, four stereo DACs */

Definition at line 70 of file envy24ht.h.

#define VT1724_CFG_I2S_192KHZ 0x08 /* supports 192kHz sampling */

Definition at line 80 of file envy24ht.h.

#define VT1724_CFG_I2S_96KHZ 0x40 /* supports 96kHz sampling */

Definition at line 78 of file envy24ht.h.

#define VT1724_CFG_I2S_CHIPID 0x3c /* I2S chip ID */

Definition at line 86 of file envy24ht.h.

#define VT1724_CFG_I2S_OTHER 0x07 /* other I2S IDs */

Definition at line 81 of file envy24ht.h.

#define VT1724_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */

Definition at line 79 of file envy24ht.h.

#define VT1724_CFG_I2S_VOLUME 0x80 /* volume/mute capability */

Definition at line 77 of file envy24ht.h.

#define VT1724_CFG_MPU401 0x20 /* MPU401 UARTs */

Definition at line 67 of file envy24ht.h.

#define VT1724_CFG_PRO_I2S 0x80 /* multitrack converter: I2S or AC'97 */

Definition at line 73 of file envy24ht.h.

#define VT1724_CFG_SPDIF_IN 0x02 /* S/PDIF input is present */

Definition at line 87 of file envy24ht.h.

#define VT1724_CFG_SPDIF_OUT 0x01 /* External S/PDIF output is present */

Definition at line 88 of file envy24ht.h.

#define VT1724_CFG_SPDIF_OUT_EN 0x80 /*Internal S/PDIF output is enabled*/

Definition at line 84 of file envy24ht.h.

#define VT1724_CFG_SPDIF_OUT_INT 0x40 /*Internal S/PDIF output is implemented*/

Definition at line 85 of file envy24ht.h.

#define VT1724_I2C_BUSY 0x01 /* busy bit */

Definition at line 115 of file envy24ht.h.

#define VT1724_I2C_EEPROM 0x80 /* 1 = EEPROM exists */

Definition at line 114 of file envy24ht.h.

#define VT1724_I2C_WRITE 0x01 /* write direction */

Definition at line 110 of file envy24ht.h.

#define VT1724_IRQ_MPU_RX 0x80

Definition at line 58 of file envy24ht.h.

#define VT1724_IRQ_MPU_TX 0x20

Definition at line 59 of file envy24ht.h.

#define VT1724_IRQ_MTPCM 0x10

Definition at line 60 of file envy24ht.h.

#define VT1724_MPU_FIFO_MASK 0x1f

Definition at line 107 of file envy24ht.h.

#define VT1724_MPU_RX_EMPTY 0x08

Definition at line 102 of file envy24ht.h.

#define VT1724_MPU_RX_FIFO 0x20

Definition at line 106 of file envy24ht.h.

#define VT1724_MPU_RX_FULL 0x10

Definition at line 103 of file envy24ht.h.

#define VT1724_MPU_TX_EMPTY 0x02

Definition at line 100 of file envy24ht.h.

#define VT1724_MPU_TX_FULL 0x04

Definition at line 101 of file envy24ht.h.

#define VT1724_MPU_UART 0x01

Definition at line 99 of file envy24ht.h.

#define VT1724_MT_AC97_CMD 0x05 /* byte - AC'97 command & status */

Definition at line 150 of file envy24ht.h.

#define VT1724_MT_AC97_DATA 0x06 /* word - AC'97 data */

Definition at line 157 of file envy24ht.h.

#define VT1724_MT_AC97_INDEX 0x04 /* byte - AC'97 index */

Definition at line 149 of file envy24ht.h.

#define VT1724_MT_BURST 0x19 /* Interleaved playback DMA Active streams / PCI burst size */

Definition at line 168 of file envy24ht.h.

#define VT1724_MT_CAPTURE_ADDR 0x20 /* dword - capture address */

Definition at line 186 of file envy24ht.h.

#define VT1724_MT_CAPTURE_COUNT 0x26 /* word - capture count */

Definition at line 188 of file envy24ht.h.

#define VT1724_MT_CAPTURE_SIZE 0x24 /* word - capture size */

Definition at line 187 of file envy24ht.h.

#define VT1724_MT_DMA_CONTROL 0x18 /* byte - control */

Definition at line 160 of file envy24ht.h.

#define VT1724_MT_DMA_FIFO_ERR 0x1a /*Global playback and record DMA FIFO Underrun/Overrun */

Definition at line 169 of file envy24ht.h.

#define VT1724_MT_DMA_INT_MASK 0x03 /* byte -DMA Interrupt Mask */

Definition at line 147 of file envy24ht.h.

#define VT1724_MT_DMA_PAUSE 0x1b /*Global playback and record DMA FIFO pause/resume */

Definition at line 177 of file envy24ht.h.

#define VT1724_MT_I2S_FORMAT 0x02 /* byte - I2S data format */

Definition at line 143 of file envy24ht.h.

#define VT1724_MT_I2S_FORMAT_I2S 0x00

Definition at line 146 of file envy24ht.h.

#define VT1724_MT_I2S_FORMAT_MASK 0x03

Definition at line 145 of file envy24ht.h.

#define VT1724_MT_I2S_MCLK_128X 0x08

Definition at line 144 of file envy24ht.h.

#define VT1724_MT_IRQ 0x00 /* byte - interrupt mask */

Definition at line 131 of file envy24ht.h.

#define VT1724_MT_MONITOR_PEAKDATA 0x3f /* byte */

Definition at line 198 of file envy24ht.h.

#define VT1724_MT_MONITOR_PEAKINDEX 0x3e /* byte */

Definition at line 197 of file envy24ht.h.

#define VT1724_MT_PDMA1_ADDR 0x70 /* dword */

Definition at line 210 of file envy24ht.h.

#define VT1724_MT_PDMA1_COUNT 0x76 /* word */

Definition at line 212 of file envy24ht.h.

#define VT1724_MT_PDMA1_SIZE 0x74 /* word */

Definition at line 211 of file envy24ht.h.

#define VT1724_MT_PDMA2_ADDR 0x60 /* dword */

Definition at line 207 of file envy24ht.h.

#define VT1724_MT_PDMA2_COUNT 0x66 /* word */

Definition at line 209 of file envy24ht.h.

#define VT1724_MT_PDMA2_SIZE 0x64 /* word */

Definition at line 208 of file envy24ht.h.

#define VT1724_MT_PDMA3_ADDR 0x50 /* dword */

Definition at line 204 of file envy24ht.h.

#define VT1724_MT_PDMA3_COUNT 0x56 /* word */

Definition at line 206 of file envy24ht.h.

#define VT1724_MT_PDMA3_SIZE 0x54 /* word */

Definition at line 205 of file envy24ht.h.

#define VT1724_MT_PDMA4_ADDR 0x40 /* dword */

Definition at line 201 of file envy24ht.h.

#define VT1724_MT_PDMA4_COUNT 0x46 /* word */

Definition at line 203 of file envy24ht.h.

#define VT1724_MT_PDMA4_SIZE 0x44 /* word */

Definition at line 202 of file envy24ht.h.

#define VT1724_MT_PLAYBACK_ADDR 0x10 /* dword - playback address */

Definition at line 158 of file envy24ht.h.

#define VT1724_MT_PLAYBACK_COUNT 0x1c /* word - playback count */

Definition at line 185 of file envy24ht.h.

#define VT1724_MT_PLAYBACK_SIZE 0x14 /* dword - playback size */

Definition at line 159 of file envy24ht.h.

#define VT1724_MT_RATE 0x01 /* byte - sampling rate select */

Definition at line 141 of file envy24ht.h.

#define VT1724_MT_RDMA1_ADDR 0x30 /* dword - RDMA1 capture address */

Definition at line 192 of file envy24ht.h.

#define VT1724_MT_RDMA1_COUNT 0x36 /* word - RDMA1 capture count */

Definition at line 194 of file envy24ht.h.

#define VT1724_MT_RDMA1_SIZE 0x34 /* word - RDMA1 capture size */

Definition at line 193 of file envy24ht.h.

#define VT1724_MT_ROUTE_PLAYBACK 0x2c /* word */

Definition at line 190 of file envy24ht.h.

#define VT1724_MT_SPDIF_CTRL 0x3c /* word */

Definition at line 196 of file envy24ht.h.

#define VT1724_MULTI_FIFO_ERR 0x08 /* DMA FIFO underrun/overrun. */

Definition at line 136 of file envy24ht.h.

#define VT1724_MULTI_PDMA0 0x01 /* MC Interleave/PDMA0 */

Definition at line 139 of file envy24ht.h.

#define VT1724_MULTI_PDMA1 0x10 /* PDMA1 */

Definition at line 135 of file envy24ht.h.

#define VT1724_MULTI_PDMA2 0x20 /* PDMA2 */

Definition at line 134 of file envy24ht.h.

#define VT1724_MULTI_PDMA3 0x40 /* PDMA3 */

Definition at line 133 of file envy24ht.h.

#define VT1724_MULTI_PDMA4 0x80 /* SPDIF Out / PDMA4 */

Definition at line 132 of file envy24ht.h.

#define VT1724_MULTI_RDMA0 0x02 /* RMDA0 */

Definition at line 138 of file envy24ht.h.

#define VT1724_MULTI_RDMA1 0x04 /* RDMA1 (S/PDIF input) */

Definition at line 137 of file envy24ht.h.

#define VT1724_PDMA0_PAUSE 0x01

Definition at line 184 of file envy24ht.h.

#define VT1724_PDMA0_START 0x01 /* MC Interleave / PDMA0 start */

Definition at line 167 of file envy24ht.h.

#define VT1724_PDMA0_UNDERRUN 0x01

Definition at line 176 of file envy24ht.h.

#define VT1724_PDMA1_PAUSE 0x10

Definition at line 181 of file envy24ht.h.

#define VT1724_PDMA1_START 0x10 /* PDMA1 start */

Definition at line 164 of file envy24ht.h.

#define VT1724_PDMA1_UNDERRUN 0x10

Definition at line 173 of file envy24ht.h.

#define VT1724_PDMA2_PAUSE 0x20

Definition at line 180 of file envy24ht.h.

#define VT1724_PDMA2_START 0x20 /* PDMA2 start */

Definition at line 163 of file envy24ht.h.

#define VT1724_PDMA2_UNDERRUN 0x40

Definition at line 171 of file envy24ht.h.

#define VT1724_PDMA3_PAUSE 0x40

Definition at line 179 of file envy24ht.h.

#define VT1724_PDMA3_START 0x40 /* PDMA3 start */

Definition at line 162 of file envy24ht.h.

#define VT1724_PDMA3_UNDERRUN 0x20

Definition at line 172 of file envy24ht.h.

#define VT1724_PDMA4_PAUSE 0x80

Definition at line 178 of file envy24ht.h.

#define VT1724_PDMA4_START 0x80 /* SPDIF out / PDMA4 start */

Definition at line 161 of file envy24ht.h.

#define VT1724_PDMA4_UNDERRUN 0x80

Definition at line 170 of file envy24ht.h.

#define VT1724_RDMA0_PAUSE 0x02

Definition at line 183 of file envy24ht.h.

#define VT1724_RDMA0_START 0x02 /* RMDA0 start */

Definition at line 166 of file envy24ht.h.

#define VT1724_RDMA0_UNDERRUN 0x02

Definition at line 175 of file envy24ht.h.

#define VT1724_RDMA1_PAUSE 0x04

Definition at line 182 of file envy24ht.h.

#define VT1724_RDMA1_START 0x04 /* RDMA1 start */

Definition at line 165 of file envy24ht.h.

#define VT1724_RDMA1_UNDERRUN 0x04

Definition at line 174 of file envy24ht.h.

#define VT1724_REG_AC97_CFG 0x05 /* byte */

Definition at line 72 of file envy24ht.h.

#define VT1724_REG_CONTROL 0x00 /* byte */

Definition at line 55 of file envy24ht.h.

#define VT1724_REG_GPIO_DATA 0x14 /* word */

Definition at line 117 of file envy24ht.h.

#define VT1724_REG_GPIO_DATA_22 0x1e /* byte direction for GPIO 16:22 */

Definition at line 121 of file envy24ht.h.

#define VT1724_REG_GPIO_DIRECTION

Value:

0x18 /* dword? (3 bytes) 0=input 1=output. 
                        bit3 - during reset used for Eeprom power-on strapping
                        if TESTEN# pin active, bit 2 always input*/

Definition at line 119 of file envy24ht.h.

#define VT1724_REG_GPIO_WRITE_MASK 0x16 /* word */

Definition at line 118 of file envy24ht.h.

#define VT1724_REG_GPIO_WRITE_MASK_22 0x1f /* byte write mask for GPIO 16:22 */

Definition at line 122 of file envy24ht.h.

#define VT1724_REG_I2C_BYTE_ADDR 0x11 /* byte */

Definition at line 111 of file envy24ht.h.

#define VT1724_REG_I2C_CTRL 0x13 /* byte */

Definition at line 113 of file envy24ht.h.

#define VT1724_REG_I2C_DATA 0x12 /* byte */

Definition at line 112 of file envy24ht.h.

#define VT1724_REG_I2C_DEV_ADDR 0x10 /* byte */

Definition at line 109 of file envy24ht.h.

#define VT1724_REG_I2S_FEATURES 0x06 /* byte */

Definition at line 76 of file envy24ht.h.

#define VT1724_REG_IRQMASK 0x01 /* byte */

Definition at line 57 of file envy24ht.h.

#define VT1724_REG_IRQSTAT 0x02 /* byte */

Definition at line 61 of file envy24ht.h.

#define VT1724_REG_MPU_CTRL 0x0d /* byte */

Definition at line 98 of file envy24ht.h.

#define VT1724_REG_MPU_DATA 0x0c /* byte */

Definition at line 97 of file envy24ht.h.

#define VT1724_REG_MPU_FIFO_WM 0x0e /*byte set the high/low watermarks for RX/TX fifos*/

Definition at line 105 of file envy24ht.h.

#define VT1724_REG_MPU_RXFIFO 0x0b /*byte ro. number of bytes in RX fifo*/

Definition at line 95 of file envy24ht.h.

#define VT1724_REG_MPU_TXFIFO 0x0a /*byte ro. number of bytes in TX fifo*/

Definition at line 94 of file envy24ht.h.

#define VT1724_REG_POWERDOWN 0x1c

Definition at line 120 of file envy24ht.h.

#define VT1724_REG_SPDIF_CFG 0x07 /* byte */

Definition at line 83 of file envy24ht.h.

#define VT1724_REG_SYS_CFG 0x04 /* byte - system configuration PCI60 on Envy24*/

Definition at line 63 of file envy24ht.h.

#define VT1724_RESET 0x80 /* reset whole chip */

Definition at line 56 of file envy24ht.h.

#define VT1724_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */

Definition at line 142 of file envy24ht.h.

Enumeration Type Documentation

anonymous enum

Enumerator:

ICE_EEP2_SYSCONF
ICE_EEP2_ACLINK
ICE_EEP2_I2S
ICE_EEP2_SPDIF
ICE_EEP2_GPIO_DIR
ICE_EEP2_GPIO_DIR1
ICE_EEP2_GPIO_DIR2
ICE_EEP2_GPIO_MASK
ICE_EEP2_GPIO_MASK1
ICE_EEP2_GPIO_MASK2
ICE_EEP2_GPIO_STATE
ICE_EEP2_GPIO_STATE1
ICE_EEP2_GPIO_STATE2

Definition at line 33 of file envy24ht.h.

Function Documentation

unsigned char snd_vt1724_read_i2c	(	struct snd_ice1712 *	ice,
		unsigned char	dev,
		unsigned char	addr
	)

Definition at line 2276 of file ice1724.c.

void snd_vt1724_write_i2c	(	struct snd_ice1712 *	ice,
		unsigned char	dev,
		unsigned char	addr,
		unsigned char	data
	)

Definition at line 2294 of file ice1724.c.

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation