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Data Structures | Macros | Functions
ep93xx_dma.c File Reference
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/dmaengine.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/platform_data/dma-ep93xx.h>
#include "dmaengine.h"

Go to the source code of this file.

Data Structures

struct  ep93xx_dma_desc
 
struct  ep93xx_dma_chan
 
struct  ep93xx_dma_engine
 

Macros

#define M2P_CONTROL   0x0000
 
#define M2P_CONTROL_STALLINT   BIT(0)
 
#define M2P_CONTROL_NFBINT   BIT(1)
 
#define M2P_CONTROL_CH_ERROR_INT   BIT(3)
 
#define M2P_CONTROL_ENABLE   BIT(4)
 
#define M2P_CONTROL_ICE   BIT(6)
 
#define M2P_INTERRUPT   0x0004
 
#define M2P_INTERRUPT_STALL   BIT(0)
 
#define M2P_INTERRUPT_NFB   BIT(1)
 
#define M2P_INTERRUPT_ERROR   BIT(3)
 
#define M2P_PPALLOC   0x0008
 
#define M2P_STATUS   0x000c
 
#define M2P_MAXCNT0   0x0020
 
#define M2P_BASE0   0x0024
 
#define M2P_MAXCNT1   0x0030
 
#define M2P_BASE1   0x0034
 
#define M2P_STATE_IDLE   0
 
#define M2P_STATE_STALL   1
 
#define M2P_STATE_ON   2
 
#define M2P_STATE_NEXT   3
 
#define M2M_CONTROL   0x0000
 
#define M2M_CONTROL_DONEINT   BIT(2)
 
#define M2M_CONTROL_ENABLE   BIT(3)
 
#define M2M_CONTROL_START   BIT(4)
 
#define M2M_CONTROL_DAH   BIT(11)
 
#define M2M_CONTROL_SAH   BIT(12)
 
#define M2M_CONTROL_PW_SHIFT   9
 
#define M2M_CONTROL_PW_8   (0 << M2M_CONTROL_PW_SHIFT)
 
#define M2M_CONTROL_PW_16   (1 << M2M_CONTROL_PW_SHIFT)
 
#define M2M_CONTROL_PW_32   (2 << M2M_CONTROL_PW_SHIFT)
 
#define M2M_CONTROL_PW_MASK   (3 << M2M_CONTROL_PW_SHIFT)
 
#define M2M_CONTROL_TM_SHIFT   13
 
#define M2M_CONTROL_TM_TX   (1 << M2M_CONTROL_TM_SHIFT)
 
#define M2M_CONTROL_TM_RX   (2 << M2M_CONTROL_TM_SHIFT)
 
#define M2M_CONTROL_NFBINT   BIT(21)
 
#define M2M_CONTROL_RSS_SHIFT   22
 
#define M2M_CONTROL_RSS_SSPRX   (1 << M2M_CONTROL_RSS_SHIFT)
 
#define M2M_CONTROL_RSS_SSPTX   (2 << M2M_CONTROL_RSS_SHIFT)
 
#define M2M_CONTROL_RSS_IDE   (3 << M2M_CONTROL_RSS_SHIFT)
 
#define M2M_CONTROL_NO_HDSK   BIT(24)
 
#define M2M_CONTROL_PWSC_SHIFT   25
 
#define M2M_INTERRUPT   0x0004
 
#define M2M_INTERRUPT_MASK   6
 
#define M2M_STATUS   0x000c
 
#define M2M_STATUS_CTL_SHIFT   1
 
#define M2M_STATUS_CTL_IDLE   (0 << M2M_STATUS_CTL_SHIFT)
 
#define M2M_STATUS_CTL_STALL   (1 << M2M_STATUS_CTL_SHIFT)
 
#define M2M_STATUS_CTL_MEMRD   (2 << M2M_STATUS_CTL_SHIFT)
 
#define M2M_STATUS_CTL_MEMWR   (3 << M2M_STATUS_CTL_SHIFT)
 
#define M2M_STATUS_CTL_BWCWAIT   (4 << M2M_STATUS_CTL_SHIFT)
 
#define M2M_STATUS_CTL_MASK   (7 << M2M_STATUS_CTL_SHIFT)
 
#define M2M_STATUS_BUF_SHIFT   4
 
#define M2M_STATUS_BUF_NO   (0 << M2M_STATUS_BUF_SHIFT)
 
#define M2M_STATUS_BUF_ON   (1 << M2M_STATUS_BUF_SHIFT)
 
#define M2M_STATUS_BUF_NEXT   (2 << M2M_STATUS_BUF_SHIFT)
 
#define M2M_STATUS_BUF_MASK   (3 << M2M_STATUS_BUF_SHIFT)
 
#define M2M_STATUS_DONE   BIT(6)
 
#define M2M_BCR0   0x0010
 
#define M2M_BCR1   0x0014
 
#define M2M_SAR_BASE0   0x0018
 
#define M2M_SAR_BASE1   0x001c
 
#define M2M_DAR_BASE0   0x002c
 
#define M2M_DAR_BASE1   0x0030
 
#define DMA_MAX_CHAN_BYTES   0xffff
 
#define DMA_MAX_CHAN_DESCRIPTORS   32
 
#define EP93XX_DMA_IS_CYCLIC   0
 
#define INTERRUPT_UNKNOWN   0
 
#define INTERRUPT_DONE   1
 
#define INTERRUPT_NEXT_BUFFER   2
 

Functions

 subsys_initcall (ep93xx_dma_module_init)
 
 MODULE_AUTHOR ("Mika Westerberg <[email protected]>")
 
 MODULE_DESCRIPTION ("EP93xx DMA driver")
 
 MODULE_LICENSE ("GPL")
 

Macro Definition Documentation

#define DMA_MAX_CHAN_BYTES   0xffff

Definition at line 107 of file ep93xx_dma.c.

#define DMA_MAX_CHAN_DESCRIPTORS   32

Definition at line 108 of file ep93xx_dma.c.

#define EP93XX_DMA_IS_CYCLIC   0

Definition at line 174 of file ep93xx_dma.c.

#define INTERRUPT_DONE   1

Definition at line 208 of file ep93xx_dma.c.

#define INTERRUPT_NEXT_BUFFER   2

Definition at line 209 of file ep93xx_dma.c.

#define INTERRUPT_UNKNOWN   0

Definition at line 207 of file ep93xx_dma.c.

#define M2M_BCR0   0x0010

Definition at line 100 of file ep93xx_dma.c.

#define M2M_BCR1   0x0014

Definition at line 101 of file ep93xx_dma.c.

#define M2M_CONTROL   0x0000

Definition at line 60 of file ep93xx_dma.c.

#define M2M_CONTROL_DAH   BIT(11)

Definition at line 64 of file ep93xx_dma.c.

#define M2M_CONTROL_DONEINT   BIT(2)

Definition at line 61 of file ep93xx_dma.c.

#define M2M_CONTROL_ENABLE   BIT(3)

Definition at line 62 of file ep93xx_dma.c.

#define M2M_CONTROL_NFBINT   BIT(21)

Definition at line 74 of file ep93xx_dma.c.

#define M2M_CONTROL_NO_HDSK   BIT(24)

Definition at line 79 of file ep93xx_dma.c.

#define M2M_CONTROL_PW_16   (1 << M2M_CONTROL_PW_SHIFT)

Definition at line 68 of file ep93xx_dma.c.

#define M2M_CONTROL_PW_32   (2 << M2M_CONTROL_PW_SHIFT)

Definition at line 69 of file ep93xx_dma.c.

#define M2M_CONTROL_PW_8   (0 << M2M_CONTROL_PW_SHIFT)

Definition at line 67 of file ep93xx_dma.c.

#define M2M_CONTROL_PW_MASK   (3 << M2M_CONTROL_PW_SHIFT)

Definition at line 70 of file ep93xx_dma.c.

#define M2M_CONTROL_PW_SHIFT   9

Definition at line 66 of file ep93xx_dma.c.

#define M2M_CONTROL_PWSC_SHIFT   25

Definition at line 80 of file ep93xx_dma.c.

#define M2M_CONTROL_RSS_IDE   (3 << M2M_CONTROL_RSS_SHIFT)

Definition at line 78 of file ep93xx_dma.c.

#define M2M_CONTROL_RSS_SHIFT   22

Definition at line 75 of file ep93xx_dma.c.

#define M2M_CONTROL_RSS_SSPRX   (1 << M2M_CONTROL_RSS_SHIFT)

Definition at line 76 of file ep93xx_dma.c.

#define M2M_CONTROL_RSS_SSPTX   (2 << M2M_CONTROL_RSS_SHIFT)

Definition at line 77 of file ep93xx_dma.c.

#define M2M_CONTROL_SAH   BIT(12)

Definition at line 65 of file ep93xx_dma.c.

#define M2M_CONTROL_START   BIT(4)

Definition at line 63 of file ep93xx_dma.c.

#define M2M_CONTROL_TM_RX   (2 << M2M_CONTROL_TM_SHIFT)

Definition at line 73 of file ep93xx_dma.c.

#define M2M_CONTROL_TM_SHIFT   13

Definition at line 71 of file ep93xx_dma.c.

#define M2M_CONTROL_TM_TX   (1 << M2M_CONTROL_TM_SHIFT)

Definition at line 72 of file ep93xx_dma.c.

#define M2M_DAR_BASE0   0x002c

Definition at line 104 of file ep93xx_dma.c.

#define M2M_DAR_BASE1   0x0030

Definition at line 105 of file ep93xx_dma.c.

#define M2M_INTERRUPT   0x0004

Definition at line 82 of file ep93xx_dma.c.

#define M2M_INTERRUPT_MASK   6

Definition at line 83 of file ep93xx_dma.c.

#define M2M_SAR_BASE0   0x0018

Definition at line 102 of file ep93xx_dma.c.

#define M2M_SAR_BASE1   0x001c

Definition at line 103 of file ep93xx_dma.c.

#define M2M_STATUS   0x000c

Definition at line 85 of file ep93xx_dma.c.

#define M2M_STATUS_BUF_MASK   (3 << M2M_STATUS_BUF_SHIFT)

Definition at line 97 of file ep93xx_dma.c.

#define M2M_STATUS_BUF_NEXT   (2 << M2M_STATUS_BUF_SHIFT)

Definition at line 96 of file ep93xx_dma.c.

#define M2M_STATUS_BUF_NO   (0 << M2M_STATUS_BUF_SHIFT)

Definition at line 94 of file ep93xx_dma.c.

#define M2M_STATUS_BUF_ON   (1 << M2M_STATUS_BUF_SHIFT)

Definition at line 95 of file ep93xx_dma.c.

#define M2M_STATUS_BUF_SHIFT   4

Definition at line 93 of file ep93xx_dma.c.

#define M2M_STATUS_CTL_BWCWAIT   (4 << M2M_STATUS_CTL_SHIFT)

Definition at line 91 of file ep93xx_dma.c.

#define M2M_STATUS_CTL_IDLE   (0 << M2M_STATUS_CTL_SHIFT)

Definition at line 87 of file ep93xx_dma.c.

#define M2M_STATUS_CTL_MASK   (7 << M2M_STATUS_CTL_SHIFT)

Definition at line 92 of file ep93xx_dma.c.

#define M2M_STATUS_CTL_MEMRD   (2 << M2M_STATUS_CTL_SHIFT)

Definition at line 89 of file ep93xx_dma.c.

#define M2M_STATUS_CTL_MEMWR   (3 << M2M_STATUS_CTL_SHIFT)

Definition at line 90 of file ep93xx_dma.c.

#define M2M_STATUS_CTL_SHIFT   1

Definition at line 86 of file ep93xx_dma.c.

#define M2M_STATUS_CTL_STALL   (1 << M2M_STATUS_CTL_SHIFT)

Definition at line 88 of file ep93xx_dma.c.

#define M2M_STATUS_DONE   BIT(6)

Definition at line 98 of file ep93xx_dma.c.

#define M2P_BASE0   0x0024

Definition at line 50 of file ep93xx_dma.c.

#define M2P_BASE1   0x0034

Definition at line 52 of file ep93xx_dma.c.

#define M2P_CONTROL   0x0000

Definition at line 34 of file ep93xx_dma.c.

#define M2P_CONTROL_CH_ERROR_INT   BIT(3)

Definition at line 37 of file ep93xx_dma.c.

#define M2P_CONTROL_ENABLE   BIT(4)

Definition at line 38 of file ep93xx_dma.c.

#define M2P_CONTROL_ICE   BIT(6)

Definition at line 39 of file ep93xx_dma.c.

#define M2P_CONTROL_NFBINT   BIT(1)

Definition at line 36 of file ep93xx_dma.c.

#define M2P_CONTROL_STALLINT   BIT(0)

Definition at line 35 of file ep93xx_dma.c.

#define M2P_INTERRUPT   0x0004

Definition at line 41 of file ep93xx_dma.c.

#define M2P_INTERRUPT_ERROR   BIT(3)

Definition at line 44 of file ep93xx_dma.c.

#define M2P_INTERRUPT_NFB   BIT(1)

Definition at line 43 of file ep93xx_dma.c.

#define M2P_INTERRUPT_STALL   BIT(0)

Definition at line 42 of file ep93xx_dma.c.

#define M2P_MAXCNT0   0x0020

Definition at line 49 of file ep93xx_dma.c.

#define M2P_MAXCNT1   0x0030

Definition at line 51 of file ep93xx_dma.c.

#define M2P_PPALLOC   0x0008

Definition at line 46 of file ep93xx_dma.c.

#define M2P_STATE_IDLE   0

Definition at line 54 of file ep93xx_dma.c.

#define M2P_STATE_NEXT   3

Definition at line 57 of file ep93xx_dma.c.

#define M2P_STATE_ON   2

Definition at line 56 of file ep93xx_dma.c.

#define M2P_STATE_STALL   1

Definition at line 55 of file ep93xx_dma.c.

#define M2P_STATUS   0x000c

Definition at line 47 of file ep93xx_dma.c.

Function Documentation

MODULE_AUTHOR ( "Mika Westerberg <[email protected]>"  )
MODULE_DESCRIPTION ( "EP93xx DMA driver )
MODULE_LICENSE ( "GPL"  )
subsys_initcall ( ep93xx_dma_module_init  )