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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | EXYNOS_DP_TX_SW_RESET 0x14 |
| #define | EXYNOS_DP_FUNC_EN_1 0x18 |
| #define | EXYNOS_DP_FUNC_EN_2 0x1C |
| #define | EXYNOS_DP_VIDEO_CTL_1 0x20 |
| #define | EXYNOS_DP_VIDEO_CTL_2 0x24 |
| #define | EXYNOS_DP_VIDEO_CTL_3 0x28 |
| #define | EXYNOS_DP_VIDEO_CTL_8 0x3C |
| #define | EXYNOS_DP_VIDEO_CTL_10 0x44 |
| #define | EXYNOS_DP_LANE_MAP 0x35C |
| #define | EXYNOS_DP_ANALOG_CTL_1 0x370 |
| #define | EXYNOS_DP_ANALOG_CTL_2 0x374 |
| #define | EXYNOS_DP_ANALOG_CTL_3 0x378 |
| #define | EXYNOS_DP_PLL_FILTER_CTL_1 0x37C |
| #define | EXYNOS_DP_TX_AMP_TUNING_CTL 0x380 |
| #define | EXYNOS_DP_AUX_HW_RETRY_CTL 0x390 |
| #define | EXYNOS_DP_COMMON_INT_STA_1 0x3C4 |
| #define | EXYNOS_DP_COMMON_INT_STA_2 0x3C8 |
| #define | EXYNOS_DP_COMMON_INT_STA_3 0x3CC |
| #define | EXYNOS_DP_COMMON_INT_STA_4 0x3D0 |
| #define | EXYNOS_DP_INT_STA 0x3DC |
| #define | EXYNOS_DP_COMMON_INT_MASK_1 0x3E0 |
| #define | EXYNOS_DP_COMMON_INT_MASK_2 0x3E4 |
| #define | EXYNOS_DP_COMMON_INT_MASK_3 0x3E8 |
| #define | EXYNOS_DP_COMMON_INT_MASK_4 0x3EC |
| #define | EXYNOS_DP_INT_STA_MASK 0x3F8 |
| #define | EXYNOS_DP_INT_CTL 0x3FC |
| #define | EXYNOS_DP_SYS_CTL_1 0x600 |
| #define | EXYNOS_DP_SYS_CTL_2 0x604 |
| #define | EXYNOS_DP_SYS_CTL_3 0x608 |
| #define | EXYNOS_DP_SYS_CTL_4 0x60C |
| #define | EXYNOS_DP_PKT_SEND_CTL 0x640 |
| #define | EXYNOS_DP_HDCP_CTL 0x648 |
| #define | EXYNOS_DP_LINK_BW_SET 0x680 |
| #define | EXYNOS_DP_LANE_COUNT_SET 0x684 |
| #define | EXYNOS_DP_TRAINING_PTN_SET 0x688 |
| #define | EXYNOS_DP_LN0_LINK_TRAINING_CTL 0x68C |
| #define | EXYNOS_DP_LN1_LINK_TRAINING_CTL 0x690 |
| #define | EXYNOS_DP_LN2_LINK_TRAINING_CTL 0x694 |
| #define | EXYNOS_DP_LN3_LINK_TRAINING_CTL 0x698 |
| #define | EXYNOS_DP_DEBUG_CTL 0x6C0 |
| #define | EXYNOS_DP_HPD_DEGLITCH_L 0x6C4 |
| #define | EXYNOS_DP_HPD_DEGLITCH_H 0x6C8 |
| #define | EXYNOS_DP_LINK_DEBUG_CTL 0x6E0 |
| #define | EXYNOS_DP_M_VID_0 0x700 |
| #define | EXYNOS_DP_M_VID_1 0x704 |
| #define | EXYNOS_DP_M_VID_2 0x708 |
| #define | EXYNOS_DP_N_VID_0 0x70C |
| #define | EXYNOS_DP_N_VID_1 0x710 |
| #define | EXYNOS_DP_N_VID_2 0x714 |
| #define | EXYNOS_DP_PLL_CTL 0x71C |
| #define | EXYNOS_DP_PHY_PD 0x720 |
| #define | EXYNOS_DP_PHY_TEST 0x724 |
| #define | EXYNOS_DP_VIDEO_FIFO_THRD 0x730 |
| #define | EXYNOS_DP_AUDIO_MARGIN 0x73C |
| #define | EXYNOS_DP_M_VID_GEN_FILTER_TH 0x764 |
| #define | EXYNOS_DP_M_AUD_GEN_FILTER_TH 0x778 |
| #define | EXYNOS_DP_AUX_CH_STA 0x780 |
| #define | EXYNOS_DP_AUX_CH_DEFER_CTL 0x788 |
| #define | EXYNOS_DP_AUX_RX_COMM 0x78C |
| #define | EXYNOS_DP_BUFFER_DATA_CTL 0x790 |
| #define | EXYNOS_DP_AUX_CH_CTL_1 0x794 |
| #define | EXYNOS_DP_AUX_ADDR_7_0 0x798 |
| #define | EXYNOS_DP_AUX_ADDR_15_8 0x79C |
| #define | EXYNOS_DP_AUX_ADDR_19_16 0x7A0 |
| #define | EXYNOS_DP_AUX_CH_CTL_2 0x7A4 |
| #define | EXYNOS_DP_BUF_DATA_0 0x7C0 |
| #define | EXYNOS_DP_SOC_GENERAL_CTL 0x800 |
| #define | RESET_DP_TX (0x1 << 0) |
| #define | MASTER_VID_FUNC_EN_N (0x1 << 7) |
| #define | SLAVE_VID_FUNC_EN_N (0x1 << 5) |
| #define | AUD_FIFO_FUNC_EN_N (0x1 << 4) |
| #define | AUD_FUNC_EN_N (0x1 << 3) |
| #define | HDCP_FUNC_EN_N (0x1 << 2) |
| #define | CRC_FUNC_EN_N (0x1 << 1) |
| #define | SW_FUNC_EN_N (0x1 << 0) |
| #define | SSC_FUNC_EN_N (0x1 << 7) |
| #define | AUX_FUNC_EN_N (0x1 << 2) |
| #define | SERDES_FIFO_FUNC_EN_N (0x1 << 1) |
| #define | LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) |
| #define | VIDEO_EN (0x1 << 7) |
| #define | HDCP_VIDEO_MUTE (0x1 << 6) |
| #define | IN_D_RANGE_MASK (0x1 << 7) |
| #define | IN_D_RANGE_SHIFT (7) |
| #define | IN_D_RANGE_CEA (0x1 << 7) |
| #define | IN_D_RANGE_VESA (0x0 << 7) |
| #define | IN_BPC_MASK (0x7 << 4) |
| #define | IN_BPC_SHIFT (4) |
| #define | IN_BPC_12_BITS (0x3 << 4) |
| #define | IN_BPC_10_BITS (0x2 << 4) |
| #define | IN_BPC_8_BITS (0x1 << 4) |
| #define | IN_BPC_6_BITS (0x0 << 4) |
| #define | IN_COLOR_F_MASK (0x3 << 0) |
| #define | IN_COLOR_F_SHIFT (0) |
| #define | IN_COLOR_F_YCBCR444 (0x2 << 0) |
| #define | IN_COLOR_F_YCBCR422 (0x1 << 0) |
| #define | IN_COLOR_F_RGB (0x0 << 0) |
| #define | IN_YC_COEFFI_MASK (0x1 << 7) |
| #define | IN_YC_COEFFI_SHIFT (7) |
| #define | IN_YC_COEFFI_ITU709 (0x1 << 7) |
| #define | IN_YC_COEFFI_ITU601 (0x0 << 7) |
| #define | VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) |
| #define | VID_CHK_UPDATE_TYPE_SHIFT (4) |
| #define | VID_CHK_UPDATE_TYPE_1 (0x1 << 4) |
| #define | VID_CHK_UPDATE_TYPE_0 (0x0 << 4) |
| #define | VID_HRES_TH(x) (((x) & 0xf) << 4) |
| #define | VID_VRES_TH(x) (((x) & 0xf) << 0) |
| #define | FORMAT_SEL (0x1 << 4) |
| #define | INTERACE_SCAN_CFG (0x1 << 2) |
| #define | VSYNC_POLARITY_CFG (0x1 << 1) |
| #define | HSYNC_POLARITY_CFG (0x1 << 0) |
| #define | LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) |
| #define | LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) |
| #define | LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) |
| #define | LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) |
| #define | LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) |
| #define | LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) |
| #define | LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) |
| #define | LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) |
| #define | LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) |
| #define | LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) |
| #define | LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) |
| #define | LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) |
| #define | LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) |
| #define | LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) |
| #define | LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) |
| #define | LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) |
| #define | TX_TERMINAL_CTRL_50_OHM (0x1 << 4) |
| #define | SEL_24M (0x1 << 3) |
| #define | TX_DVDD_BIT_1_0625V (0x4 << 0) |
| #define | DRIVE_DVDD_BIT_1_0625V (0x4 << 5) |
| #define | VCO_BIT_600_MICRO (0x5 << 0) |
| #define | PD_RING_OSC (0x1 << 6) |
| #define | AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) |
| #define | TX_CUR1_2X (0x1 << 2) |
| #define | TX_CUR_16_MA (0x3 << 0) |
| #define | CH3_AMP_400_MV (0x0 << 24) |
| #define | CH2_AMP_400_MV (0x0 << 16) |
| #define | CH1_AMP_400_MV (0x0 << 8) |
| #define | CH0_AMP_400_MV (0x0 << 0) |
| #define | AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) |
| #define | AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) |
| #define | AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) |
| #define | AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) |
| #define | AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) |
| #define | AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) |
| #define | AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) |
| #define | VSYNC_DET (0x1 << 7) |
| #define | PLL_LOCK_CHG (0x1 << 6) |
| #define | SPDIF_ERR (0x1 << 5) |
| #define | SPDIF_UNSTBL (0x1 << 4) |
| #define | VID_FORMAT_CHG (0x1 << 3) |
| #define | AUD_CLK_CHG (0x1 << 2) |
| #define | VID_CLK_CHG (0x1 << 1) |
| #define | SW_INT (0x1 << 0) |
| #define | ENC_EN_CHG (0x1 << 6) |
| #define | HW_BKSV_RDY (0x1 << 3) |
| #define | HW_SHA_DONE (0x1 << 2) |
| #define | HW_AUTH_STATE_CHG (0x1 << 1) |
| #define | HW_AUTH_DONE (0x1 << 0) |
| #define | AFIFO_UNDER (0x1 << 7) |
| #define | AFIFO_OVER (0x1 << 6) |
| #define | R0_CHK_FLAG (0x1 << 5) |
| #define | PSR_ACTIVE (0x1 << 7) |
| #define | PSR_INACTIVE (0x1 << 6) |
| #define | SPDIF_BI_PHASE_ERR (0x1 << 5) |
| #define | HOTPLUG_CHG (0x1 << 2) |
| #define | HPD_LOST (0x1 << 1) |
| #define | PLUG (0x1 << 0) |
| #define | INT_HPD (0x1 << 6) |
| #define | HW_TRAINING_FINISH (0x1 << 5) |
| #define | RPLY_RECEIV (0x1 << 1) |
| #define | AUX_ERR (0x1 << 0) |
| #define | SOFT_INT_CTRL (0x1 << 2) |
| #define | INT_POL (0x1 << 0) |
| #define | DET_STA (0x1 << 2) |
| #define | FORCE_DET (0x1 << 1) |
| #define | DET_CTRL (0x1 << 0) |
| #define | CHA_CRI(x) (((x) & 0xf) << 4) |
| #define | CHA_STA (0x1 << 2) |
| #define | FORCE_CHA (0x1 << 1) |
| #define | CHA_CTRL (0x1 << 0) |
| #define | HPD_STATUS (0x1 << 6) |
| #define | F_HPD (0x1 << 5) |
| #define | HPD_CTRL (0x1 << 4) |
| #define | HDCP_RDY (0x1 << 3) |
| #define | STRM_VALID (0x1 << 2) |
| #define | F_VALID (0x1 << 1) |
| #define | VALID_CTRL (0x1 << 0) |
| #define | FIX_M_AUD (0x1 << 4) |
| #define | ENHANCED (0x1 << 3) |
| #define | FIX_M_VID (0x1 << 2) |
| #define | M_VID_UPDATE_CTRL (0x3 << 0) |
| #define | SCRAMBLER_TYPE (0x1 << 9) |
| #define | HW_LINK_TRAINING_PATTERN (0x1 << 8) |
| #define | SCRAMBLING_DISABLE (0x1 << 5) |
| #define | SCRAMBLING_ENABLE (0x0 << 5) |
| #define | LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) |
| #define | LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) |
| #define | LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) |
| #define | LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) |
| #define | SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) |
| #define | SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) |
| #define | SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) |
| #define | SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) |
| #define | PRE_EMPHASIS_SET_MASK (0x3 << 3) |
| #define | PRE_EMPHASIS_SET_SHIFT (3) |
| #define | PLL_LOCK (0x1 << 4) |
| #define | F_PLL_LOCK (0x1 << 3) |
| #define | PLL_LOCK_CTRL (0x1 << 2) |
| #define | PN_INV (0x1 << 0) |
| #define | DP_PLL_PD (0x1 << 7) |
| #define | DP_PLL_RESET (0x1 << 6) |
| #define | DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) |
| #define | DP_PLL_REF_BIT_1_1250V (0x5 << 0) |
| #define | DP_PLL_REF_BIT_1_2500V (0x7 << 0) |
| #define | DP_PHY_PD (0x1 << 5) |
| #define | AUX_PD (0x1 << 4) |
| #define | CH3_PD (0x1 << 3) |
| #define | CH2_PD (0x1 << 2) |
| #define | CH1_PD (0x1 << 1) |
| #define | CH0_PD (0x1 << 0) |
| #define | MACRO_RST (0x1 << 5) |
| #define | CH1_TEST (0x1 << 1) |
| #define | CH0_TEST (0x1 << 0) |
| #define | AUX_BUSY (0x1 << 4) |
| #define | AUX_STATUS_MASK (0xf << 0) |
| #define | DEFER_CTRL_EN (0x1 << 7) |
| #define | DEFER_COUNT(x) (((x) & 0x7f) << 0) |
| #define | AUX_RX_COMM_I2C_DEFER (0x2 << 2) |
| #define | AUX_RX_COMM_AUX_DEFER (0x2 << 0) |
| #define | BUF_CLR (0x1 << 7) |
| #define | BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) |
| #define | AUX_LENGTH(x) (((x - 1) & 0xf) << 4) |
| #define | AUX_TX_COMM_MASK (0xf << 0) |
| #define | AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) |
| #define | AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) |
| #define | AUX_TX_COMM_MOT (0x1 << 2) |
| #define | AUX_TX_COMM_WRITE (0x0 << 0) |
| #define | AUX_TX_COMM_READ (0x1 << 0) |
| #define | AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) |
| #define | AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) |
| #define | AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) |
| #define | ADDR_ONLY (0x1 << 1) |
| #define | AUX_EN (0x1 << 0) |
| #define | AUDIO_MODE_SPDIF_MODE (0x1 << 8) |
| #define | AUDIO_MODE_MASTER_MODE (0x0 << 8) |
| #define | MASTER_VIDEO_INTERLACE_EN (0x1 << 4) |
| #define | VIDEO_MASTER_CLK_SEL (0x1 << 2) |
| #define | VIDEO_MASTER_MODE_EN (0x1 << 1) |
| #define | VIDEO_MODE_MASK (0x1 << 0) |
| #define | VIDEO_MODE_SLAVE_MODE (0x1 << 0) |
| #define | VIDEO_MODE_MASTER_MODE (0x0 << 0) |
| #define ADDR_ONLY (0x1 << 1) |
Definition at line 352 of file exynos_dp_reg.h.
| #define AFIFO_OVER (0x1 << 6) |
Definition at line 226 of file exynos_dp_reg.h.
| #define AFIFO_UNDER (0x1 << 7) |
Definition at line 225 of file exynos_dp_reg.h.
| #define AUD_CLK_CHG (0x1 << 2) |
Definition at line 213 of file exynos_dp_reg.h.
| #define AUD_FIFO_FUNC_EN_N (0x1 << 4) |
Definition at line 104 of file exynos_dp_reg.h.
| #define AUD_FUNC_EN_N (0x1 << 3) |
Definition at line 105 of file exynos_dp_reg.h.
| #define AUDIO_MODE_MASTER_MODE (0x0 << 8) |
Definition at line 357 of file exynos_dp_reg.h.
| #define AUDIO_MODE_SPDIF_MODE (0x1 << 8) |
Definition at line 356 of file exynos_dp_reg.h.
Definition at line 346 of file exynos_dp_reg.h.
Definition at line 349 of file exynos_dp_reg.h.
Definition at line 343 of file exynos_dp_reg.h.
Definition at line 199 of file exynos_dp_reg.h.
| #define AUX_BUSY (0x1 << 4) |
Definition at line 318 of file exynos_dp_reg.h.
| #define AUX_EN (0x1 << 0) |
Definition at line 353 of file exynos_dp_reg.h.
| #define AUX_ERR (0x1 << 0) |
Definition at line 241 of file exynos_dp_reg.h.
| #define AUX_FUNC_EN_N (0x1 << 2) |
Definition at line 112 of file exynos_dp_reg.h.
Definition at line 205 of file exynos_dp_reg.h.
| #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) |
Definition at line 203 of file exynos_dp_reg.h.
| #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) |
Definition at line 204 of file exynos_dp_reg.h.
| #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) |
Definition at line 201 of file exynos_dp_reg.h.
| #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) |
Definition at line 202 of file exynos_dp_reg.h.
| #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) |
Definition at line 200 of file exynos_dp_reg.h.
Definition at line 334 of file exynos_dp_reg.h.
| #define AUX_PD (0x1 << 4) |
Definition at line 306 of file exynos_dp_reg.h.
| #define AUX_RX_COMM_AUX_DEFER (0x2 << 0) |
Definition at line 327 of file exynos_dp_reg.h.
| #define AUX_RX_COMM_I2C_DEFER (0x2 << 2) |
Definition at line 326 of file exynos_dp_reg.h.
| #define AUX_STATUS_MASK (0xf << 0) |
Definition at line 319 of file exynos_dp_reg.h.
| #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) |
Definition at line 188 of file exynos_dp_reg.h.
| #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) |
Definition at line 336 of file exynos_dp_reg.h.
| #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) |
Definition at line 337 of file exynos_dp_reg.h.
| #define AUX_TX_COMM_MASK (0xf << 0) |
Definition at line 335 of file exynos_dp_reg.h.
| #define AUX_TX_COMM_MOT (0x1 << 2) |
Definition at line 338 of file exynos_dp_reg.h.
| #define AUX_TX_COMM_READ (0x1 << 0) |
Definition at line 340 of file exynos_dp_reg.h.
| #define AUX_TX_COMM_WRITE (0x0 << 0) |
Definition at line 339 of file exynos_dp_reg.h.
| #define BUF_CLR (0x1 << 7) |
Definition at line 330 of file exynos_dp_reg.h.
Definition at line 331 of file exynos_dp_reg.h.
| #define CH0_AMP_400_MV (0x0 << 0) |
Definition at line 196 of file exynos_dp_reg.h.
| #define CH0_PD (0x1 << 0) |
Definition at line 310 of file exynos_dp_reg.h.
| #define CH0_TEST (0x1 << 0) |
Definition at line 315 of file exynos_dp_reg.h.
| #define CH1_AMP_400_MV (0x0 << 8) |
Definition at line 195 of file exynos_dp_reg.h.
| #define CH1_PD (0x1 << 1) |
Definition at line 309 of file exynos_dp_reg.h.
| #define CH1_TEST (0x1 << 1) |
Definition at line 314 of file exynos_dp_reg.h.
| #define CH2_AMP_400_MV (0x0 << 16) |
Definition at line 194 of file exynos_dp_reg.h.
| #define CH2_PD (0x1 << 2) |
Definition at line 308 of file exynos_dp_reg.h.
| #define CH3_AMP_400_MV (0x0 << 24) |
Definition at line 193 of file exynos_dp_reg.h.
| #define CH3_PD (0x1 << 3) |
Definition at line 307 of file exynos_dp_reg.h.
Definition at line 253 of file exynos_dp_reg.h.
| #define CHA_CTRL (0x1 << 0) |
Definition at line 256 of file exynos_dp_reg.h.
| #define CHA_STA (0x1 << 2) |
Definition at line 254 of file exynos_dp_reg.h.
| #define CRC_FUNC_EN_N (0x1 << 1) |
Definition at line 107 of file exynos_dp_reg.h.
Definition at line 323 of file exynos_dp_reg.h.
| #define DEFER_CTRL_EN (0x1 << 7) |
Definition at line 322 of file exynos_dp_reg.h.
| #define DET_CTRL (0x1 << 0) |
Definition at line 250 of file exynos_dp_reg.h.
| #define DET_STA (0x1 << 2) |
Definition at line 248 of file exynos_dp_reg.h.
| #define DP_PHY_PD (0x1 << 5) |
Definition at line 305 of file exynos_dp_reg.h.
| #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) |
Definition at line 300 of file exynos_dp_reg.h.
| #define DP_PLL_PD (0x1 << 7) |
Definition at line 298 of file exynos_dp_reg.h.
| #define DP_PLL_REF_BIT_1_1250V (0x5 << 0) |
Definition at line 301 of file exynos_dp_reg.h.
| #define DP_PLL_REF_BIT_1_2500V (0x7 << 0) |
Definition at line 302 of file exynos_dp_reg.h.
| #define DP_PLL_RESET (0x1 << 6) |
Definition at line 299 of file exynos_dp_reg.h.
| #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) |
Definition at line 183 of file exynos_dp_reg.h.
| #define ENC_EN_CHG (0x1 << 6) |
Definition at line 218 of file exynos_dp_reg.h.
| #define ENHANCED (0x1 << 3) |
Definition at line 269 of file exynos_dp_reg.h.
| #define EXYNOS_DP_ANALOG_CTL_1 0x370 |
Definition at line 27 of file exynos_dp_reg.h.
| #define EXYNOS_DP_ANALOG_CTL_2 0x374 |
Definition at line 28 of file exynos_dp_reg.h.
| #define EXYNOS_DP_ANALOG_CTL_3 0x378 |
Definition at line 29 of file exynos_dp_reg.h.
| #define EXYNOS_DP_AUDIO_MARGIN 0x73C |
Definition at line 80 of file exynos_dp_reg.h.
| #define EXYNOS_DP_AUX_ADDR_15_8 0x79C |
Definition at line 90 of file exynos_dp_reg.h.
| #define EXYNOS_DP_AUX_ADDR_19_16 0x7A0 |
Definition at line 91 of file exynos_dp_reg.h.
| #define EXYNOS_DP_AUX_ADDR_7_0 0x798 |
Definition at line 89 of file exynos_dp_reg.h.
| #define EXYNOS_DP_AUX_CH_CTL_1 0x794 |
Definition at line 88 of file exynos_dp_reg.h.
| #define EXYNOS_DP_AUX_CH_CTL_2 0x7A4 |
Definition at line 92 of file exynos_dp_reg.h.
| #define EXYNOS_DP_AUX_CH_DEFER_CTL 0x788 |
Definition at line 85 of file exynos_dp_reg.h.
| #define EXYNOS_DP_AUX_CH_STA 0x780 |
Definition at line 84 of file exynos_dp_reg.h.
| #define EXYNOS_DP_AUX_HW_RETRY_CTL 0x390 |
Definition at line 33 of file exynos_dp_reg.h.
| #define EXYNOS_DP_AUX_RX_COMM 0x78C |
Definition at line 86 of file exynos_dp_reg.h.
| #define EXYNOS_DP_BUF_DATA_0 0x7C0 |
Definition at line 94 of file exynos_dp_reg.h.
| #define EXYNOS_DP_BUFFER_DATA_CTL 0x790 |
Definition at line 87 of file exynos_dp_reg.h.
| #define EXYNOS_DP_COMMON_INT_MASK_1 0x3E0 |
Definition at line 40 of file exynos_dp_reg.h.
| #define EXYNOS_DP_COMMON_INT_MASK_2 0x3E4 |
Definition at line 41 of file exynos_dp_reg.h.
| #define EXYNOS_DP_COMMON_INT_MASK_3 0x3E8 |
Definition at line 42 of file exynos_dp_reg.h.
| #define EXYNOS_DP_COMMON_INT_MASK_4 0x3EC |
Definition at line 43 of file exynos_dp_reg.h.
| #define EXYNOS_DP_COMMON_INT_STA_1 0x3C4 |
Definition at line 35 of file exynos_dp_reg.h.
| #define EXYNOS_DP_COMMON_INT_STA_2 0x3C8 |
Definition at line 36 of file exynos_dp_reg.h.
| #define EXYNOS_DP_COMMON_INT_STA_3 0x3CC |
Definition at line 37 of file exynos_dp_reg.h.
| #define EXYNOS_DP_COMMON_INT_STA_4 0x3D0 |
Definition at line 38 of file exynos_dp_reg.h.
| #define EXYNOS_DP_DEBUG_CTL 0x6C0 |
Definition at line 63 of file exynos_dp_reg.h.
| #define EXYNOS_DP_FUNC_EN_1 0x18 |
Definition at line 16 of file exynos_dp_reg.h.
| #define EXYNOS_DP_FUNC_EN_2 0x1C |
Definition at line 17 of file exynos_dp_reg.h.
| #define EXYNOS_DP_HDCP_CTL 0x648 |
Definition at line 53 of file exynos_dp_reg.h.
| #define EXYNOS_DP_HPD_DEGLITCH_H 0x6C8 |
Definition at line 65 of file exynos_dp_reg.h.
| #define EXYNOS_DP_HPD_DEGLITCH_L 0x6C4 |
Definition at line 64 of file exynos_dp_reg.h.
| #define EXYNOS_DP_INT_CTL 0x3FC |
Definition at line 45 of file exynos_dp_reg.h.
| #define EXYNOS_DP_INT_STA 0x3DC |
Definition at line 39 of file exynos_dp_reg.h.
| #define EXYNOS_DP_INT_STA_MASK 0x3F8 |
Definition at line 44 of file exynos_dp_reg.h.
| #define EXYNOS_DP_LANE_COUNT_SET 0x684 |
Definition at line 56 of file exynos_dp_reg.h.
| #define EXYNOS_DP_LANE_MAP 0x35C |
Definition at line 25 of file exynos_dp_reg.h.
| #define EXYNOS_DP_LINK_BW_SET 0x680 |
Definition at line 55 of file exynos_dp_reg.h.
| #define EXYNOS_DP_LINK_DEBUG_CTL 0x6E0 |
Definition at line 66 of file exynos_dp_reg.h.
| #define EXYNOS_DP_LN0_LINK_TRAINING_CTL 0x68C |
Definition at line 58 of file exynos_dp_reg.h.
| #define EXYNOS_DP_LN1_LINK_TRAINING_CTL 0x690 |
Definition at line 59 of file exynos_dp_reg.h.
| #define EXYNOS_DP_LN2_LINK_TRAINING_CTL 0x694 |
Definition at line 60 of file exynos_dp_reg.h.
| #define EXYNOS_DP_LN3_LINK_TRAINING_CTL 0x698 |
Definition at line 61 of file exynos_dp_reg.h.
| #define EXYNOS_DP_M_AUD_GEN_FILTER_TH 0x778 |
Definition at line 83 of file exynos_dp_reg.h.
| #define EXYNOS_DP_M_VID_0 0x700 |
Definition at line 68 of file exynos_dp_reg.h.
| #define EXYNOS_DP_M_VID_1 0x704 |
Definition at line 69 of file exynos_dp_reg.h.
| #define EXYNOS_DP_M_VID_2 0x708 |
Definition at line 70 of file exynos_dp_reg.h.
| #define EXYNOS_DP_M_VID_GEN_FILTER_TH 0x764 |
Definition at line 82 of file exynos_dp_reg.h.
| #define EXYNOS_DP_N_VID_0 0x70C |
Definition at line 71 of file exynos_dp_reg.h.
| #define EXYNOS_DP_N_VID_1 0x710 |
Definition at line 72 of file exynos_dp_reg.h.
| #define EXYNOS_DP_N_VID_2 0x714 |
Definition at line 73 of file exynos_dp_reg.h.
| #define EXYNOS_DP_PHY_PD 0x720 |
Definition at line 76 of file exynos_dp_reg.h.
| #define EXYNOS_DP_PHY_TEST 0x724 |
Definition at line 77 of file exynos_dp_reg.h.
| #define EXYNOS_DP_PKT_SEND_CTL 0x640 |
Definition at line 52 of file exynos_dp_reg.h.
| #define EXYNOS_DP_PLL_CTL 0x71C |
Definition at line 75 of file exynos_dp_reg.h.
| #define EXYNOS_DP_PLL_FILTER_CTL_1 0x37C |
Definition at line 30 of file exynos_dp_reg.h.
| #define EXYNOS_DP_SOC_GENERAL_CTL 0x800 |
Definition at line 96 of file exynos_dp_reg.h.
| #define EXYNOS_DP_SYS_CTL_1 0x600 |
Definition at line 47 of file exynos_dp_reg.h.
| #define EXYNOS_DP_SYS_CTL_2 0x604 |
Definition at line 48 of file exynos_dp_reg.h.
| #define EXYNOS_DP_SYS_CTL_3 0x608 |
Definition at line 49 of file exynos_dp_reg.h.
| #define EXYNOS_DP_SYS_CTL_4 0x60C |
Definition at line 50 of file exynos_dp_reg.h.
| #define EXYNOS_DP_TRAINING_PTN_SET 0x688 |
Definition at line 57 of file exynos_dp_reg.h.
| #define EXYNOS_DP_TX_AMP_TUNING_CTL 0x380 |
Definition at line 31 of file exynos_dp_reg.h.
| #define EXYNOS_DP_TX_SW_RESET 0x14 |
Definition at line 15 of file exynos_dp_reg.h.
| #define EXYNOS_DP_VIDEO_CTL_1 0x20 |
Definition at line 18 of file exynos_dp_reg.h.
| #define EXYNOS_DP_VIDEO_CTL_10 0x44 |
Definition at line 23 of file exynos_dp_reg.h.
| #define EXYNOS_DP_VIDEO_CTL_2 0x24 |
Definition at line 19 of file exynos_dp_reg.h.
| #define EXYNOS_DP_VIDEO_CTL_3 0x28 |
Definition at line 20 of file exynos_dp_reg.h.
| #define EXYNOS_DP_VIDEO_CTL_8 0x3C |
Definition at line 22 of file exynos_dp_reg.h.
| #define EXYNOS_DP_VIDEO_FIFO_THRD 0x730 |
Definition at line 79 of file exynos_dp_reg.h.
| #define F_HPD (0x1 << 5) |
Definition at line 260 of file exynos_dp_reg.h.
| #define F_PLL_LOCK (0x1 << 3) |
Definition at line 293 of file exynos_dp_reg.h.
| #define F_VALID (0x1 << 1) |
Definition at line 264 of file exynos_dp_reg.h.
| #define FIX_M_AUD (0x1 << 4) |
Definition at line 268 of file exynos_dp_reg.h.
| #define FIX_M_VID (0x1 << 2) |
Definition at line 270 of file exynos_dp_reg.h.
| #define FORCE_CHA (0x1 << 1) |
Definition at line 255 of file exynos_dp_reg.h.
| #define FORCE_DET (0x1 << 1) |
Definition at line 249 of file exynos_dp_reg.h.
| #define FORMAT_SEL (0x1 << 4) |
Definition at line 152 of file exynos_dp_reg.h.
| #define HDCP_FUNC_EN_N (0x1 << 2) |
Definition at line 106 of file exynos_dp_reg.h.
| #define HDCP_RDY (0x1 << 3) |
Definition at line 262 of file exynos_dp_reg.h.
| #define HDCP_VIDEO_MUTE (0x1 << 6) |
Definition at line 118 of file exynos_dp_reg.h.
| #define HOTPLUG_CHG (0x1 << 2) |
Definition at line 233 of file exynos_dp_reg.h.
| #define HPD_CTRL (0x1 << 4) |
Definition at line 261 of file exynos_dp_reg.h.
| #define HPD_LOST (0x1 << 1) |
Definition at line 234 of file exynos_dp_reg.h.
| #define HPD_STATUS (0x1 << 6) |
Definition at line 259 of file exynos_dp_reg.h.
| #define HSYNC_POLARITY_CFG (0x1 << 0) |
Definition at line 155 of file exynos_dp_reg.h.
| #define HW_AUTH_DONE (0x1 << 0) |
Definition at line 222 of file exynos_dp_reg.h.
| #define HW_AUTH_STATE_CHG (0x1 << 1) |
Definition at line 221 of file exynos_dp_reg.h.
| #define HW_BKSV_RDY (0x1 << 3) |
Definition at line 219 of file exynos_dp_reg.h.
| #define HW_LINK_TRAINING_PATTERN (0x1 << 8) |
Definition at line 275 of file exynos_dp_reg.h.
| #define HW_SHA_DONE (0x1 << 2) |
Definition at line 220 of file exynos_dp_reg.h.
| #define HW_TRAINING_FINISH (0x1 << 5) |
Definition at line 239 of file exynos_dp_reg.h.
| #define IN_BPC_10_BITS (0x2 << 4) |
Definition at line 128 of file exynos_dp_reg.h.
| #define IN_BPC_12_BITS (0x3 << 4) |
Definition at line 127 of file exynos_dp_reg.h.
| #define IN_BPC_6_BITS (0x0 << 4) |
Definition at line 130 of file exynos_dp_reg.h.
| #define IN_BPC_8_BITS (0x1 << 4) |
Definition at line 129 of file exynos_dp_reg.h.
| #define IN_BPC_MASK (0x7 << 4) |
Definition at line 125 of file exynos_dp_reg.h.
| #define IN_BPC_SHIFT (4) |
Definition at line 126 of file exynos_dp_reg.h.
| #define IN_COLOR_F_MASK (0x3 << 0) |
Definition at line 131 of file exynos_dp_reg.h.
| #define IN_COLOR_F_RGB (0x0 << 0) |
Definition at line 135 of file exynos_dp_reg.h.
| #define IN_COLOR_F_SHIFT (0) |
Definition at line 132 of file exynos_dp_reg.h.
| #define IN_COLOR_F_YCBCR422 (0x1 << 0) |
Definition at line 134 of file exynos_dp_reg.h.
| #define IN_COLOR_F_YCBCR444 (0x2 << 0) |
Definition at line 133 of file exynos_dp_reg.h.
| #define IN_D_RANGE_CEA (0x1 << 7) |
Definition at line 123 of file exynos_dp_reg.h.
| #define IN_D_RANGE_MASK (0x1 << 7) |
Definition at line 121 of file exynos_dp_reg.h.
| #define IN_D_RANGE_SHIFT (7) |
Definition at line 122 of file exynos_dp_reg.h.
| #define IN_D_RANGE_VESA (0x0 << 7) |
Definition at line 124 of file exynos_dp_reg.h.
| #define IN_YC_COEFFI_ITU601 (0x0 << 7) |
Definition at line 141 of file exynos_dp_reg.h.
| #define IN_YC_COEFFI_ITU709 (0x1 << 7) |
Definition at line 140 of file exynos_dp_reg.h.
| #define IN_YC_COEFFI_MASK (0x1 << 7) |
Definition at line 138 of file exynos_dp_reg.h.
| #define IN_YC_COEFFI_SHIFT (7) |
Definition at line 139 of file exynos_dp_reg.h.
| #define INT_HPD (0x1 << 6) |
Definition at line 238 of file exynos_dp_reg.h.
| #define INT_POL (0x1 << 0) |
Definition at line 245 of file exynos_dp_reg.h.
| #define INTERACE_SCAN_CFG (0x1 << 2) |
Definition at line 153 of file exynos_dp_reg.h.
| #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) |
Definition at line 170 of file exynos_dp_reg.h.
| #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) |
Definition at line 171 of file exynos_dp_reg.h.
| #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) |
Definition at line 172 of file exynos_dp_reg.h.
| #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) |
Definition at line 173 of file exynos_dp_reg.h.
| #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) |
Definition at line 166 of file exynos_dp_reg.h.
| #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) |
Definition at line 167 of file exynos_dp_reg.h.
| #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) |
Definition at line 168 of file exynos_dp_reg.h.
| #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) |
Definition at line 169 of file exynos_dp_reg.h.
| #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) |
Definition at line 162 of file exynos_dp_reg.h.
| #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) |
Definition at line 163 of file exynos_dp_reg.h.
| #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) |
Definition at line 164 of file exynos_dp_reg.h.
| #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) |
Definition at line 165 of file exynos_dp_reg.h.
| #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) |
Definition at line 158 of file exynos_dp_reg.h.
| #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) |
Definition at line 159 of file exynos_dp_reg.h.
| #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) |
Definition at line 160 of file exynos_dp_reg.h.
| #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) |
Definition at line 161 of file exynos_dp_reg.h.
| #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) |
Definition at line 280 of file exynos_dp_reg.h.
| #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) |
Definition at line 281 of file exynos_dp_reg.h.
| #define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) |
Definition at line 278 of file exynos_dp_reg.h.
| #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) |
Definition at line 279 of file exynos_dp_reg.h.
| #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) |
Definition at line 114 of file exynos_dp_reg.h.
| #define M_VID_UPDATE_CTRL (0x3 << 0) |
Definition at line 271 of file exynos_dp_reg.h.
| #define MACRO_RST (0x1 << 5) |
Definition at line 313 of file exynos_dp_reg.h.
| #define MASTER_VID_FUNC_EN_N (0x1 << 7) |
Definition at line 102 of file exynos_dp_reg.h.
| #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) |
Definition at line 358 of file exynos_dp_reg.h.
| #define PD_RING_OSC (0x1 << 6) |
Definition at line 187 of file exynos_dp_reg.h.
| #define PLL_LOCK (0x1 << 4) |
Definition at line 292 of file exynos_dp_reg.h.
| #define PLL_LOCK_CHG (0x1 << 6) |
Definition at line 209 of file exynos_dp_reg.h.
| #define PLL_LOCK_CTRL (0x1 << 2) |
Definition at line 294 of file exynos_dp_reg.h.
| #define PLUG (0x1 << 0) |
Definition at line 235 of file exynos_dp_reg.h.
| #define PN_INV (0x1 << 0) |
Definition at line 295 of file exynos_dp_reg.h.
| #define PRE_EMPHASIS_SET_MASK (0x3 << 3) |
Definition at line 288 of file exynos_dp_reg.h.
| #define PRE_EMPHASIS_SET_SHIFT (3) |
Definition at line 289 of file exynos_dp_reg.h.
| #define PSR_ACTIVE (0x1 << 7) |
Definition at line 230 of file exynos_dp_reg.h.
| #define PSR_INACTIVE (0x1 << 6) |
Definition at line 231 of file exynos_dp_reg.h.
| #define R0_CHK_FLAG (0x1 << 5) |
Definition at line 227 of file exynos_dp_reg.h.
| #define RESET_DP_TX (0x1 << 0) |
Definition at line 99 of file exynos_dp_reg.h.
| #define RPLY_RECEIV (0x1 << 1) |
Definition at line 240 of file exynos_dp_reg.h.
| #define SCRAMBLER_TYPE (0x1 << 9) |
Definition at line 274 of file exynos_dp_reg.h.
| #define SCRAMBLING_DISABLE (0x1 << 5) |
Definition at line 276 of file exynos_dp_reg.h.
| #define SCRAMBLING_ENABLE (0x0 << 5) |
Definition at line 277 of file exynos_dp_reg.h.
| #define SEL_24M (0x1 << 3) |
Definition at line 179 of file exynos_dp_reg.h.
| #define SERDES_FIFO_FUNC_EN_N (0x1 << 1) |
Definition at line 113 of file exynos_dp_reg.h.
| #define SLAVE_VID_FUNC_EN_N (0x1 << 5) |
Definition at line 103 of file exynos_dp_reg.h.
| #define SOFT_INT_CTRL (0x1 << 2) |
Definition at line 244 of file exynos_dp_reg.h.
| #define SPDIF_BI_PHASE_ERR (0x1 << 5) |
Definition at line 232 of file exynos_dp_reg.h.
| #define SPDIF_ERR (0x1 << 5) |
Definition at line 210 of file exynos_dp_reg.h.
| #define SPDIF_UNSTBL (0x1 << 4) |
Definition at line 211 of file exynos_dp_reg.h.
| #define SSC_FUNC_EN_N (0x1 << 7) |
Definition at line 111 of file exynos_dp_reg.h.
| #define STRM_VALID (0x1 << 2) |
Definition at line 263 of file exynos_dp_reg.h.
| #define SW_FUNC_EN_N (0x1 << 0) |
Definition at line 108 of file exynos_dp_reg.h.
| #define SW_INT (0x1 << 0) |
Definition at line 215 of file exynos_dp_reg.h.
| #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) |
Definition at line 282 of file exynos_dp_reg.h.
| #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) |
Definition at line 285 of file exynos_dp_reg.h.
| #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) |
Definition at line 284 of file exynos_dp_reg.h.
| #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) |
Definition at line 283 of file exynos_dp_reg.h.
| #define TX_CUR1_2X (0x1 << 2) |
Definition at line 189 of file exynos_dp_reg.h.
| #define TX_CUR_16_MA (0x3 << 0) |
Definition at line 190 of file exynos_dp_reg.h.
| #define TX_DVDD_BIT_1_0625V (0x4 << 0) |
Definition at line 180 of file exynos_dp_reg.h.
| #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) |
Definition at line 176 of file exynos_dp_reg.h.
| #define VALID_CTRL (0x1 << 0) |
Definition at line 265 of file exynos_dp_reg.h.
| #define VCO_BIT_600_MICRO (0x5 << 0) |
Definition at line 184 of file exynos_dp_reg.h.
| #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) |
Definition at line 145 of file exynos_dp_reg.h.
| #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) |
Definition at line 144 of file exynos_dp_reg.h.
| #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) |
Definition at line 142 of file exynos_dp_reg.h.
| #define VID_CHK_UPDATE_TYPE_SHIFT (4) |
Definition at line 143 of file exynos_dp_reg.h.
| #define VID_CLK_CHG (0x1 << 1) |
Definition at line 214 of file exynos_dp_reg.h.
| #define VID_FORMAT_CHG (0x1 << 3) |
Definition at line 212 of file exynos_dp_reg.h.
Definition at line 148 of file exynos_dp_reg.h.
Definition at line 149 of file exynos_dp_reg.h.
| #define VIDEO_EN (0x1 << 7) |
Definition at line 117 of file exynos_dp_reg.h.
| #define VIDEO_MASTER_CLK_SEL (0x1 << 2) |
Definition at line 359 of file exynos_dp_reg.h.
| #define VIDEO_MASTER_MODE_EN (0x1 << 1) |
Definition at line 360 of file exynos_dp_reg.h.
| #define VIDEO_MODE_MASK (0x1 << 0) |
Definition at line 361 of file exynos_dp_reg.h.
| #define VIDEO_MODE_MASTER_MODE (0x0 << 0) |
Definition at line 363 of file exynos_dp_reg.h.
| #define VIDEO_MODE_SLAVE_MODE (0x1 << 0) |
Definition at line 362 of file exynos_dp_reg.h.
| #define VSYNC_DET (0x1 << 7) |
Definition at line 208 of file exynos_dp_reg.h.
| #define VSYNC_POLARITY_CFG (0x1 << 1) |
Definition at line 154 of file exynos_dp_reg.h.
1.8.2