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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | EXYNOS_DSIM_STATUS 0x0 /* Status register */ |
| #define | EXYNOS_DSIM_SWRST 0x4 /* Software reset register */ |
| #define | EXYNOS_DSIM_CLKCTRL 0x8 /* Clock control register */ |
| #define | EXYNOS_DSIM_TIMEOUT 0xc /* Time out register */ |
| #define | EXYNOS_DSIM_CONFIG 0x10 /* Configuration register */ |
| #define | EXYNOS_DSIM_ESCMODE 0x14 /* Escape mode register */ |
| #define | EXYNOS_DSIM_MDRESOL 0x18 |
| #define | EXYNOS_DSIM_MVPORCH 0x1c /* Main display Vporch register */ |
| #define | EXYNOS_DSIM_MHPORCH 0x20 /* Main display Hporch register */ |
| #define | EXYNOS_DSIM_MSYNC 0x24 /* Main display sync area register */ |
| #define | EXYNOS_DSIM_SDRESOL 0x28 |
| #define | EXYNOS_DSIM_INTSRC 0x2c /* Interrupt source register */ |
| #define | EXYNOS_DSIM_INTMSK 0x30 /* Interrupt mask register */ |
| #define | EXYNOS_DSIM_PKTHDR 0x34 /* Packet Header FIFO register */ |
| #define | EXYNOS_DSIM_PAYLOAD 0x38 /* Payload FIFO register */ |
| #define | EXYNOS_DSIM_RXFIFO 0x3c /* Read FIFO register */ |
| #define | EXYNOS_DSIM_FIFOTHLD 0x40 /* FIFO threshold level register */ |
| #define | EXYNOS_DSIM_FIFOCTRL 0x44 /* FIFO status and control register */ |
| #define | EXYNOS_DSIM_PLLCTRL 0x4c /* PLL control register */ |
| #define | EXYNOS_DSIM_PLLTMR 0x50 /* PLL timer register */ |
| #define | EXYNOS_DSIM_PHYACCHR 0x54 /* D-PHY AC characteristic register */ |
| #define | EXYNOS_DSIM_PHYACCHR1 0x58 /* D-PHY AC characteristic register1 */ |
| #define | DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) |
| #define | DSIM_STOP_STATE_CLK (1 << 8) |
| #define | DSIM_TX_READY_HS_CLK (1 << 10) |
| #define | DSIM_FUNCRST (1 << 16) |
| #define | DSIM_SWRST (1 << 0) |
| #define | DSIM_LPDR_TOUT_SHIFT(x) ((x) << 0) |
| #define | DSIM_BTA_TOUT_SHIFT(x) ((x) << 16) |
| #define | DSIM_LANE_ESC_CLKEN(x) (((x) & 0x1f) << 19) |
| #define | DSIM_BYTE_CLKEN_SHIFT(x) ((x) << 24) |
| #define | DSIM_BYTE_CLK_SRC_SHIFT(x) ((x) << 25) |
| #define | DSIM_PLL_BYPASS_SHIFT(x) ((x) << 27) |
| #define | DSIM_ESC_CLKEN_SHIFT(x) ((x) << 28) |
| #define | DSIM_TX_REQUEST_HSCLK_SHIFT(x) ((x) << 31) |
| #define | DSIM_LANE_ENx(x) (((x) & 0x1f) << 0) |
| #define | DSIM_NUM_OF_DATALANE_SHIFT(x) ((x) << 5) |
| #define | DSIM_HSA_MODE_SHIFT(x) ((x) << 20) |
| #define | DSIM_HBP_MODE_SHIFT(x) ((x) << 21) |
| #define | DSIM_HFP_MODE_SHIFT(x) ((x) << 22) |
| #define | DSIM_HSE_MODE_SHIFT(x) ((x) << 23) |
| #define | DSIM_AUTO_MODE_SHIFT(x) ((x) << 24) |
| #define | DSIM_EOT_DISABLE(x) ((x) << 28) |
| #define | DSIM_AUTO_FLUSH(x) ((x) << 29) |
| #define | DSIM_NUM_OF_DATA_LANE(x) ((x) << DSIM_NUM_OF_DATALANE_SHIFT) |
| #define | DSIM_TX_LPDT_LP (1 << 6) |
| #define | DSIM_CMD_LPDT_LP (1 << 7) |
| #define | DSIM_FORCE_STOP_STATE_SHIFT(x) ((x) << 20) |
| #define | DSIM_STOP_STATE_CNT_SHIFT(x) ((x) << 21) |
| #define | DSIM_MAIN_STAND_BY (1 << 31) |
| #define | DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16) |
| #define | DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0) |
| #define | DSIM_CMD_ALLOW_SHIFT(x) ((x) << 28) |
| #define | DSIM_STABLE_VFP_SHIFT(x) ((x) << 16) |
| #define | DSIM_MAIN_VBP_SHIFT(x) ((x) << 0) |
| #define | DSIM_CMD_ALLOW_MASK (0xf << 28) |
| #define | DSIM_STABLE_VFP_MASK (0x7ff << 16) |
| #define | DSIM_MAIN_VBP_MASK (0x7ff << 0) |
| #define | DSIM_MAIN_HFP_SHIFT(x) ((x) << 16) |
| #define | DSIM_MAIN_HBP_SHIFT(x) ((x) << 0) |
| #define | DSIM_MAIN_HFP_MASK ((0xffff) << 16) |
| #define | DSIM_MAIN_HBP_MASK ((0xffff) << 0) |
| #define | DSIM_MAIN_VSA_SHIFT(x) ((x) << 22) |
| #define | DSIM_MAIN_HSA_SHIFT(x) ((x) << 0) |
| #define | DSIM_MAIN_VSA_MASK ((0x3ff) << 22) |
| #define | DSIM_MAIN_HSA_MASK ((0xffff) << 0) |
| #define | DSIM_SUB_STANDY_SHIFT(x) ((x) << 31) |
| #define | DSIM_SUB_VRESOL_SHIFT(x) ((x) << 16) |
| #define | DSIM_SUB_HRESOL_SHIFT(x) ((x) << 0) |
| #define | DSIM_SUB_STANDY_MASK ((0x1) << 31) |
| #define | DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) |
| #define | DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) |
| #define | INTSRC_PLL_STABLE (1 << 31) |
| #define | INTSRC_SW_RST_RELEASE (1 << 30) |
| #define | INTSRC_SFR_FIFO_EMPTY (1 << 29) |
| #define | INTSRC_FRAME_DONE (1 << 24) |
| #define | INTSRC_RX_DATA_DONE (1 << 18) |
| #define | INTMSK_FIFO_EMPTY (1 << 29) |
| #define | INTMSK_BTA (1 << 25) |
| #define | INTMSK_FRAME_DONE (1 << 24) |
| #define | INTMSK_RX_TIMEOUT (1 << 21) |
| #define | INTMSK_BTA_TIMEOUT (1 << 20) |
| #define | INTMSK_RX_DONE (1 << 18) |
| #define | INTMSK_RX_TE (1 << 17) |
| #define | INTMSK_RX_ACK (1 << 16) |
| #define | INTMSK_RX_ECC_ERR (1 << 15) |
| #define | INTMSK_RX_CRC_ERR (1 << 14) |
| #define | SFR_HEADER_EMPTY (1 << 22) |
| #define | DSIM_AFC_CTL(x) (((x) & 0x7) << 5) |
| #define | DSIM_PLL_EN_SHIFT(x) ((x) << 23) |
| #define | DSIM_FREQ_BAND_SHIFT(x) ((x) << 24) |
Definition at line 143 of file exynos_mipi_dsi_regs.h.
Definition at line 77 of file exynos_mipi_dsi_regs.h.
Definition at line 75 of file exynos_mipi_dsi_regs.h.
Definition at line 58 of file exynos_mipi_dsi_regs.h.
Definition at line 63 of file exynos_mipi_dsi_regs.h.
Definition at line 62 of file exynos_mipi_dsi_regs.h.
| #define DSIM_CMD_ALLOW_MASK (0xf << 28) |
Definition at line 96 of file exynos_mipi_dsi_regs.h.
Definition at line 93 of file exynos_mipi_dsi_regs.h.
| #define DSIM_CMD_LPDT_LP (1 << 7) |
Definition at line 83 of file exynos_mipi_dsi_regs.h.
Definition at line 76 of file exynos_mipi_dsi_regs.h.
Definition at line 65 of file exynos_mipi_dsi_regs.h.
Definition at line 84 of file exynos_mipi_dsi_regs.h.
Definition at line 147 of file exynos_mipi_dsi_regs.h.
| #define DSIM_FUNCRST (1 << 16) |
Definition at line 53 of file exynos_mipi_dsi_regs.h.
Definition at line 72 of file exynos_mipi_dsi_regs.h.
Definition at line 73 of file exynos_mipi_dsi_regs.h.
Definition at line 71 of file exynos_mipi_dsi_regs.h.
Definition at line 74 of file exynos_mipi_dsi_regs.h.
Definition at line 69 of file exynos_mipi_dsi_regs.h.
Definition at line 61 of file exynos_mipi_dsi_regs.h.
Definition at line 57 of file exynos_mipi_dsi_regs.h.
| #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) |
Definition at line 104 of file exynos_mipi_dsi_regs.h.
Definition at line 102 of file exynos_mipi_dsi_regs.h.
| #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) |
Definition at line 103 of file exynos_mipi_dsi_regs.h.
Definition at line 101 of file exynos_mipi_dsi_regs.h.
Definition at line 90 of file exynos_mipi_dsi_regs.h.
| #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) |
Definition at line 110 of file exynos_mipi_dsi_regs.h.
Definition at line 108 of file exynos_mipi_dsi_regs.h.
| #define DSIM_MAIN_STAND_BY (1 << 31) |
Definition at line 88 of file exynos_mipi_dsi_regs.h.
| #define DSIM_MAIN_VBP_MASK (0x7ff << 0) |
Definition at line 98 of file exynos_mipi_dsi_regs.h.
Definition at line 95 of file exynos_mipi_dsi_regs.h.
Definition at line 89 of file exynos_mipi_dsi_regs.h.
| #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) |
Definition at line 109 of file exynos_mipi_dsi_regs.h.
Definition at line 107 of file exynos_mipi_dsi_regs.h.
| #define DSIM_NUM_OF_DATA_LANE | ( | x | ) | ((x) << DSIM_NUM_OF_DATALANE_SHIFT) |
Definition at line 79 of file exynos_mipi_dsi_regs.h.
Definition at line 70 of file exynos_mipi_dsi_regs.h.
Definition at line 64 of file exynos_mipi_dsi_regs.h.
Definition at line 146 of file exynos_mipi_dsi_regs.h.
| #define DSIM_STABLE_VFP_MASK (0x7ff << 16) |
Definition at line 97 of file exynos_mipi_dsi_regs.h.
Definition at line 94 of file exynos_mipi_dsi_regs.h.
| #define DSIM_STOP_STATE_CLK (1 << 8) |
Definition at line 49 of file exynos_mipi_dsi_regs.h.
Definition at line 85 of file exynos_mipi_dsi_regs.h.
Definition at line 48 of file exynos_mipi_dsi_regs.h.
| #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) |
Definition at line 118 of file exynos_mipi_dsi_regs.h.
Definition at line 115 of file exynos_mipi_dsi_regs.h.
| #define DSIM_SUB_STANDY_MASK ((0x1) << 31) |
Definition at line 116 of file exynos_mipi_dsi_regs.h.
Definition at line 113 of file exynos_mipi_dsi_regs.h.
| #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) |
Definition at line 117 of file exynos_mipi_dsi_regs.h.
Definition at line 114 of file exynos_mipi_dsi_regs.h.
| #define DSIM_SWRST (1 << 0) |
Definition at line 54 of file exynos_mipi_dsi_regs.h.
| #define DSIM_TX_LPDT_LP (1 << 6) |
Definition at line 82 of file exynos_mipi_dsi_regs.h.
| #define DSIM_TX_READY_HS_CLK (1 << 10) |
Definition at line 50 of file exynos_mipi_dsi_regs.h.
Definition at line 66 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_CLKCTRL 0x8 /* Clock control register */ |
Definition at line 20 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_CONFIG 0x10 /* Configuration register */ |
Definition at line 22 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_ESCMODE 0x14 /* Escape mode register */ |
Definition at line 23 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_FIFOCTRL 0x44 /* FIFO status and control register */ |
Definition at line 39 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_FIFOTHLD 0x40 /* FIFO threshold level register */ |
Definition at line 38 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_INTMSK 0x30 /* Interrupt mask register */ |
Definition at line 34 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_INTSRC 0x2c /* Interrupt source register */ |
Definition at line 33 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_MDRESOL 0x18 |
Definition at line 26 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_MHPORCH 0x20 /* Main display Hporch register */ |
Definition at line 28 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_MSYNC 0x24 /* Main display sync area register */ |
Definition at line 29 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_MVPORCH 0x1c /* Main display Vporch register */ |
Definition at line 27 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_PAYLOAD 0x38 /* Payload FIFO register */ |
Definition at line 36 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_PHYACCHR 0x54 /* D-PHY AC characteristic register */ |
Definition at line 44 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_PHYACCHR1 0x58 /* D-PHY AC characteristic register1 */ |
Definition at line 45 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_PKTHDR 0x34 /* Packet Header FIFO register */ |
Definition at line 35 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_PLLCTRL 0x4c /* PLL control register */ |
Definition at line 42 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_PLLTMR 0x50 /* PLL timer register */ |
Definition at line 43 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_RXFIFO 0x3c /* Read FIFO register */ |
Definition at line 37 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_SDRESOL 0x28 |
Definition at line 32 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_STATUS 0x0 /* Status register */ |
Definition at line 18 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_SWRST 0x4 /* Software reset register */ |
Definition at line 19 of file exynos_mipi_dsi_regs.h.
| #define EXYNOS_DSIM_TIMEOUT 0xc /* Time out register */ |
Definition at line 21 of file exynos_mipi_dsi_regs.h.
| #define INTMSK_BTA (1 << 25) |
Definition at line 129 of file exynos_mipi_dsi_regs.h.
| #define INTMSK_BTA_TIMEOUT (1 << 20) |
Definition at line 132 of file exynos_mipi_dsi_regs.h.
| #define INTMSK_FIFO_EMPTY (1 << 29) |
Definition at line 128 of file exynos_mipi_dsi_regs.h.
| #define INTMSK_FRAME_DONE (1 << 24) |
Definition at line 130 of file exynos_mipi_dsi_regs.h.
| #define INTMSK_RX_ACK (1 << 16) |
Definition at line 135 of file exynos_mipi_dsi_regs.h.
| #define INTMSK_RX_CRC_ERR (1 << 14) |
Definition at line 137 of file exynos_mipi_dsi_regs.h.
| #define INTMSK_RX_DONE (1 << 18) |
Definition at line 133 of file exynos_mipi_dsi_regs.h.
| #define INTMSK_RX_ECC_ERR (1 << 15) |
Definition at line 136 of file exynos_mipi_dsi_regs.h.
| #define INTMSK_RX_TE (1 << 17) |
Definition at line 134 of file exynos_mipi_dsi_regs.h.
| #define INTMSK_RX_TIMEOUT (1 << 21) |
Definition at line 131 of file exynos_mipi_dsi_regs.h.
| #define INTSRC_FRAME_DONE (1 << 24) |
Definition at line 124 of file exynos_mipi_dsi_regs.h.
| #define INTSRC_PLL_STABLE (1 << 31) |
Definition at line 121 of file exynos_mipi_dsi_regs.h.
| #define INTSRC_RX_DATA_DONE (1 << 18) |
Definition at line 125 of file exynos_mipi_dsi_regs.h.
| #define INTSRC_SFR_FIFO_EMPTY (1 << 29) |
Definition at line 123 of file exynos_mipi_dsi_regs.h.
| #define INTSRC_SW_RST_RELEASE (1 << 30) |
Definition at line 122 of file exynos_mipi_dsi_regs.h.
| #define SFR_HEADER_EMPTY (1 << 22) |
Definition at line 140 of file exynos_mipi_dsi_regs.h.
1.8.2