fdc37c93xapm.c File Reference

#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/err.h>
#include <mach/microdev.h>

Go to the source code of this file.

Macros
#define	SMSC_CONFIG_PORT_ADDR   (0x3F0)
#define	SMSC_INDEX_PORT_ADDR   SMSC_CONFIG_PORT_ADDR
#define	SMSC_DATA_PORT_ADDR   (SMSC_INDEX_PORT_ADDR + 1)
#define	SMSC_ENTER_CONFIG_KEY   0x55
#define	SMSC_EXIT_CONFIG_KEY   0xaa
#define	SMCS_LOGICAL_DEV_INDEX   0x07 /* Logical Device Number */
#define	SMSC_DEVICE_ID_INDEX   0x20 /* Device ID */
#define	SMSC_DEVICE_REV_INDEX   0x21 /* Device Revision */
#define	SMSC_ACTIVATE_INDEX   0x30 /* Activate */
#define	SMSC_PRIMARY_BASE_INDEX   0x60 /* Primary Base Address */
#define	SMSC_SECONDARY_BASE_INDEX   0x62 /* Secondary Base Address */
#define	SMSC_PRIMARY_INT_INDEX   0x70 /* Primary Interrupt Select */
#define	SMSC_SECONDARY_INT_INDEX   0x72 /* Secondary Interrupt Select */
#define	SMSC_HDCS0_INDEX   0xf0 /* HDCS0 Address Decoder */
#define	SMSC_HDCS1_INDEX   0xf1 /* HDCS1 Address Decoder */
#define	SMSC_IDE1_DEVICE   1 /* IDE #1 logical device */
#define	SMSC_IDE2_DEVICE   2 /* IDE #2 logical device */
#define	SMSC_PARALLEL_DEVICE   3 /* Parallel Port logical device */
#define	SMSC_SERIAL1_DEVICE   4 /* Serial #1 logical device */
#define	SMSC_SERIAL2_DEVICE   5 /* Serial #2 logical device */
#define	SMSC_KEYBOARD_DEVICE   7 /* Keyboard logical device */
#define	SMSC_CONFIG_REGISTERS   8 /* Configuration Registers (Aux I/O) */
#define	SMSC_READ_INDEXED(index)
#define	SMSC_WRITE_INDEXED(val, index)
#define	IDE1_PRIMARY_BASE   0x01f0 /* Task File Registe base for IDE #1 */
#define	IDE1_SECONDARY_BASE   0x03f6 /* Miscellaneous AT registers for IDE #1 */
#define	IDE2_PRIMARY_BASE   0x0170 /* Task File Registe base for IDE #2 */
#define	IDE2_SECONDARY_BASE   0x0376 /* Miscellaneous AT registers for IDE #2 */
#define	SERIAL1_PRIMARY_BASE   0x03f8
#define	SERIAL2_PRIMARY_BASE   0x02f8
#define	MSB(x)   ( (x) >> 8 )
#define	LSB(x)   ( (x) & 0xff )
#define	MICRODEV_FPGA_GP_BASE   0xa6100000ul

Functions
	device_initcall (smsc_superio_setup)

Macro Definition Documentation

#define IDE1_PRIMARY_BASE   0x01f0 /* Task File Registe base for IDE #1 */

Definition at line 53 of file fdc37c93xapm.c.

#define IDE1_SECONDARY_BASE   0x03f6 /* Miscellaneous AT registers for IDE #1 */

Definition at line 54 of file fdc37c93xapm.c.

#define IDE2_PRIMARY_BASE   0x0170 /* Task File Registe base for IDE #2 */

Definition at line 55 of file fdc37c93xapm.c.

#define IDE2_SECONDARY_BASE   0x0376 /* Miscellaneous AT registers for IDE #2 */

Definition at line 56 of file fdc37c93xapm.c.

#define LSB

(

x

)

( (x) & 0xff )

Definition at line 62 of file fdc37c93xapm.c.

#define MICRODEV_FPGA_GP_BASE   0xa6100000ul

Definition at line 65 of file fdc37c93xapm.c.

#define MSB

(

x

)

( (x) >> 8 )

Definition at line 61 of file fdc37c93xapm.c.

#define SERIAL1_PRIMARY_BASE   0x03f8

Definition at line 58 of file fdc37c93xapm.c.

#define SERIAL2_PRIMARY_BASE   0x02f8

Definition at line 59 of file fdc37c93xapm.c.

#define SMCS_LOGICAL_DEV_INDEX   0x07 /* Logical Device Number */

Definition at line 27 of file fdc37c93xapm.c.

#define SMSC_ACTIVATE_INDEX   0x30 /* Activate */

Definition at line 30 of file fdc37c93xapm.c.

#define SMSC_CONFIG_PORT_ADDR   (0x3F0)

Definition at line 20 of file fdc37c93xapm.c.

#define SMSC_CONFIG_REGISTERS   8 /* Configuration Registers (Aux I/O) */

Definition at line 44 of file fdc37c93xapm.c.

#define SMSC_DATA_PORT_ADDR   (SMSC_INDEX_PORT_ADDR + 1)

Definition at line 22 of file fdc37c93xapm.c.

#define SMSC_DEVICE_ID_INDEX   0x20 /* Device ID */

Definition at line 28 of file fdc37c93xapm.c.

#define SMSC_DEVICE_REV_INDEX   0x21 /* Device Revision */

Definition at line 29 of file fdc37c93xapm.c.

#define SMSC_ENTER_CONFIG_KEY   0x55

Definition at line 24 of file fdc37c93xapm.c.

#define SMSC_EXIT_CONFIG_KEY   0xaa

Definition at line 25 of file fdc37c93xapm.c.

#define SMSC_HDCS0_INDEX   0xf0 /* HDCS0 Address Decoder */

Definition at line 35 of file fdc37c93xapm.c.

#define SMSC_HDCS1_INDEX   0xf1 /* HDCS1 Address Decoder */

Definition at line 36 of file fdc37c93xapm.c.

#define SMSC_IDE1_DEVICE   1 /* IDE #1 logical device */

Definition at line 38 of file fdc37c93xapm.c.

#define SMSC_IDE2_DEVICE   2 /* IDE #2 logical device */

Definition at line 39 of file fdc37c93xapm.c.

#define SMSC_INDEX_PORT_ADDR   SMSC_CONFIG_PORT_ADDR

Definition at line 21 of file fdc37c93xapm.c.

#define SMSC_KEYBOARD_DEVICE   7 /* Keyboard logical device */

Definition at line 43 of file fdc37c93xapm.c.

#define SMSC_PARALLEL_DEVICE   3 /* Parallel Port logical device */

Definition at line 40 of file fdc37c93xapm.c.

#define SMSC_PRIMARY_BASE_INDEX   0x60 /* Primary Base Address */

Definition at line 31 of file fdc37c93xapm.c.

#define SMSC_PRIMARY_INT_INDEX   0x70 /* Primary Interrupt Select */

Definition at line 33 of file fdc37c93xapm.c.

#define SMSC_READ_INDEXED

(

index

)

Value:

({ \
    outb((index), SMSC_INDEX_PORT_ADDR); \
    inb(SMSC_DATA_PORT_ADDR); })

Definition at line 46 of file fdc37c93xapm.c.

#define SMSC_SECONDARY_BASE_INDEX   0x62 /* Secondary Base Address */

Definition at line 32 of file fdc37c93xapm.c.

#define SMSC_SECONDARY_INT_INDEX   0x72 /* Secondary Interrupt Select */

Definition at line 34 of file fdc37c93xapm.c.

#define SMSC_SERIAL1_DEVICE   4 /* Serial #1 logical device */

Definition at line 41 of file fdc37c93xapm.c.

#define SMSC_SERIAL2_DEVICE   5 /* Serial #2 logical device */

Definition at line 42 of file fdc37c93xapm.c.

#define SMSC_WRITE_INDEXED	(		val,
			index
	)

Value:

({ \
    outb((index), SMSC_INDEX_PORT_ADDR); \
    outb((val),   SMSC_DATA_PORT_ADDR); })

Definition at line 49 of file fdc37c93xapm.c.

Function Documentation

device_initcall

(

smsc_superio_setup

)