|
Linux Kernel
3.7.1
|
All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
|
Linux Kernel
3.7.1
|
#include <linux/module.h>#include <linux/kernel.h>#include <linux/init.h>#include <linux/ptrace.h>#include <linux/slab.h>#include <linux/string.h>#include <linux/timer.h>#include <linux/interrupt.h>#include <linux/in.h>#include <linux/delay.h>#include <linux/ethtool.h>#include <linux/netdevice.h>#include <linux/etherdevice.h>#include <linux/skbuff.h>#include <linux/if_arp.h>#include <linux/ioport.h>#include <linux/crc32.h>#include <pcmcia/cistpl.h>#include <pcmcia/ciscode.h>#include <pcmcia/ds.h>#include <asm/uaccess.h>#include <asm/io.h>Go to the source code of this file.
Data Structures | |
| struct | local_info_t |
Macros | |
| #define | pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| #define | DRV_NAME "fmvj18x_cs" |
| #define | DRV_VERSION "2.9" |
| #define | INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0) |
| #define | MC_FILTERBREAK 64 |
| #define | TX_STATUS 0 /* transmit status register */ |
| #define | RX_STATUS 1 /* receive status register */ |
| #define | TX_INTR 2 /* transmit interrupt mask register */ |
| #define | RX_INTR 3 /* receive interrupt mask register */ |
| #define | TX_MODE 4 /* transmit mode register */ |
| #define | RX_MODE 5 /* receive mode register */ |
| #define | CONFIG_0 6 /* configuration register 0 */ |
| #define | CONFIG_1 7 /* configuration register 1 */ |
| #define | NODE_ID 8 /* node ID register (bank 0) */ |
| #define | MAR_ADR 8 /* multicast address registers (bank 1) */ |
| #define | DATAPORT 8 /* buffer mem port registers (bank 2) */ |
| #define | TX_START 10 /* transmit start register */ |
| #define | COL_CTRL 11 /* 16 collision control register */ |
| #define | BMPR12 12 /* reserved */ |
| #define | BMPR13 13 /* reserved */ |
| #define | RX_SKIP 14 /* skip received packet register */ |
| #define | LAN_CTRL 16 /* LAN card control register */ |
| #define | MAC_ID 0x1a /* hardware address */ |
| #define | UNGERMANN_MAC_ID 0x18 /* UNGERMANN-BASS hardware address */ |
| #define | ENA_TMT_OK 0x80 |
| #define | ENA_TMT_REC 0x20 |
| #define | ENA_COL 0x04 |
| #define | ENA_16_COL 0x02 |
| #define | ENA_TBUS_ERR 0x01 |
| #define | ENA_PKT_RDY 0x80 |
| #define | ENA_BUS_ERR 0x40 |
| #define | ENA_LEN_ERR 0x08 |
| #define | ENA_ALG_ERR 0x04 |
| #define | ENA_CRC_ERR 0x02 |
| #define | ENA_OVR_FLO 0x01 |
| #define | F_TMT_RDY 0x80 /* can accept new packet */ |
| #define | F_NET_BSY 0x40 /* carrier is detected */ |
| #define | F_TMT_OK 0x20 /* send packet successfully */ |
| #define | F_SRT_PKT 0x10 /* short packet error */ |
| #define | F_COL_ERR 0x04 /* collision error */ |
| #define | F_16_COL 0x02 /* 16 collision error */ |
| #define | F_TBUS_ERR 0x01 /* bus read error */ |
| #define | F_PKT_RDY 0x80 /* packet(s) in buffer */ |
| #define | F_BUS_ERR 0x40 /* bus read error */ |
| #define | F_LEN_ERR 0x08 /* short packet */ |
| #define | F_ALG_ERR 0x04 /* frame error */ |
| #define | F_CRC_ERR 0x02 /* CRC error */ |
| #define | F_OVR_FLO 0x01 /* overflow error */ |
| #define | F_BUF_EMP 0x40 /* receive buffer is empty */ |
| #define | F_SKP_PKT 0x05 /* drop packet in buffer */ |
| #define | D_TX_INTR ( ENA_TMT_OK ) |
| #define | D_RX_INTR |
| #define | TX_STAT_M ( F_TMT_RDY ) |
| #define | RX_STAT_M |
| #define | D_TX_MODE 0x06 /* no tests, detect carrier */ |
| #define | ID_MATCHED 0x02 /* (RX_MODE) */ |
| #define | RECV_ALL 0x03 /* (RX_MODE) */ |
| #define | CONFIG0_DFL 0x5a /* 16bit bus, 4K x 2 Tx queues */ |
| #define | CONFIG0_DFL_1 0x5e /* 16bit bus, 8K x 2 Tx queues */ |
| #define | CONFIG0_RST 0xda /* Data Link Controller off (CONFIG_0) */ |
| #define | CONFIG0_RST_1 0xde /* Data Link Controller off (CONFIG_0) */ |
| #define | BANK_0 0xa0 /* bank 0 (CONFIG_1) */ |
| #define | BANK_1 0xa4 /* bank 1 (CONFIG_1) */ |
| #define | BANK_2 0xa8 /* bank 2 (CONFIG_1) */ |
| #define | CHIP_OFF 0x80 /* contrl chip power off (CONFIG_1) */ |
| #define | DO_TX 0x80 /* do transmit packet */ |
| #define | SEND_PKT 0x81 /* send a packet */ |
| #define | AUTO_MODE 0x07 /* Auto skip packet on 16 col detected */ |
| #define | MANU_MODE 0x03 /* Stop and skip packet on 16 col */ |
| #define | TDK_AUTO_MODE 0x47 /* Auto skip packet on 16 col detected */ |
| #define | TDK_MANU_MODE 0x43 /* Stop and skip packet on 16 col */ |
| #define | INTR_OFF 0x0d /* LAN controller ignores interrupts */ |
| #define | INTR_ON 0x1d /* LAN controller will catch interrupts */ |
| #define | TX_TIMEOUT ((400*HZ)/1000) |
| #define | BANK_0U 0x20 /* bank 0 (CONFIG_1) */ |
| #define | BANK_1U 0x24 /* bank 1 (CONFIG_1) */ |
| #define | BANK_2U 0x28 /* bank 2 (CONFIG_1) */ |
Typedefs | |
| typedef struct local_info_t | local_info_t |
Enumerations | |
| enum | cardtype_t { MBH10302, MBH10304, TDK, CONTEC, LA501, UNGERMANN, XXX10304, NEC, KME } |
Functions | |
| MODULE_DESCRIPTION ("fmvj18x and compatible PCMCIA ethernet driver") | |
| MODULE_LICENSE ("GPL") | |
| INT_MODULE_PARM (sram_config, 0) | |
| MODULE_DEVICE_TABLE (pcmcia, fmvj18x_ids) | |
| module_init (init_fmvj18x_cs) | |
| module_exit (exit_fmvj18x_cs) | |
| #define AUTO_MODE 0x07 /* Auto skip packet on 16 col detected */ |
Definition at line 209 of file fmvj18x_cs.c.
| #define BANK_0 0xa0 /* bank 0 (CONFIG_1) */ |
Definition at line 203 of file fmvj18x_cs.c.
| #define BANK_0U 0x20 /* bank 0 (CONFIG_1) */ |
Definition at line 218 of file fmvj18x_cs.c.
| #define BANK_1 0xa4 /* bank 1 (CONFIG_1) */ |
Definition at line 204 of file fmvj18x_cs.c.
| #define BANK_1U 0x24 /* bank 1 (CONFIG_1) */ |
Definition at line 219 of file fmvj18x_cs.c.
| #define BANK_2 0xa8 /* bank 2 (CONFIG_1) */ |
Definition at line 205 of file fmvj18x_cs.c.
| #define BANK_2U 0x28 /* bank 2 (CONFIG_1) */ |
Definition at line 220 of file fmvj18x_cs.c.
| #define BMPR12 12 /* reserved */ |
Definition at line 142 of file fmvj18x_cs.c.
| #define BMPR13 13 /* reserved */ |
Definition at line 143 of file fmvj18x_cs.c.
| #define CHIP_OFF 0x80 /* contrl chip power off (CONFIG_1) */ |
Definition at line 206 of file fmvj18x_cs.c.
| #define COL_CTRL 11 /* 16 collision control register */ |
Definition at line 141 of file fmvj18x_cs.c.
| #define CONFIG0_DFL 0x5a /* 16bit bus, 4K x 2 Tx queues */ |
Definition at line 199 of file fmvj18x_cs.c.
| #define CONFIG0_DFL_1 0x5e /* 16bit bus, 8K x 2 Tx queues */ |
Definition at line 200 of file fmvj18x_cs.c.
| #define CONFIG0_RST 0xda /* Data Link Controller off (CONFIG_0) */ |
Definition at line 201 of file fmvj18x_cs.c.
| #define CONFIG0_RST_1 0xde /* Data Link Controller off (CONFIG_0) */ |
Definition at line 202 of file fmvj18x_cs.c.
| #define CONFIG_0 6 /* configuration register 0 */ |
Definition at line 133 of file fmvj18x_cs.c.
| #define CONFIG_1 7 /* configuration register 1 */ |
Definition at line 134 of file fmvj18x_cs.c.
| #define D_RX_INTR |
Definition at line 189 of file fmvj18x_cs.c.
| #define D_TX_INTR ( ENA_TMT_OK ) |
Definition at line 188 of file fmvj18x_cs.c.
| #define D_TX_MODE 0x06 /* no tests, detect carrier */ |
Definition at line 196 of file fmvj18x_cs.c.
Definition at line 139 of file fmvj18x_cs.c.
| #define DO_TX 0x80 /* do transmit packet */ |
Definition at line 207 of file fmvj18x_cs.c.
| #define DRV_NAME "fmvj18x_cs" |
Definition at line 33 of file fmvj18x_cs.c.
| #define DRV_VERSION "2.9" |
Definition at line 34 of file fmvj18x_cs.c.
| #define ENA_16_COL 0x02 |
Definition at line 157 of file fmvj18x_cs.c.
| #define ENA_ALG_ERR 0x04 |
Definition at line 163 of file fmvj18x_cs.c.
| #define ENA_BUS_ERR 0x40 |
Definition at line 161 of file fmvj18x_cs.c.
| #define ENA_COL 0x04 |
Definition at line 156 of file fmvj18x_cs.c.
| #define ENA_CRC_ERR 0x02 |
Definition at line 164 of file fmvj18x_cs.c.
| #define ENA_LEN_ERR 0x08 |
Definition at line 162 of file fmvj18x_cs.c.
| #define ENA_OVR_FLO 0x01 |
Definition at line 165 of file fmvj18x_cs.c.
| #define ENA_PKT_RDY 0x80 |
Definition at line 160 of file fmvj18x_cs.c.
| #define ENA_TBUS_ERR 0x01 |
Definition at line 158 of file fmvj18x_cs.c.
| #define ENA_TMT_OK 0x80 |
Definition at line 154 of file fmvj18x_cs.c.
| #define ENA_TMT_REC 0x20 |
Definition at line 155 of file fmvj18x_cs.c.
| #define F_16_COL 0x02 /* 16 collision error */ |
Definition at line 173 of file fmvj18x_cs.c.
| #define F_ALG_ERR 0x04 /* frame error */ |
Definition at line 179 of file fmvj18x_cs.c.
| #define F_BUF_EMP 0x40 /* receive buffer is empty */ |
Definition at line 183 of file fmvj18x_cs.c.
| #define F_BUS_ERR 0x40 /* bus read error */ |
Definition at line 177 of file fmvj18x_cs.c.
| #define F_COL_ERR 0x04 /* collision error */ |
Definition at line 172 of file fmvj18x_cs.c.
| #define F_CRC_ERR 0x02 /* CRC error */ |
Definition at line 180 of file fmvj18x_cs.c.
| #define F_LEN_ERR 0x08 /* short packet */ |
Definition at line 178 of file fmvj18x_cs.c.
| #define F_NET_BSY 0x40 /* carrier is detected */ |
Definition at line 169 of file fmvj18x_cs.c.
| #define F_OVR_FLO 0x01 /* overflow error */ |
Definition at line 181 of file fmvj18x_cs.c.
| #define F_PKT_RDY 0x80 /* packet(s) in buffer */ |
Definition at line 176 of file fmvj18x_cs.c.
| #define F_SKP_PKT 0x05 /* drop packet in buffer */ |
Definition at line 185 of file fmvj18x_cs.c.
| #define F_SRT_PKT 0x10 /* short packet error */ |
Definition at line 171 of file fmvj18x_cs.c.
| #define F_TBUS_ERR 0x01 /* bus read error */ |
Definition at line 174 of file fmvj18x_cs.c.
| #define F_TMT_OK 0x20 /* send packet successfully */ |
Definition at line 170 of file fmvj18x_cs.c.
| #define F_TMT_RDY 0x80 /* can accept new packet */ |
Definition at line 168 of file fmvj18x_cs.c.
| #define ID_MATCHED 0x02 /* (RX_MODE) */ |
Definition at line 197 of file fmvj18x_cs.c.
Definition at line 68 of file fmvj18x_cs.c.
| #define INTR_OFF 0x0d /* LAN controller ignores interrupts */ |
Definition at line 213 of file fmvj18x_cs.c.
| #define INTR_ON 0x1d /* LAN controller will catch interrupts */ |
Definition at line 214 of file fmvj18x_cs.c.
Definition at line 146 of file fmvj18x_cs.c.
| #define MAC_ID 0x1a /* hardware address */ |
Definition at line 148 of file fmvj18x_cs.c.
| #define MANU_MODE 0x03 /* Stop and skip packet on 16 col */ |
Definition at line 210 of file fmvj18x_cs.c.
Definition at line 137 of file fmvj18x_cs.c.
| #define MC_FILTERBREAK 64 |
Definition at line 121 of file fmvj18x_cs.c.
Definition at line 136 of file fmvj18x_cs.c.
Definition at line 31 of file fmvj18x_cs.c.
| #define RECV_ALL 0x03 /* (RX_MODE) */ |
Definition at line 198 of file fmvj18x_cs.c.
Definition at line 130 of file fmvj18x_cs.c.
| #define RX_MODE 5 /* receive mode register */ |
Definition at line 132 of file fmvj18x_cs.c.
Definition at line 144 of file fmvj18x_cs.c.
| #define RX_STAT_M |
| #define RX_STATUS 1 /* receive status register */ |
Definition at line 128 of file fmvj18x_cs.c.
| #define SEND_PKT 0x81 /* send a packet */ |
Definition at line 208 of file fmvj18x_cs.c.
| #define TDK_AUTO_MODE 0x47 /* Auto skip packet on 16 col detected */ |
Definition at line 211 of file fmvj18x_cs.c.
| #define TDK_MANU_MODE 0x43 /* Stop and skip packet on 16 col */ |
Definition at line 212 of file fmvj18x_cs.c.
Definition at line 129 of file fmvj18x_cs.c.
| #define TX_MODE 4 /* transmit mode register */ |
Definition at line 131 of file fmvj18x_cs.c.
| #define TX_START 10 /* transmit start register */ |
Definition at line 140 of file fmvj18x_cs.c.
| #define TX_STAT_M ( F_TMT_RDY ) |
Definition at line 191 of file fmvj18x_cs.c.
| #define TX_STATUS 0 /* transmit status register */ |
Definition at line 127 of file fmvj18x_cs.c.
| #define TX_TIMEOUT ((400*HZ)/1000) |
Definition at line 216 of file fmvj18x_cs.c.
| #define UNGERMANN_MAC_ID 0x18 /* UNGERMANN-BASS hardware address */ |
Definition at line 149 of file fmvj18x_cs.c.
| typedef struct local_info_t local_info_t |
| enum cardtype_t |
Definition at line 103 of file fmvj18x_cs.c.
| INT_MODULE_PARM | ( | sram_config | , |
| 0 | |||
| ) |
| MODULE_DESCRIPTION | ( | "fmvj18x and compatible PCMCIA ethernet driver" | ) |
| MODULE_DEVICE_TABLE | ( | pcmcia | , |
| fmvj18x_ids | |||
| ) |
| module_exit | ( | exit_fmvj18x_cs | ) |
| module_init | ( | init_fmvj18x_cs | ) |
| MODULE_LICENSE | ( | "GPL" | ) |
1.8.2