fsl_85xx_cache_ctlr.h File Reference

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Data Structures
struct	mpc85xx_l2ctlr
struct	sram_parameters

Macros
#define	L2CR_L2FI   0x40000000 /* L2 flash invalidate */
#define	L2CR_L2IO   0x00200000 /* L2 instruction only */
#define	L2CR_SRAM_ZERO   0x00000000 /* L2SRAM zero size */
#define	L2CR_SRAM_FULL   0x00010000 /* L2SRAM full size */
#define	L2CR_SRAM_HALF   0x00020000 /* L2SRAM half size */
#define	L2CR_SRAM_TWO_HALFS   0x00030000 /* L2SRAM two half sizes */
#define	L2CR_SRAM_QUART   0x00040000 /* L2SRAM one quarter size */
#define	L2CR_SRAM_TWO_QUARTS   0x00050000 /* L2SRAM two quarter size */
#define	L2CR_SRAM_EIGHTH   0x00060000 /* L2SRAM one eighth size */
#define	L2CR_SRAM_TWO_EIGHTH   0x00070000 /* L2SRAM two eighth size */
#define	L2SRAM_OPTIMAL_SZ_SHIFT   0x00000003 /* Optimum size for L2SRAM */
#define	L2SRAM_BAR_MSK_LO18   0xFFFFC000 /* Lower 18 bits */
#define	L2SRAM_BARE_MSK_HI4   0x0000000F /* Upper 4 bits */

Enumerations
enum	cache_sram_lock_ways {   LOCK_WAYS_ZERO, LOCK_WAYS_EIGHTH, LOCK_WAYS_TWO_EIGHTH, LOCK_WAYS_HALF = 4,   LOCK_WAYS_FULL = 8 }

Functions
int	instantiate_cache_sram (struct platform_device *dev, struct sram_parameters sram_params)
void	remove_cache_sram (struct platform_device *dev)

Macro Definition Documentation

#define L2CR_L2FI   0x40000000 /* L2 flash invalidate */

Definition at line 26 of file fsl_85xx_cache_ctlr.h.

#define L2CR_L2IO   0x00200000 /* L2 instruction only */

Definition at line 27 of file fsl_85xx_cache_ctlr.h.

#define L2CR_SRAM_EIGHTH   0x00060000 /* L2SRAM one eighth size */

Definition at line 34 of file fsl_85xx_cache_ctlr.h.

#define L2CR_SRAM_FULL   0x00010000 /* L2SRAM full size */

Definition at line 29 of file fsl_85xx_cache_ctlr.h.

#define L2CR_SRAM_HALF   0x00020000 /* L2SRAM half size */

Definition at line 30 of file fsl_85xx_cache_ctlr.h.

#define L2CR_SRAM_QUART   0x00040000 /* L2SRAM one quarter size */

Definition at line 32 of file fsl_85xx_cache_ctlr.h.

#define L2CR_SRAM_TWO_EIGHTH   0x00070000 /* L2SRAM two eighth size */

Definition at line 35 of file fsl_85xx_cache_ctlr.h.

#define L2CR_SRAM_TWO_HALFS   0x00030000 /* L2SRAM two half sizes */

Definition at line 31 of file fsl_85xx_cache_ctlr.h.

#define L2CR_SRAM_TWO_QUARTS   0x00050000 /* L2SRAM two quarter size */

Definition at line 33 of file fsl_85xx_cache_ctlr.h.

#define L2CR_SRAM_ZERO   0x00000000 /* L2SRAM zero size */

Definition at line 28 of file fsl_85xx_cache_ctlr.h.

#define L2SRAM_BAR_MSK_LO18   0xFFFFC000 /* Lower 18 bits */

Definition at line 39 of file fsl_85xx_cache_ctlr.h.

#define L2SRAM_BARE_MSK_HI4   0x0000000F /* Upper 4 bits */

Definition at line 40 of file fsl_85xx_cache_ctlr.h.

#define L2SRAM_OPTIMAL_SZ_SHIFT   0x00000003 /* Optimum size for L2SRAM */

Definition at line 37 of file fsl_85xx_cache_ctlr.h.

Enumeration Type Documentation

enum cache_sram_lock_ways

Enumerator:

LOCK_WAYS_ZERO
LOCK_WAYS_EIGHTH
LOCK_WAYS_TWO_EIGHTH
LOCK_WAYS_HALF
LOCK_WAYS_FULL

Definition at line 42 of file fsl_85xx_cache_ctlr.h.

Function Documentation

int instantiate_cache_sram	(	struct platform_device *	dev,
		struct sram_parameters	sram_params
	)

Definition at line 83 of file fsl_85xx_cache_sram.c.

void remove_cache_sram

(

struct platform_device *

dev

)

Definition at line 146 of file fsl_85xx_cache_sram.c.