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fsl_lbc.h
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1 /* Freescale Local Bus Controller
2  *
3  * Copyright © 2006-2007, 2010 Freescale Semiconductor
4  *
5  * Authors: Nick Spence <[email protected]>,
6  * Scott Wood <[email protected]>
7  * Jack Lan <[email protected]>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22  */
23 
24 #ifndef __ASM_FSL_LBC_H
25 #define __ASM_FSL_LBC_H
26 
27 #include <linux/compiler.h>
28 #include <linux/types.h>
29 #include <linux/io.h>
30 #include <linux/device.h>
31 #include <linux/spinlock.h>
32 
33 struct fsl_lbc_bank {
34  __be32 br;
35 #define BR_BA 0xFFFF8000
36 #define BR_BA_SHIFT 15
37 #define BR_PS 0x00001800
38 #define BR_PS_SHIFT 11
39 #define BR_PS_8 0x00000800 /* Port Size 8 bit */
40 #define BR_PS_16 0x00001000 /* Port Size 16 bit */
41 #define BR_PS_32 0x00001800 /* Port Size 32 bit */
42 #define BR_DECC 0x00000600
43 #define BR_DECC_SHIFT 9
44 #define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
45 #define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
46 #define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
47 #define BR_WP 0x00000100
48 #define BR_WP_SHIFT 8
49 #define BR_MSEL 0x000000E0
50 #define BR_MSEL_SHIFT 5
51 #define BR_MS_GPCM 0x00000000 /* GPCM */
52 #define BR_MS_FCM 0x00000020 /* FCM */
53 #define BR_MS_SDRAM 0x00000060 /* SDRAM */
54 #define BR_MS_UPMA 0x00000080 /* UPMA */
55 #define BR_MS_UPMB 0x000000A0 /* UPMB */
56 #define BR_MS_UPMC 0x000000C0 /* UPMC */
57 #define BR_V 0x00000001
58 #define BR_V_SHIFT 0
59 #define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
60 
61  __be32 or;
62 #define OR0 0x5004
63 #define OR1 0x500C
64 #define OR2 0x5014
65 #define OR3 0x501C
66 #define OR4 0x5024
67 #define OR5 0x502C
68 #define OR6 0x5034
69 #define OR7 0x503C
70 
71 #define OR_FCM_AM 0xFFFF8000
72 #define OR_FCM_AM_SHIFT 15
73 #define OR_FCM_BCTLD 0x00001000
74 #define OR_FCM_BCTLD_SHIFT 12
75 #define OR_FCM_PGS 0x00000400
76 #define OR_FCM_PGS_SHIFT 10
77 #define OR_FCM_CSCT 0x00000200
78 #define OR_FCM_CSCT_SHIFT 9
79 #define OR_FCM_CST 0x00000100
80 #define OR_FCM_CST_SHIFT 8
81 #define OR_FCM_CHT 0x00000080
82 #define OR_FCM_CHT_SHIFT 7
83 #define OR_FCM_SCY 0x00000070
84 #define OR_FCM_SCY_SHIFT 4
85 #define OR_FCM_SCY_1 0x00000010
86 #define OR_FCM_SCY_2 0x00000020
87 #define OR_FCM_SCY_3 0x00000030
88 #define OR_FCM_SCY_4 0x00000040
89 #define OR_FCM_SCY_5 0x00000050
90 #define OR_FCM_SCY_6 0x00000060
91 #define OR_FCM_SCY_7 0x00000070
92 #define OR_FCM_RST 0x00000008
93 #define OR_FCM_RST_SHIFT 3
94 #define OR_FCM_TRLX 0x00000004
95 #define OR_FCM_TRLX_SHIFT 2
96 #define OR_FCM_EHTR 0x00000002
97 #define OR_FCM_EHTR_SHIFT 1
98 };
99 
100 struct fsl_lbc_regs {
101  struct fsl_lbc_bank bank[12];
102  u8 res0[0x8];
103  __be32 mar;
104  u8 res1[0x4];
105  __be32 mamr;
106 #define MxMR_OP_NO (0 << 28)
107 #define MxMR_OP_WA (1 << 28)
108 #define MxMR_OP_RA (2 << 28)
109 #define MxMR_OP_RP (3 << 28)
110 #define MxMR_MAD 0x3f
111  __be32 mbmr;
112  __be32 mcmr;
113  u8 res2[0x8];
114  __be32 mrtpr;
115  __be32 mdr;
116  u8 res3[0x4];
117  __be32 lsor;
118  __be32 lsdmr;
119  u8 res4[0x8];
120  __be32 lurt;
121  __be32 lsrt;
122  u8 res5[0x8];
123  __be32 ltesr;
124 #define LTESR_BM 0x80000000
125 #define LTESR_FCT 0x40000000
126 #define LTESR_PAR 0x20000000
127 #define LTESR_WP 0x04000000
128 #define LTESR_ATMW 0x00800000
129 #define LTESR_ATMR 0x00400000
130 #define LTESR_CS 0x00080000
131 #define LTESR_UPM 0x00000002
132 #define LTESR_CC 0x00000001
133 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
134 #define LTESR_MASK (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \
135  | LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \
136  | LTESR_CC)
137 #define LTESR_CLEAR 0xFFFFFFFF
138 #define LTECCR_CLEAR 0xFFFFFFFF
139 #define LTESR_STATUS LTESR_MASK
140 #define LTEIR_ENABLE LTESR_MASK
141 #define LTEDR_ENABLE 0x00000000
142  __be32 ltedr;
143  __be32 lteir;
144  __be32 lteatr;
145  __be32 ltear;
146  __be32 lteccr;
147  u8 res6[0x8];
148  __be32 lbcr;
149 #define LBCR_LDIS 0x80000000
150 #define LBCR_LDIS_SHIFT 31
151 #define LBCR_BCTLC 0x00C00000
152 #define LBCR_BCTLC_SHIFT 22
153 #define LBCR_AHD 0x00200000
154 #define LBCR_LPBSE 0x00020000
155 #define LBCR_LPBSE_SHIFT 17
156 #define LBCR_EPAR 0x00010000
157 #define LBCR_EPAR_SHIFT 16
158 #define LBCR_BMT 0x0000FF00
159 #define LBCR_BMT_SHIFT 8
160 #define LBCR_BMTPS 0x0000000F
161 #define LBCR_BMTPS_SHIFT 0
162 #define LBCR_INIT 0x00040000
163  __be32 lcrr;
164 #define LCRR_DBYP 0x80000000
165 #define LCRR_DBYP_SHIFT 31
166 #define LCRR_BUFCMDC 0x30000000
167 #define LCRR_BUFCMDC_SHIFT 28
168 #define LCRR_ECL 0x03000000
169 #define LCRR_ECL_SHIFT 24
170 #define LCRR_EADC 0x00030000
171 #define LCRR_EADC_SHIFT 16
172 #define LCRR_CLKDIV 0x0000000F
173 #define LCRR_CLKDIV_SHIFT 0
174  u8 res7[0x8];
175  __be32 fmr;
176 #define FMR_CWTO 0x0000F000
177 #define FMR_CWTO_SHIFT 12
178 #define FMR_BOOT 0x00000800
179 #define FMR_ECCM 0x00000100
180 #define FMR_AL 0x00000030
181 #define FMR_AL_SHIFT 4
182 #define FMR_OP 0x00000003
183 #define FMR_OP_SHIFT 0
184  __be32 fir;
185 #define FIR_OP0 0xF0000000
186 #define FIR_OP0_SHIFT 28
187 #define FIR_OP1 0x0F000000
188 #define FIR_OP1_SHIFT 24
189 #define FIR_OP2 0x00F00000
190 #define FIR_OP2_SHIFT 20
191 #define FIR_OP3 0x000F0000
192 #define FIR_OP3_SHIFT 16
193 #define FIR_OP4 0x0000F000
194 #define FIR_OP4_SHIFT 12
195 #define FIR_OP5 0x00000F00
196 #define FIR_OP5_SHIFT 8
197 #define FIR_OP6 0x000000F0
198 #define FIR_OP6_SHIFT 4
199 #define FIR_OP7 0x0000000F
200 #define FIR_OP7_SHIFT 0
201 #define FIR_OP_NOP 0x0 /* No operation and end of sequence */
202 #define FIR_OP_CA 0x1 /* Issue current column address */
203 #define FIR_OP_PA 0x2 /* Issue current block+page address */
204 #define FIR_OP_UA 0x3 /* Issue user defined address */
205 #define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
206 #define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
207 #define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
208 #define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
209 #define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
210 #define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
211 #define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
212 #define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
213 #define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
214 #define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
215 #define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
216 #define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */
217  __be32 fcr;
218 #define FCR_CMD0 0xFF000000
219 #define FCR_CMD0_SHIFT 24
220 #define FCR_CMD1 0x00FF0000
221 #define FCR_CMD1_SHIFT 16
222 #define FCR_CMD2 0x0000FF00
223 #define FCR_CMD2_SHIFT 8
224 #define FCR_CMD3 0x000000FF
225 #define FCR_CMD3_SHIFT 0
226  __be32 fbar;
227 #define FBAR_BLK 0x00FFFFFF
228  __be32 fpar;
229 #define FPAR_SP_PI 0x00007C00
230 #define FPAR_SP_PI_SHIFT 10
231 #define FPAR_SP_MS 0x00000200
232 #define FPAR_SP_CI 0x000001FF
233 #define FPAR_SP_CI_SHIFT 0
234 #define FPAR_LP_PI 0x0003F000
235 #define FPAR_LP_PI_SHIFT 12
236 #define FPAR_LP_MS 0x00000800
237 #define FPAR_LP_CI 0x000007FF
238 #define FPAR_LP_CI_SHIFT 0
239  __be32 fbcr;
240 #define FBCR_BC 0x00000FFF
241 };
242 
243 /*
244  * FSL UPM routines
245  */
246 struct fsl_upm {
247  __be32 __iomem *mxmr;
248  int width;
249 };
250 
251 extern u32 fsl_lbc_addr(phys_addr_t addr_base);
252 extern int fsl_lbc_find(phys_addr_t addr_base);
253 extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
254 
263 static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
264 {
265  clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset);
266 }
267 
274 static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
275 {
276  clrbits32(upm->mxmr, MxMR_OP_RP);
277 
278  while (in_be32(upm->mxmr) & MxMR_OP_RP)
279  cpu_relax();
280 }
281 
282 /* overview of the fsl lbc controller */
283 
284 struct fsl_lbc_ctrl {
285  /* device info */
286  struct device *dev;
287  struct fsl_lbc_regs __iomem *regs;
288  int irq;
289  wait_queue_head_t irq_wait;
290  spinlock_t lock;
291  void *nand;
292 
293  /* status read from LTESR by irq handler */
294  unsigned int irq_status;
295 
296 #ifdef CONFIG_SUSPEND
297  /* save regs when system go to deep-sleep */
298  struct fsl_lbc_regs *saved_regs;
299 #endif
300 };
301 
302 extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
303  u32 mar);
304 extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
305 
306 #endif /* __ASM_FSL_LBC_H */
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