fsl_lbc_regs Struct Reference

#include <fsl_lbc.h>

Data Fields
struct fsl_lbc_bank	bank [12]
u8	res0 [0x8]
__be32	mar
u8	res1 [0x4]
__be32	mamr
__be32	mbmr
__be32	mcmr
u8	res2 [0x8]
__be32	mrtpr
__be32	mdr
u8	res3 [0x4]
__be32	lsor
__be32	lsdmr
u8	res4 [0x8]
__be32	lurt
__be32	lsrt
u8	res5 [0x8]
__be32	ltesr
__be32	ltedr
__be32	lteir
__be32	lteatr
__be32	ltear
__be32	lteccr
u8	res6 [0x8]
__be32	lbcr
__be32	lcrr
u8	res7 [0x8]
__be32	fmr
__be32	fir
__be32	fcr
__be32	fbar
__be32	fpar
__be32	fbcr

Detailed Description

Definition at line 100 of file fsl_lbc.h.

Field Documentation

struct fsl_lbc_bank bank[12]

Definition at line 101 of file fsl_lbc.h.

__be32 fbar

Flash Block Address Register

Definition at line 226 of file fsl_lbc.h.

__be32 fbcr

Flash Byte Count Register

Definition at line 239 of file fsl_lbc.h.

__be32 fcr

Flash Command Register

Definition at line 217 of file fsl_lbc.h.

__be32 fir

Flash Instruction Register

Definition at line 184 of file fsl_lbc.h.

__be32 fmr

Flash Mode Register

Definition at line 175 of file fsl_lbc.h.

__be32 fpar

Flash Page Address Register

Definition at line 228 of file fsl_lbc.h.

__be32 lbcr

Configuration Register

Definition at line 148 of file fsl_lbc.h.

__be32 lcrr

Clock Ratio Register

Definition at line 163 of file fsl_lbc.h.

__be32 lsdmr

SDRAM Mode Register

Definition at line 118 of file fsl_lbc.h.

__be32 lsor

Special Operation Initiation Register

Definition at line 117 of file fsl_lbc.h.

__be32 lsrt

SDRAM Refresh Timer

Definition at line 121 of file fsl_lbc.h.

__be32 ltear

Transfer Error Address Register

Definition at line 145 of file fsl_lbc.h.

__be32 lteatr

Transfer Error Attributes Register

Definition at line 144 of file fsl_lbc.h.

__be32 lteccr

Transfer Error ECC Register

Definition at line 146 of file fsl_lbc.h.

__be32 ltedr

Transfer Error Disable Register

Definition at line 142 of file fsl_lbc.h.

__be32 lteir

Transfer Error Interrupt Register

Definition at line 143 of file fsl_lbc.h.

__be32 ltesr

Transfer Error Status Register

Definition at line 123 of file fsl_lbc.h.

__be32 lurt

UPM Refresh Timer

Definition at line 120 of file fsl_lbc.h.

__be32 mamr

UPMA Mode Register

Definition at line 105 of file fsl_lbc.h.

__be32 mar

UPM Address Register

Definition at line 103 of file fsl_lbc.h.

__be32 mbmr

UPMB Mode Register

Definition at line 111 of file fsl_lbc.h.

__be32 mcmr

UPMC Mode Register

Definition at line 112 of file fsl_lbc.h.

__be32 mdr

UPM Data Register

Definition at line 115 of file fsl_lbc.h.

__be32 mrtpr

Memory Refresh Timer Prescaler Register

Definition at line 114 of file fsl_lbc.h.

u8 res0[0x8]

Definition at line 102 of file fsl_lbc.h.

u8 res1[0x4]

Definition at line 104 of file fsl_lbc.h.

u8 res2[0x8]

Definition at line 113 of file fsl_lbc.h.

u8 res3[0x4]

Definition at line 116 of file fsl_lbc.h.

u8 res4[0x8]

Definition at line 119 of file fsl_lbc.h.

u8 res5[0x8]

Definition at line 122 of file fsl_lbc.h.

u8 res6[0x8]

Definition at line 147 of file fsl_lbc.h.

u8 res7[0x8]

Definition at line 174 of file fsl_lbc.h.

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The documentation for this struct was generated from the following file:

• arch/powerpc/include/asm/fsl_lbc.h