#include <linux/compiler.h>
#include <linux/types.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/spinlock.h>
Go to the source code of this file.
| #define BR_DECC 0x00000600 |
| #define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */ |
| #define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */ |
| #define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */ |
| #define BR_MS_FCM 0x00000020 /* FCM */ |
| #define BR_MS_GPCM 0x00000000 /* GPCM */ |
| #define BR_MS_SDRAM 0x00000060 /* SDRAM */ |
| #define BR_MS_UPMA 0x00000080 /* UPMA */ |
| #define BR_MS_UPMB 0x000000A0 /* UPMB */ |
| #define BR_MS_UPMC 0x000000C0 /* UPMC */ |
| #define BR_MSEL 0x000000E0 |
| #define BR_PS_16 0x00001000 /* Port Size 16 bit */ |
| #define BR_PS_32 0x00001800 /* Port Size 32 bit */ |
| #define BR_PS_8 0x00000800 /* Port Size 8 bit */ |
| #define FBAR_BLK 0x00FFFFFF |
| #define FBCR_BC 0x00000FFF |
| #define FCR_CMD0 0xFF000000 |
| #define FCR_CMD0_SHIFT 24 |
| #define FCR_CMD1 0x00FF0000 |
| #define FCR_CMD1_SHIFT 16 |
| #define FCR_CMD2 0x0000FF00 |
| #define FCR_CMD3 0x000000FF |
| #define FIR_OP0 0xF0000000 |
| #define FIR_OP1 0x0F000000 |
| #define FIR_OP2 0x00F00000 |
| #define FIR_OP3 0x000F0000 |
| #define FIR_OP4 0x0000F000 |
| #define FIR_OP5 0x00000F00 |
| #define FIR_OP6 0x000000F0 |
| #define FIR_OP7 0x0000000F |
| #define FIR_OP_CA 0x1 /* Issue current column address */ |
| #define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ |
| #define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ |
| #define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ |
| #define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ |
| #define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ |
| #define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ |
| #define FIR_OP_NOP 0x0 /* No operation and end of sequence */ |
| #define FIR_OP_PA 0x2 /* Issue current block+page address */ |
| #define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ |
| #define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ |
| #define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ |
| #define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */ |
| #define FIR_OP_UA 0x3 /* Issue user defined address */ |
| #define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ |
| #define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ |
| #define FMR_AL 0x00000030 |
| #define FMR_BOOT 0x00000800 |
| #define FMR_CWTO 0x0000F000 |
| #define FMR_CWTO_SHIFT 12 |
| #define FMR_ECCM 0x00000100 |
| #define FMR_OP 0x00000003 |
| #define FPAR_LP_CI 0x000007FF |
| #define FPAR_LP_CI_SHIFT 0 |
| #define FPAR_LP_MS 0x00000800 |
| #define FPAR_LP_PI 0x0003F000 |
| #define FPAR_LP_PI_SHIFT 12 |
| #define FPAR_SP_CI 0x000001FF |
| #define FPAR_SP_CI_SHIFT 0 |
| #define FPAR_SP_MS 0x00000200 |
| #define FPAR_SP_PI 0x00007C00 |
| #define FPAR_SP_PI_SHIFT 10 |
| #define LBCR_AHD 0x00200000 |
| #define LBCR_BCTLC 0x00C00000 |
| #define LBCR_BCTLC_SHIFT 22 |
| #define LBCR_BMT 0x0000FF00 |
| #define LBCR_BMTPS 0x0000000F |
| #define LBCR_BMTPS_SHIFT 0 |
| #define LBCR_EPAR 0x00010000 |
| #define LBCR_EPAR_SHIFT 16 |
| #define LBCR_INIT 0x00040000 |
| #define LBCR_LDIS 0x80000000 |
| #define LBCR_LDIS_SHIFT 31 |
| #define LBCR_LPBSE 0x00020000 |
| #define LBCR_LPBSE_SHIFT 17 |
| #define LCRR_BUFCMDC 0x30000000 |
| #define LCRR_BUFCMDC_SHIFT 28 |
| #define LCRR_CLKDIV 0x0000000F |
| #define LCRR_CLKDIV_SHIFT 0 |
| #define LCRR_DBYP 0x80000000 |
| #define LCRR_DBYP_SHIFT 31 |
| #define LCRR_EADC 0x00030000 |
| #define LCRR_EADC_SHIFT 16 |
| #define LCRR_ECL 0x03000000 |
| #define LCRR_ECL_SHIFT 24 |
| #define LTECCR_CLEAR 0xFFFFFFFF |
| #define LTEDR_ENABLE 0x00000000 |
| #define LTESR_ATMR 0x00400000 |
| #define LTESR_ATMW 0x00800000 |
| #define LTESR_BM 0x80000000 |
| #define LTESR_CC 0x00000001 |
| #define LTESR_CLEAR 0xFFFFFFFF |
| #define LTESR_CS 0x00080000 |
| #define LTESR_FCT 0x40000000 |
| #define LTESR_PAR 0x20000000 |
| #define LTESR_UPM 0x00000002 |
| #define LTESR_WP 0x04000000 |
| #define MxMR_OP_NO (0 << 28) |
| #define MxMR_OP_RA (2 << 28) |
| #define MxMR_OP_RP (3 << 28) |
| #define MxMR_OP_WA (1 << 28) |
| #define OR_FCM_AM 0xFFFF8000 |
| #define OR_FCM_AM_SHIFT 15 |
| #define OR_FCM_BCTLD 0x00001000 |
| #define OR_FCM_BCTLD_SHIFT 12 |
| #define OR_FCM_CHT 0x00000080 |
| #define OR_FCM_CHT_SHIFT 7 |
| #define OR_FCM_CSCT 0x00000200 |
| #define OR_FCM_CSCT_SHIFT 9 |
| #define OR_FCM_CST 0x00000100 |
| #define OR_FCM_CST_SHIFT 8 |
| #define OR_FCM_EHTR 0x00000002 |
| #define OR_FCM_EHTR_SHIFT 1 |
| #define OR_FCM_PGS 0x00000400 |
| #define OR_FCM_PGS_SHIFT 10 |
| #define OR_FCM_RST 0x00000008 |
| #define OR_FCM_RST_SHIFT 3 |
| #define OR_FCM_SCY 0x00000070 |
| #define OR_FCM_SCY_1 0x00000010 |
| #define OR_FCM_SCY_2 0x00000020 |
| #define OR_FCM_SCY_3 0x00000030 |
| #define OR_FCM_SCY_4 0x00000040 |
| #define OR_FCM_SCY_5 0x00000050 |
| #define OR_FCM_SCY_6 0x00000060 |
| #define OR_FCM_SCY_7 0x00000070 |
| #define OR_FCM_SCY_SHIFT 4 |
| #define OR_FCM_TRLX 0x00000004 |
| #define OR_FCM_TRLX_SHIFT 2 |
fsl_lbc_addr - convert the base address : base address of the memory bank
This function converts a base address of lbc into the right format for the BR register. If the SOC has eLBC then it returns 32bit physical address else it convers a 34bit local bus physical address to correct format of 32bit address for BR register (Example: MPC8641).
Definition at line 46 of file fsl_lbc.c.
fsl_lbc_find - find Localbus bank : base address of the memory bank
This function walks LBC banks comparing "Base address" field of the BR registers with the supplied addr_base argument. When bases match this function returns bank number (starting with 0), otherwise it returns appropriate errno value.
Definition at line 67 of file fsl_lbc.c.
fsl_upm_find - find pre-programmed UPM via base address : base address of the memory bank controlled by the UPM : pointer to the allocated fsl_upm structure
This function fills fsl_upm structure so you can use it with the rest of UPM API. On success this function returns 0, otherwise it returns appropriate errno value.
Definition at line 97 of file fsl_lbc.c.
fsl_upm_run_pattern - actually run an UPM pattern : pointer to the fsl_upm structure obtained via fsl_upm_find : remapped pointer to where memory access should happen : MAR register content during pattern execution
This function triggers dummy write to the memory specified by the io_base, thus UPM pattern actually executed. Note that mar usage depends on the pre-programmed AMX bits in the UPM RAM.
Definition at line 155 of file fsl_lbc.c.
1.8.2