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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | GLOBAL_ID 0x00 |
| #define | CHIP_ID(reg) ((reg) >> 8) |
| #define | CHIP_REVISION(reg) ((reg) & 0xFF) |
| #define | GLOBAL_STATUS 0x04 |
| #define | CPU_BIG_ENDIAN (1 << 31) |
| #define | PLL_OSC_30M (1 << 30) /* else 60MHz */ |
| #define | OPERATION_MODE_MASK (0xF << 26) |
| #define | OPM_IDDQ (0xF << 26) |
| #define | OPM_NAND (0xE << 26) |
| #define | OPM_RING (0xD << 26) |
| #define | OPM_DIRECT_BOOT (0xC << 26) |
| #define | OPM_USB1_PHY_TEST (0xB << 26) |
| #define | OPM_USB0_PHY_TEST (0xA << 26) |
| #define | OPM_SATA1_PHY_TEST (0x9 << 26) |
| #define | OPM_SATA0_PHY_TEST (0x8 << 26) |
| #define | OPM_ICE_ARM (0x7 << 26) |
| #define | OPM_ICE_FARADAY (0x6 << 26) |
| #define | OPM_PLL_BYPASS (0x5 << 26) |
| #define | OPM_DEBUG (0x4 << 26) |
| #define | OPM_BURN_IN (0x3 << 26) |
| #define | OPM_MBIST (0x2 << 26) |
| #define | OPM_SCAN (0x1 << 26) |
| #define | OPM_REAL (0x0 << 26) |
| #define | FLASH_TYPE_MASK (0x3 << 24) |
| #define | FLASH_TYPE_NAND_2K (0x3 << 24) |
| #define | FLASH_TYPE_NAND_512 (0x2 << 24) |
| #define | FLASH_TYPE_PARALLEL (0x1 << 24) |
| #define | FLASH_TYPE_SERIAL (0x0 << 24) |
| #define | FLASH_WIDTH_16BIT (1 << 23) /* else 8 bit */ |
| #define | FLASH_ATMEL (1 << 23) /* else STM */ |
| #define | FLASH_SIZE_MASK (0x3 << 21) |
| #define | NAND_256M (0x3 << 21) /* and more */ |
| #define | NAND_128M (0x2 << 21) |
| #define | NAND_64M (0x1 << 21) |
| #define | NAND_32M (0x0 << 21) |
| #define | ATMEL_16M (0x3 << 21) /* and more */ |
| #define | ATMEL_8M (0x2 << 21) |
| #define | ATMEL_4M_2M (0x1 << 21) |
| #define | ATMEL_1M (0x0 << 21) /* and less */ |
| #define | STM_32M (1 << 22) /* and more */ |
| #define | STM_16M (0 << 22) /* and less */ |
| #define | FLASH_PARALLEL_HIGH_PIN_CNT (1 << 20) /* else low pin cnt */ |
| #define | CPU_AHB_RATIO_MASK (0x3 << 18) |
| #define | CPU_AHB_1_1 (0x0 << 18) |
| #define | CPU_AHB_3_2 (0x1 << 18) |
| #define | CPU_AHB_24_13 (0x2 << 18) |
| #define | CPU_AHB_2_1 (0x3 << 18) |
| #define | REG_TO_AHB_SPEED(reg) ((((reg) >> 15) & 0x7) * 10 + 130) |
| #define | AHB_SPEED_TO_REG(x) ((((x - 130)) / 10) << 15) |
| #define | OVERRIDE_FLASH_TYPE_SHIFT 16 |
| #define | OVERRIDE_FLASH_WIDTH_SHIFT 16 |
| #define | OVERRIDE_FLASH_SIZE_SHIFT 16 |
| #define | OVERRIDE_CPU_AHB_RATIO_SHIFT 15 |
| #define | OVERRIDE_AHB_SPEED_SHIFT 15 |
| #define | GLOBAL_PLL_CTRL 0x08 |
| #define | PLL_BYPASS (1 << 31) |
| #define | PLL_POWER_DOWN (1 << 8) |
| #define | PLL_CONTROL_Q (0x1F << 0) |
| #define | GLOBAL_RESET 0x0C |
| #define | RESET_GLOBAL (1 << 31) |
| #define | RESET_CPU1 (1 << 30) |
| #define | RESET_TVE (1 << 28) |
| #define | RESET_SATA1 (1 << 27) |
| #define | RESET_SATA0 (1 << 26) |
| #define | RESET_CIR (1 << 25) |
| #define | RESET_EXT_DEV (1 << 24) |
| #define | RESET_WD (1 << 23) |
| #define | RESET_GPIO2 (1 << 22) |
| #define | RESET_GPIO1 (1 << 21) |
| #define | RESET_GPIO0 (1 << 20) |
| #define | RESET_SSP (1 << 19) |
| #define | RESET_UART (1 << 18) |
| #define | RESET_TIMER (1 << 17) |
| #define | RESET_RTC (1 << 16) |
| #define | RESET_INT1 (1 << 15) |
| #define | RESET_INT0 (1 << 14) |
| #define | RESET_LCD (1 << 13) |
| #define | RESET_LPC (1 << 12) |
| #define | RESET_APB (1 << 11) |
| #define | RESET_DMA (1 << 10) |
| #define | RESET_USB1 (1 << 9) |
| #define | RESET_USB0 (1 << 8) |
| #define | RESET_PCI (1 << 7) |
| #define | RESET_GMAC1 (1 << 6) |
| #define | RESET_GMAC0 (1 << 5) |
| #define | RESET_SECURITY (1 << 4) |
| #define | RESET_RAID (1 << 3) |
| #define | RESET_IDE (1 << 2) |
| #define | RESET_FLASH (1 << 1) |
| #define | RESET_DRAM (1 << 0) |
| #define | GLOBAL_IO_DRIVING_CTRL 0x10 |
| #define | DRIVING_CURRENT_MASK 0x3 |
| #define | GPIO1_PADS_31_28_SHIFT 28 |
| #define | GPIO0_PADS_31_16_SHIFT 26 |
| #define | GPIO0_PADS_15_0_SHIFT 24 |
| #define | PCI_AND_EXT_RESET_PADS_SHIFT 22 |
| #define | IDE_PADS_SHIFT 20 |
| #define | GMAC1_PADS_SHIFT 18 |
| #define | GMAC0_PADS_SHIFT 16 |
| #define | DRAM_CLOCK_PADS_SHIFT 8 |
| #define | DRAM_DATA_PADS_SHIFT 4 |
| #define | DRAM_CONTROL_PADS_SHIFT 0 |
| #define | GLOBAL_IO_SLEW_RATE_CTRL 0x14 |
| #define | GPIO1_PADS_31_28_SLOW (1 << 10) |
| #define | GPIO0_PADS_31_16_SLOW (1 << 9) |
| #define | GPIO0_PADS_15_0_SLOW (1 << 8) |
| #define | PCI_PADS_SLOW (1 << 7) |
| #define | IDE_PADS_SLOW (1 << 6) |
| #define | GMAC1_PADS_SLOW (1 << 5) |
| #define | GMAC0_PADS_SLOW (1 << 4) |
| #define | DRAM_CLOCK_PADS_SLOW (1 << 1) |
| #define | DRAM_IO_PADS_SLOW (1 << 0) |
| #define | SKEW_MASK 0xF |
| #define | GLOBAL_IDE_SKEW_CTRL 0x18 |
| #define | IDE1_HOST_STROBE_DELAY_SHIFT 28 |
| #define | IDE1_DEVICE_STROBE_DELAY_SHIFT 24 |
| #define | IDE1_OUTPUT_IO_SKEW_SHIFT 20 |
| #define | IDE1_INPUT_IO_SKEW_SHIFT 16 |
| #define | IDE0_HOST_STROBE_DELAY_SHIFT 12 |
| #define | IDE0_DEVICE_STROBE_DELAY_SHIFT 8 |
| #define | IDE0_OUTPUT_IO_SKEW_SHIFT 4 |
| #define | IDE0_INPUT_IO_SKEW_SHIFT 0 |
| #define | GLOBAL_GMAC_CTRL_SKEW_CTRL 0x1C |
| #define | GMAC1_TXC_SKEW_SHIFT 28 |
| #define | GMAC1_TXEN_SKEW_SHIFT 24 |
| #define | GMAC1_RXC_SKEW_SHIFT 20 |
| #define | GMAC1_RXDV_SKEW_SHIFT 16 |
| #define | GMAC0_TXC_SKEW_SHIFT 12 |
| #define | GMAC0_TXEN_SKEW_SHIFT 8 |
| #define | GMAC0_RXC_SKEW_SHIFT 4 |
| #define | GMAC0_RXDV_SKEW_SHIFT 0 |
| #define | GLOBAL_GMAC0_DATA_SKEW_CTRL 0x20 |
| #define | GLOBAL_GMAC1_DATA_SKEW_CTRL 0x24 |
| #define | GMAC_TXD_SKEW_SHIFT(x) (((x) * 4) + 16) |
| #define | GMAC_RXD_SKEW_SHIFT(x) ((x) * 4) |
| #define | GLOBAL_ARBITRATION0_CTRL 0x28 |
| #define | BOOT_CONTROLLER_HIGH_PRIO (1 << 3) |
| #define | DMA_BUS1_HIGH_PRIO (1 << 2) |
| #define | CPU0_HIGH_PRIO (1 << 0) |
| #define | GLOBAL_ARBITRATION1_CTRL 0x2C |
| #define | TVE_HIGH_PRIO (1 << 9) |
| #define | PCI_HIGH_PRIO (1 << 8) |
| #define | USB1_HIGH_PRIO (1 << 7) |
| #define | USB0_HIGH_PRIO (1 << 6) |
| #define | GMAC1_HIGH_PRIO (1 << 5) |
| #define | GMAC0_HIGH_PRIO (1 << 4) |
| #define | SECURITY_HIGH_PRIO (1 << 3) |
| #define | RAID_HIGH_PRIO (1 << 2) |
| #define | IDE_HIGH_PRIO (1 << 1) |
| #define | DMA_BUS2_HIGH_PRIO (1 << 0) |
| #define | BURST_LENGTH_SHIFT 16 |
| #define | BURST_LENGTH_MASK (0x3F << 16) |
| #define | GLOBAL_MISC_CTRL 0x30 |
| #define | MEMORY_SPACE_SWAP (1 << 31) |
| #define | USB1_PLUG_MINIB (1 << 30) /* else plug is mini-A */ |
| #define | USB0_PLUG_MINIB (1 << 29) |
| #define | GMAC_GMII (1 << 28) |
| #define | GMAC_1_ENABLE (1 << 27) |
| #define | USB1_VBUS_ON (1 << 23) |
| #define | USB0_VBUS_ON (1 << 22) |
| #define | APB_CLKOUT_ENABLE (1 << 21) |
| #define | TVC_CLKOUT_ENABLE (1 << 20) |
| #define | EXT_CLKIN_ENABLE (1 << 19) |
| #define | PCI_66MHZ (1 << 18) /* else 33 MHz */ |
| #define | PCI_CLKOUT_ENABLE (1 << 17) |
| #define | LPC_CLKOUT_ENABLE (1 << 16) |
| #define | USB1_WAKEUP_ON (1 << 15) |
| #define | USB0_WAKEUP_ON (1 << 14) |
| #define | TVC_PADS_ENABLE (1 << 9) |
| #define | SSP_PADS_ENABLE (1 << 8) |
| #define | LCD_PADS_ENABLE (1 << 7) |
| #define | LPC_PADS_ENABLE (1 << 6) |
| #define | PCI_PADS_ENABLE (1 << 5) |
| #define | IDE_PADS_ENABLE (1 << 4) |
| #define | DRAM_PADS_POWER_DOWN (1 << 3) |
| #define | NAND_PADS_DISABLE (1 << 2) |
| #define | PFLASH_PADS_DISABLE (1 << 1) |
| #define | SFLASH_PADS_DISABLE (1 << 0) |
| #define | GLOBAL_CLOCK_CTRL 0x34 |
| #define | POWER_STATE_G0 (1 << 31) |
| #define | POWER_STATE_S1 (1 << 30) /* else it is S3/S4 state */ |
| #define | SECURITY_APB_AHB (1 << 29) |
| #define | PCI_CLKRUN_ENABLE (1 << 16) |
| #define | BOOT_CLK_DISABLE (1 << 13) |
| #define | TVC_CLK_DISABLE (1 << 12) |
| #define | FLASH_CLK_DISABLE (1 << 11) |
| #define | DDR_CLK_DISABLE (1 << 10) |
| #define | PCI_CLK_DISABLE (1 << 9) |
| #define | IDE_CLK_DISABLE (1 << 8) |
| #define | USB1_CLK_DISABLE (1 << 7) |
| #define | USB0_CLK_DISABLE (1 << 6) |
| #define | SATA1_CLK_DISABLE (1 << 5) |
| #define | SATA0_CLK_DISABLE (1 << 4) |
| #define | GMAC1_CLK_DISABLE (1 << 3) |
| #define | GMAC0_CLK_DISABLE (1 << 2) |
| #define | SECURITY_CLK_DISABLE (1 << 1) |
Definition at line 75 of file global_reg.h.
| #define APB_CLKOUT_ENABLE (1 << 21) |
Definition at line 233 of file global_reg.h.
| #define ATMEL_16M (0x3 << 21) /* and more */ |
Definition at line 59 of file global_reg.h.
| #define ATMEL_1M (0x0 << 21) /* and less */ |
Definition at line 62 of file global_reg.h.
| #define ATMEL_4M_2M (0x1 << 21) |
Definition at line 61 of file global_reg.h.
| #define ATMEL_8M (0x2 << 21) |
Definition at line 60 of file global_reg.h.
| #define BOOT_CLK_DISABLE (1 << 13) |
Definition at line 262 of file global_reg.h.
| #define BOOT_CONTROLLER_HIGH_PRIO (1 << 3) |
Definition at line 200 of file global_reg.h.
| #define BURST_LENGTH_MASK (0x3F << 16) |
Definition at line 220 of file global_reg.h.
| #define BURST_LENGTH_SHIFT 16 |
Definition at line 219 of file global_reg.h.
Definition at line 17 of file global_reg.h.
Definition at line 18 of file global_reg.h.
| #define CPU0_HIGH_PRIO (1 << 0) |
Definition at line 202 of file global_reg.h.
| #define CPU_AHB_1_1 (0x0 << 18) |
Definition at line 69 of file global_reg.h.
| #define CPU_AHB_24_13 (0x2 << 18) |
Definition at line 71 of file global_reg.h.
| #define CPU_AHB_2_1 (0x3 << 18) |
Definition at line 72 of file global_reg.h.
| #define CPU_AHB_3_2 (0x1 << 18) |
Definition at line 70 of file global_reg.h.
| #define CPU_AHB_RATIO_MASK (0x3 << 18) |
Definition at line 68 of file global_reg.h.
| #define CPU_BIG_ENDIAN (1 << 31) |
Definition at line 23 of file global_reg.h.
| #define DDR_CLK_DISABLE (1 << 10) |
Definition at line 265 of file global_reg.h.
| #define DMA_BUS1_HIGH_PRIO (1 << 2) |
Definition at line 201 of file global_reg.h.
| #define DMA_BUS2_HIGH_PRIO (1 << 0) |
Definition at line 216 of file global_reg.h.
| #define DRAM_CLOCK_PADS_SHIFT 8 |
Definition at line 140 of file global_reg.h.
| #define DRAM_CLOCK_PADS_SLOW (1 << 1) |
Definition at line 154 of file global_reg.h.
| #define DRAM_CONTROL_PADS_SHIFT 0 |
Definition at line 142 of file global_reg.h.
| #define DRAM_DATA_PADS_SHIFT 4 |
Definition at line 141 of file global_reg.h.
| #define DRAM_IO_PADS_SLOW (1 << 0) |
Definition at line 155 of file global_reg.h.
| #define DRAM_PADS_POWER_DOWN (1 << 3) |
Definition at line 248 of file global_reg.h.
| #define DRIVING_CURRENT_MASK 0x3 |
Definition at line 129 of file global_reg.h.
| #define EXT_CLKIN_ENABLE (1 << 19) |
Definition at line 235 of file global_reg.h.
| #define FLASH_ATMEL (1 << 23) /* else STM */ |
Definition at line 52 of file global_reg.h.
| #define FLASH_CLK_DISABLE (1 << 11) |
Definition at line 264 of file global_reg.h.
Definition at line 66 of file global_reg.h.
| #define FLASH_SIZE_MASK (0x3 << 21) |
Definition at line 54 of file global_reg.h.
| #define FLASH_TYPE_MASK (0x3 << 24) |
Definition at line 44 of file global_reg.h.
| #define FLASH_TYPE_NAND_2K (0x3 << 24) |
Definition at line 45 of file global_reg.h.
| #define FLASH_TYPE_NAND_512 (0x2 << 24) |
Definition at line 46 of file global_reg.h.
| #define FLASH_TYPE_PARALLEL (0x1 << 24) |
Definition at line 47 of file global_reg.h.
| #define FLASH_TYPE_SERIAL (0x0 << 24) |
Definition at line 48 of file global_reg.h.
Definition at line 50 of file global_reg.h.
| #define GLOBAL_ARBITRATION0_CTRL 0x28 |
Definition at line 198 of file global_reg.h.
| #define GLOBAL_ARBITRATION1_CTRL 0x2C |
Definition at line 205 of file global_reg.h.
| #define GLOBAL_CLOCK_CTRL 0x34 |
Definition at line 254 of file global_reg.h.
| #define GLOBAL_GMAC0_DATA_SKEW_CTRL 0x20 |
Definition at line 188 of file global_reg.h.
| #define GLOBAL_GMAC1_DATA_SKEW_CTRL 0x24 |
Definition at line 190 of file global_reg.h.
| #define GLOBAL_GMAC_CTRL_SKEW_CTRL 0x1C |
Definition at line 176 of file global_reg.h.
| #define GLOBAL_ID 0x00 |
Definition at line 15 of file global_reg.h.
| #define GLOBAL_IDE_SKEW_CTRL 0x18 |
Definition at line 164 of file global_reg.h.
| #define GLOBAL_IO_DRIVING_CTRL 0x10 |
Definition at line 127 of file global_reg.h.
| #define GLOBAL_IO_SLEW_RATE_CTRL 0x14 |
Definition at line 145 of file global_reg.h.
| #define GLOBAL_MISC_CTRL 0x30 |
Definition at line 223 of file global_reg.h.
| #define GLOBAL_PLL_CTRL 0x08 |
Definition at line 85 of file global_reg.h.
| #define GLOBAL_RESET 0x0C |
Definition at line 92 of file global_reg.h.
| #define GLOBAL_STATUS 0x04 |
Definition at line 21 of file global_reg.h.
| #define GMAC0_CLK_DISABLE (1 << 2) |
Definition at line 273 of file global_reg.h.
| #define GMAC0_HIGH_PRIO (1 << 4) |
Definition at line 212 of file global_reg.h.
| #define GMAC0_PADS_SHIFT 16 |
Definition at line 138 of file global_reg.h.
| #define GMAC0_PADS_SLOW (1 << 4) |
Definition at line 153 of file global_reg.h.
| #define GMAC0_RXC_SKEW_SHIFT 4 |
Definition at line 184 of file global_reg.h.
| #define GMAC0_RXDV_SKEW_SHIFT 0 |
Definition at line 185 of file global_reg.h.
| #define GMAC0_TXC_SKEW_SHIFT 12 |
Definition at line 182 of file global_reg.h.
| #define GMAC0_TXEN_SKEW_SHIFT 8 |
Definition at line 183 of file global_reg.h.
| #define GMAC1_CLK_DISABLE (1 << 3) |
Definition at line 272 of file global_reg.h.
| #define GMAC1_HIGH_PRIO (1 << 5) |
Definition at line 211 of file global_reg.h.
| #define GMAC1_PADS_SHIFT 18 |
Definition at line 137 of file global_reg.h.
| #define GMAC1_PADS_SLOW (1 << 5) |
Definition at line 152 of file global_reg.h.
| #define GMAC1_RXC_SKEW_SHIFT 20 |
Definition at line 180 of file global_reg.h.
| #define GMAC1_RXDV_SKEW_SHIFT 16 |
Definition at line 181 of file global_reg.h.
| #define GMAC1_TXC_SKEW_SHIFT 28 |
Definition at line 178 of file global_reg.h.
| #define GMAC1_TXEN_SKEW_SHIFT 24 |
Definition at line 179 of file global_reg.h.
| #define GMAC_1_ENABLE (1 << 27) |
Definition at line 229 of file global_reg.h.
| #define GMAC_GMII (1 << 28) |
Definition at line 228 of file global_reg.h.
Definition at line 193 of file global_reg.h.
Definition at line 192 of file global_reg.h.
| #define GPIO0_PADS_15_0_SHIFT 24 |
Definition at line 134 of file global_reg.h.
| #define GPIO0_PADS_15_0_SLOW (1 << 8) |
Definition at line 149 of file global_reg.h.
| #define GPIO0_PADS_31_16_SHIFT 26 |
Definition at line 133 of file global_reg.h.
| #define GPIO0_PADS_31_16_SLOW (1 << 9) |
Definition at line 148 of file global_reg.h.
| #define GPIO1_PADS_31_28_SHIFT 28 |
Definition at line 132 of file global_reg.h.
| #define GPIO1_PADS_31_28_SLOW (1 << 10) |
Definition at line 147 of file global_reg.h.
| #define IDE0_DEVICE_STROBE_DELAY_SHIFT 8 |
Definition at line 171 of file global_reg.h.
| #define IDE0_HOST_STROBE_DELAY_SHIFT 12 |
Definition at line 170 of file global_reg.h.
| #define IDE0_INPUT_IO_SKEW_SHIFT 0 |
Definition at line 173 of file global_reg.h.
| #define IDE0_OUTPUT_IO_SKEW_SHIFT 4 |
Definition at line 172 of file global_reg.h.
| #define IDE1_DEVICE_STROBE_DELAY_SHIFT 24 |
Definition at line 167 of file global_reg.h.
| #define IDE1_HOST_STROBE_DELAY_SHIFT 28 |
Definition at line 166 of file global_reg.h.
| #define IDE1_INPUT_IO_SKEW_SHIFT 16 |
Definition at line 169 of file global_reg.h.
| #define IDE1_OUTPUT_IO_SKEW_SHIFT 20 |
Definition at line 168 of file global_reg.h.
| #define IDE_CLK_DISABLE (1 << 8) |
Definition at line 267 of file global_reg.h.
| #define IDE_HIGH_PRIO (1 << 1) |
Definition at line 215 of file global_reg.h.
| #define IDE_PADS_ENABLE (1 << 4) |
Definition at line 247 of file global_reg.h.
| #define IDE_PADS_SHIFT 20 |
Definition at line 136 of file global_reg.h.
| #define IDE_PADS_SLOW (1 << 6) |
Definition at line 151 of file global_reg.h.
| #define LCD_PADS_ENABLE (1 << 7) |
Definition at line 244 of file global_reg.h.
| #define LPC_CLKOUT_ENABLE (1 << 16) |
Definition at line 238 of file global_reg.h.
| #define LPC_PADS_ENABLE (1 << 6) |
Definition at line 245 of file global_reg.h.
| #define MEMORY_SPACE_SWAP (1 << 31) |
Definition at line 225 of file global_reg.h.
| #define NAND_128M (0x2 << 21) |
Definition at line 56 of file global_reg.h.
| #define NAND_256M (0x3 << 21) /* and more */ |
Definition at line 55 of file global_reg.h.
| #define NAND_32M (0x0 << 21) |
Definition at line 58 of file global_reg.h.
| #define NAND_64M (0x1 << 21) |
Definition at line 57 of file global_reg.h.
| #define NAND_PADS_DISABLE (1 << 2) |
Definition at line 249 of file global_reg.h.
| #define OPERATION_MODE_MASK (0xF << 26) |
Definition at line 26 of file global_reg.h.
| #define OPM_BURN_IN (0x3 << 26) |
Definition at line 39 of file global_reg.h.
| #define OPM_DEBUG (0x4 << 26) |
Definition at line 38 of file global_reg.h.
| #define OPM_DIRECT_BOOT (0xC << 26) |
Definition at line 30 of file global_reg.h.
| #define OPM_ICE_ARM (0x7 << 26) |
Definition at line 35 of file global_reg.h.
| #define OPM_ICE_FARADAY (0x6 << 26) |
Definition at line 36 of file global_reg.h.
| #define OPM_IDDQ (0xF << 26) |
Definition at line 27 of file global_reg.h.
| #define OPM_MBIST (0x2 << 26) |
Definition at line 40 of file global_reg.h.
| #define OPM_NAND (0xE << 26) |
Definition at line 28 of file global_reg.h.
| #define OPM_PLL_BYPASS (0x5 << 26) |
Definition at line 37 of file global_reg.h.
| #define OPM_REAL (0x0 << 26) |
Definition at line 42 of file global_reg.h.
| #define OPM_RING (0xD << 26) |
Definition at line 29 of file global_reg.h.
| #define OPM_SATA0_PHY_TEST (0x8 << 26) |
Definition at line 34 of file global_reg.h.
| #define OPM_SATA1_PHY_TEST (0x9 << 26) |
Definition at line 33 of file global_reg.h.
| #define OPM_SCAN (0x1 << 26) |
Definition at line 41 of file global_reg.h.
| #define OPM_USB0_PHY_TEST (0xA << 26) |
Definition at line 32 of file global_reg.h.
| #define OPM_USB1_PHY_TEST (0xB << 26) |
Definition at line 31 of file global_reg.h.
| #define OVERRIDE_AHB_SPEED_SHIFT 15 |
Definition at line 82 of file global_reg.h.
| #define OVERRIDE_CPU_AHB_RATIO_SHIFT 15 |
Definition at line 81 of file global_reg.h.
| #define OVERRIDE_FLASH_SIZE_SHIFT 16 |
Definition at line 80 of file global_reg.h.
| #define OVERRIDE_FLASH_TYPE_SHIFT 16 |
Definition at line 78 of file global_reg.h.
| #define OVERRIDE_FLASH_WIDTH_SHIFT 16 |
Definition at line 79 of file global_reg.h.
Definition at line 236 of file global_reg.h.
| #define PCI_AND_EXT_RESET_PADS_SHIFT 22 |
Definition at line 135 of file global_reg.h.
| #define PCI_CLK_DISABLE (1 << 9) |
Definition at line 266 of file global_reg.h.
| #define PCI_CLKOUT_ENABLE (1 << 17) |
Definition at line 237 of file global_reg.h.
| #define PCI_CLKRUN_ENABLE (1 << 16) |
Definition at line 261 of file global_reg.h.
| #define PCI_HIGH_PRIO (1 << 8) |
Definition at line 208 of file global_reg.h.
| #define PCI_PADS_ENABLE (1 << 5) |
Definition at line 246 of file global_reg.h.
| #define PCI_PADS_SLOW (1 << 7) |
Definition at line 150 of file global_reg.h.
| #define PFLASH_PADS_DISABLE (1 << 1) |
Definition at line 250 of file global_reg.h.
| #define PLL_BYPASS (1 << 31) |
Definition at line 87 of file global_reg.h.
| #define PLL_CONTROL_Q (0x1F << 0) |
Definition at line 89 of file global_reg.h.
| #define PLL_OSC_30M (1 << 30) /* else 60MHz */ |
Definition at line 24 of file global_reg.h.
| #define PLL_POWER_DOWN (1 << 8) |
Definition at line 88 of file global_reg.h.
| #define POWER_STATE_G0 (1 << 31) |
Definition at line 256 of file global_reg.h.
Definition at line 257 of file global_reg.h.
| #define RAID_HIGH_PRIO (1 << 2) |
Definition at line 214 of file global_reg.h.
Definition at line 74 of file global_reg.h.
| #define RESET_APB (1 << 11) |
Definition at line 113 of file global_reg.h.
| #define RESET_CIR (1 << 25) |
Definition at line 99 of file global_reg.h.
| #define RESET_CPU1 (1 << 30) |
Definition at line 95 of file global_reg.h.
| #define RESET_DMA (1 << 10) |
Definition at line 114 of file global_reg.h.
| #define RESET_DRAM (1 << 0) |
Definition at line 124 of file global_reg.h.
| #define RESET_EXT_DEV (1 << 24) |
Definition at line 100 of file global_reg.h.
| #define RESET_FLASH (1 << 1) |
Definition at line 123 of file global_reg.h.
| #define RESET_GLOBAL (1 << 31) |
Definition at line 94 of file global_reg.h.
| #define RESET_GMAC0 (1 << 5) |
Definition at line 119 of file global_reg.h.
| #define RESET_GMAC1 (1 << 6) |
Definition at line 118 of file global_reg.h.
| #define RESET_GPIO0 (1 << 20) |
Definition at line 104 of file global_reg.h.
| #define RESET_GPIO1 (1 << 21) |
Definition at line 103 of file global_reg.h.
| #define RESET_GPIO2 (1 << 22) |
Definition at line 102 of file global_reg.h.
| #define RESET_IDE (1 << 2) |
Definition at line 122 of file global_reg.h.
| #define RESET_INT0 (1 << 14) |
Definition at line 110 of file global_reg.h.
| #define RESET_INT1 (1 << 15) |
Definition at line 109 of file global_reg.h.
| #define RESET_LCD (1 << 13) |
Definition at line 111 of file global_reg.h.
| #define RESET_LPC (1 << 12) |
Definition at line 112 of file global_reg.h.
| #define RESET_PCI (1 << 7) |
Definition at line 117 of file global_reg.h.
| #define RESET_RAID (1 << 3) |
Definition at line 121 of file global_reg.h.
| #define RESET_RTC (1 << 16) |
Definition at line 108 of file global_reg.h.
| #define RESET_SATA0 (1 << 26) |
Definition at line 98 of file global_reg.h.
| #define RESET_SATA1 (1 << 27) |
Definition at line 97 of file global_reg.h.
| #define RESET_SECURITY (1 << 4) |
Definition at line 120 of file global_reg.h.
| #define RESET_SSP (1 << 19) |
Definition at line 105 of file global_reg.h.
| #define RESET_TIMER (1 << 17) |
Definition at line 107 of file global_reg.h.
| #define RESET_TVE (1 << 28) |
Definition at line 96 of file global_reg.h.
| #define RESET_UART (1 << 18) |
Definition at line 106 of file global_reg.h.
| #define RESET_USB0 (1 << 8) |
Definition at line 116 of file global_reg.h.
| #define RESET_USB1 (1 << 9) |
Definition at line 115 of file global_reg.h.
| #define RESET_WD (1 << 23) |
Definition at line 101 of file global_reg.h.
| #define SATA0_CLK_DISABLE (1 << 4) |
Definition at line 271 of file global_reg.h.
| #define SATA1_CLK_DISABLE (1 << 5) |
Definition at line 270 of file global_reg.h.
| #define SECURITY_APB_AHB (1 << 29) |
Definition at line 258 of file global_reg.h.
| #define SECURITY_CLK_DISABLE (1 << 1) |
Definition at line 274 of file global_reg.h.
| #define SECURITY_HIGH_PRIO (1 << 3) |
Definition at line 213 of file global_reg.h.
| #define SFLASH_PADS_DISABLE (1 << 0) |
Definition at line 251 of file global_reg.h.
| #define SKEW_MASK 0xF |
Definition at line 161 of file global_reg.h.
| #define SSP_PADS_ENABLE (1 << 8) |
Definition at line 243 of file global_reg.h.
| #define STM_16M (0 << 22) /* and less */ |
Definition at line 64 of file global_reg.h.
| #define STM_32M (1 << 22) /* and more */ |
Definition at line 63 of file global_reg.h.
| #define TVC_CLK_DISABLE (1 << 12) |
Definition at line 263 of file global_reg.h.
| #define TVC_CLKOUT_ENABLE (1 << 20) |
Definition at line 234 of file global_reg.h.
| #define TVC_PADS_ENABLE (1 << 9) |
Definition at line 242 of file global_reg.h.
| #define TVE_HIGH_PRIO (1 << 9) |
Definition at line 207 of file global_reg.h.
| #define USB0_CLK_DISABLE (1 << 6) |
Definition at line 269 of file global_reg.h.
| #define USB0_HIGH_PRIO (1 << 6) |
Definition at line 210 of file global_reg.h.
| #define USB0_PLUG_MINIB (1 << 29) |
Definition at line 227 of file global_reg.h.
| #define USB0_VBUS_ON (1 << 22) |
Definition at line 232 of file global_reg.h.
| #define USB0_WAKEUP_ON (1 << 14) |
Definition at line 240 of file global_reg.h.
| #define USB1_CLK_DISABLE (1 << 7) |
Definition at line 268 of file global_reg.h.
| #define USB1_HIGH_PRIO (1 << 7) |
Definition at line 209 of file global_reg.h.
Definition at line 226 of file global_reg.h.
| #define USB1_VBUS_ON (1 << 23) |
Definition at line 231 of file global_reg.h.
| #define USB1_WAKEUP_ON (1 << 15) |
Definition at line 239 of file global_reg.h.
1.8.2