Data Structures
struct	control_block_extended_exc_detail

struct	gru_instruction_bits

struct	gru_instruction

union	gru_mesqhead

struct	gru_control_block_status

Macros
#define	CBS_IDLE 0

#define	CBS_EXCEPTION 1

#define	CBS_ACTIVE 2

#define	CBS_CALL_OS 3

#define	CBSS_MSG_QUEUE_MASK 7

#define	CBSS_IMPLICIT_ABORT_ACTIVE_MASK 8

#define	CBSS_NO_ERROR 0

#define	CBSS_LB_OVERFLOWED 1

#define	CBSS_QLIMIT_REACHED 2

#define	CBSS_PAGE_OVERFLOW 3

#define	CBSS_AMO_NACKED 4

#define	CBSS_PUT_NACKED 5

#define	GRU_CB_ICMD_SHFT 0

#define	GRU_CB_ICMD_MASK 0x1

#define	GRU_CB_XTYPE_SHFT 8

#define	GRU_CB_XTYPE_MASK 0x7

#define	GRU_CB_IAA0_SHFT 11

#define	GRU_CB_IAA0_MASK 0x3

#define	GRU_CB_IAA1_SHFT 13

#define	GRU_CB_IAA1_MASK 0x3

#define	GRU_CB_IMA_SHFT 1

#define	GRU_CB_IMA_MASK 0x3

#define	GRU_CB_OPC_SHFT 16

#define	GRU_CB_OPC_MASK 0xff

#define	GRU_CB_EXOPC_SHFT 24

#define	GRU_CB_EXOPC_MASK 0xff

#define	GRU_IDEF2_SHFT 32

#define	GRU_IDEF2_MASK 0x3ffff

#define	GRU_ISTATUS_SHFT 56

#define	GRU_ISTATUS_MASK 0x3

#define	OP_NOP 0x00

#define	OP_BCOPY 0x01

#define	OP_VLOAD 0x02

#define	OP_IVLOAD 0x03

#define	OP_VSTORE 0x04

#define	OP_IVSTORE 0x05

#define	OP_VSET 0x06

#define	OP_IVSET 0x07

#define	OP_MESQ 0x08

#define	OP_GAMXR 0x09

#define	OP_GAMIR 0x0a

#define	OP_GAMIRR 0x0b

#define	OP_GAMER 0x0c

#define	OP_GAMERR 0x0d

#define	OP_BSTORE 0x0e

#define	OP_VFLUSH 0x0f

#define	EOP_IR_FETCH 0x01 /* Plain fetch of memory */

#define	EOP_IR_CLR 0x02 /* Fetch and clear */

#define	EOP_IR_INC 0x05 /* Fetch and increment */

#define	EOP_IR_DEC 0x07 /* Fetch and decrement */

#define	EOP_IR_QCHK1 0x0d /* Queue check, 64 byte msg */

#define	EOP_IR_QCHK2 0x0e /* Queue check, 128 byte msg */

#define	EOP_IRR_FETCH 0x01 /* Registered fetch of memory */

#define	EOP_IRR_CLR 0x02 /* Registered fetch and clear */

#define	EOP_IRR_INC 0x05 /* Registered fetch and increment */

#define	EOP_IRR_DEC 0x07 /* Registered fetch and decrement */

#define	EOP_IRR_DECZ 0x0f /* Registered fetch and decrement, update on zero*/

#define	EOP_ER_SWAP 0x00 /* Exchange argument and memory */

#define	EOP_ER_OR 0x01 /* Logical OR with memory */

#define	EOP_ER_AND 0x02 /* Logical AND with memory */

#define	EOP_ER_XOR 0x03 /* Logical XOR with memory */

#define	EOP_ER_ADD 0x04 /* Add value to memory */

#define	EOP_ER_CSWAP 0x08 /* Compare with operand2, write operand1 if match*/

#define	EOP_ER_CADD 0x0c /* Queue check, operand164 byte msg /

#define	EOP_ERR_SWAP 0x00 /* Exchange argument and memory */

#define	EOP_ERR_OR 0x01 /* Logical OR with memory */

#define	EOP_ERR_AND 0x02 /* Logical AND with memory */

#define	EOP_ERR_XOR 0x03 /* Logical XOR with memory */

#define	EOP_ERR_ADD 0x04 /* Add value to memory */

#define	EOP_ERR_CSWAP 0x08 /* Compare with operand2, write operand1 if match*/

#define	EOP_ERR_EPOLL 0x09 /* Poll for equality */

#define	EOP_ERR_NPOLL 0x0a /* Poll for inequality */

#define	EOP_XR_CSWAP 0x0b /* Masked compare exchange */

#define	XTYPE_B 0x0 /* byte */

#define	XTYPE_S 0x1 /* short (2-byte) */

#define	XTYPE_W 0x2 /* word (4-byte) */

#define	XTYPE_DW 0x3 /* doubleword (8-byte) */

#define	XTYPE_CL 0x6 /* cacheline (64-byte) */

#define	IAA_RAM 0x0 /* normal cached RAM access */

#define	IAA_NCRAM 0x2 /* noncoherent RAM access */

#define	IAA_MMIO 0x1 /* noncoherent memory-mapped I/O space */

#define	IAA_REGISTER 0x3 /* memory-mapped registers, etc. */

#define	IMA_MAPPED 0x0 /* Virtual mode */

#define	IMA_CB_DELAY 0x1 /* hold read responses until status changes */

#define	IMA_UNMAPPED 0x2 /* bypass the TLBs (OS only) */

#define	IMA_INTERRUPT 0x4 /* Interrupt when instruction completes */

#define	CBE_CAUSE_RI (1 << 0)

#define	CBE_CAUSE_INVALID_INSTRUCTION (1 << 1)

#define	CBE_CAUSE_UNMAPPED_MODE_FORBIDDEN (1 << 2)

#define	CBE_CAUSE_PE_CHECK_DATA_ERROR (1 << 3)

#define	CBE_CAUSE_IAA_GAA_MISMATCH (1 << 4)

#define	CBE_CAUSE_DATA_SEGMENT_LIMIT_EXCEPTION (1 << 5)

#define	CBE_CAUSE_OS_FATAL_TLB_FAULT (1 << 6)

#define	CBE_CAUSE_EXECUTION_HW_ERROR (1 << 7)

#define	CBE_CAUSE_TLBHW_ERROR (1 << 8)

#define	CBE_CAUSE_RA_REQUEST_TIMEOUT (1 << 9)

#define	CBE_CAUSE_HA_REQUEST_TIMEOUT (1 << 10)

#define	CBE_CAUSE_RA_RESPONSE_FATAL (1 << 11)

#define	CBE_CAUSE_RA_RESPONSE_NON_FATAL (1 << 12)

#define	CBE_CAUSE_HA_RESPONSE_FATAL (1 << 13)

#define	CBE_CAUSE_HA_RESPONSE_NON_FATAL (1 << 14)

#define	CBE_CAUSE_ADDRESS_SPACE_DECODE_ERROR (1 << 15)

#define	CBE_CAUSE_PROTOCOL_STATE_DATA_ERROR (1 << 16)

#define	CBE_CAUSE_RA_RESPONSE_DATA_ERROR (1 << 17)

#define	CBE_CAUSE_HA_RESPONSE_DATA_ERROR (1 << 18)

#define	CBE_CAUSE_FORCED_ERROR (1 << 19)

#define	CBR_EXS_ABORT_OCC_BIT 0

#define	CBR_EXS_INT_OCC_BIT 1

#define	CBR_EXS_PENDING_BIT 2

#define	CBR_EXS_QUEUED_BIT 3

#define	CBR_EXS_TLB_INVAL_BIT 4

#define	CBR_EXS_EXCEPTION_BIT 5

#define	CBR_EXS_CB_INT_PENDING_BIT 6

#define	CBR_EXS_ABORT_OCC (1 << CBR_EXS_ABORT_OCC_BIT)

#define	CBR_EXS_INT_OCC (1 << CBR_EXS_INT_OCC_BIT)

#define	CBR_EXS_PENDING (1 << CBR_EXS_PENDING_BIT)

#define	CBR_EXS_QUEUED (1 << CBR_EXS_QUEUED_BIT)

#define	CBR_EXS_TLB_INVAL (1 << CBR_EXS_TLB_INVAL_BIT)

#define	CBR_EXS_EXCEPTION (1 << CBR_EXS_EXCEPTION_BIT)

#define	CBR_EXS_CB_INT_PENDING (1 << CBR_EXS_CB_INT_PENDING_BIT)

#define	EXCEPTION_RETRY_BITS

#define	CB_IMA(h) ((h) \| IMA_UNMAPPED)

#define	GRU_DINDEX(i) ((i) * GRU_CACHE_LINE_BYTES)

#define	GRU_EXC_STR_SIZE 256

Functions
int	gru_check_status_proc (void *cb)

int	gru_wait_proc (void *cb)

void	gru_wait_abort_proc (void *cb)

int	gru_get_cb_exception_detail (void cb, struct control_block_extended_exc_detail excdet)

Macro Definition Documentation

#define CB_IMA ( h ) ((h) | IMA_UNMAPPED)

Definition at line 349 of file gru_instructions.h.

#define CBE_CAUSE_ADDRESS_SPACE_DECODE_ERROR (1 << 15)

Definition at line 265 of file gru_instructions.h.

#define CBE_CAUSE_DATA_SEGMENT_LIMIT_EXCEPTION (1 << 5)

Definition at line 255 of file gru_instructions.h.

#define CBE_CAUSE_EXECUTION_HW_ERROR (1 << 7)

Definition at line 257 of file gru_instructions.h.

#define CBE_CAUSE_FORCED_ERROR (1 << 19)

Definition at line 269 of file gru_instructions.h.

#define CBE_CAUSE_HA_REQUEST_TIMEOUT (1 << 10)

Definition at line 260 of file gru_instructions.h.

#define CBE_CAUSE_HA_RESPONSE_DATA_ERROR (1 << 18)

Definition at line 268 of file gru_instructions.h.

#define CBE_CAUSE_HA_RESPONSE_FATAL (1 << 13)

Definition at line 263 of file gru_instructions.h.

#define CBE_CAUSE_HA_RESPONSE_NON_FATAL (1 << 14)

Definition at line 264 of file gru_instructions.h.

#define CBE_CAUSE_IAA_GAA_MISMATCH (1 << 4)

Definition at line 254 of file gru_instructions.h.

#define CBE_CAUSE_INVALID_INSTRUCTION (1 << 1)

Definition at line 251 of file gru_instructions.h.

#define CBE_CAUSE_OS_FATAL_TLB_FAULT (1 << 6)

Definition at line 256 of file gru_instructions.h.

#define CBE_CAUSE_PE_CHECK_DATA_ERROR (1 << 3)

Definition at line 253 of file gru_instructions.h.

#define CBE_CAUSE_PROTOCOL_STATE_DATA_ERROR (1 << 16)

Definition at line 266 of file gru_instructions.h.

#define CBE_CAUSE_RA_REQUEST_TIMEOUT (1 << 9)

Definition at line 259 of file gru_instructions.h.

#define CBE_CAUSE_RA_RESPONSE_DATA_ERROR (1 << 17)

Definition at line 267 of file gru_instructions.h.

#define CBE_CAUSE_RA_RESPONSE_FATAL (1 << 11)

Definition at line 261 of file gru_instructions.h.

#define CBE_CAUSE_RA_RESPONSE_NON_FATAL (1 << 12)

Definition at line 262 of file gru_instructions.h.

#define CBE_CAUSE_RI (1 << 0)

Definition at line 250 of file gru_instructions.h.

#define CBE_CAUSE_TLBHW_ERROR (1 << 8)

Definition at line 258 of file gru_instructions.h.

#define CBE_CAUSE_UNMAPPED_MODE_FORBIDDEN (1 << 2)

Definition at line 252 of file gru_instructions.h.

#define CBR_EXS_ABORT_OCC (1 << CBR_EXS_ABORT_OCC_BIT)

Definition at line 280 of file gru_instructions.h.

#define CBR_EXS_ABORT_OCC_BIT 0

Definition at line 272 of file gru_instructions.h.

#define CBR_EXS_CB_INT_PENDING (1 << CBR_EXS_CB_INT_PENDING_BIT)

Definition at line 286 of file gru_instructions.h.

#define CBR_EXS_CB_INT_PENDING_BIT 6

Definition at line 278 of file gru_instructions.h.

#define CBR_EXS_EXCEPTION (1 << CBR_EXS_EXCEPTION_BIT)

Definition at line 285 of file gru_instructions.h.

#define CBR_EXS_EXCEPTION_BIT 5

Definition at line 277 of file gru_instructions.h.

#define CBR_EXS_INT_OCC (1 << CBR_EXS_INT_OCC_BIT)

Definition at line 281 of file gru_instructions.h.

#define CBR_EXS_INT_OCC_BIT 1

Definition at line 273 of file gru_instructions.h.

#define CBR_EXS_PENDING (1 << CBR_EXS_PENDING_BIT)

Definition at line 282 of file gru_instructions.h.

#define CBR_EXS_PENDING_BIT 2

Definition at line 274 of file gru_instructions.h.

#define CBR_EXS_QUEUED (1 << CBR_EXS_QUEUED_BIT)

Definition at line 283 of file gru_instructions.h.

#define CBR_EXS_QUEUED_BIT 3

Definition at line 275 of file gru_instructions.h.

#define CBR_EXS_TLB_INVAL (1 << CBR_EXS_TLB_INVAL_BIT)

Definition at line 284 of file gru_instructions.h.

#define CBR_EXS_TLB_INVAL_BIT 4

Definition at line 276 of file gru_instructions.h.

#define CBS_ACTIVE 2

Definition at line 59 of file gru_instructions.h.

#define CBS_CALL_OS 3

Definition at line 60 of file gru_instructions.h.

#define CBS_EXCEPTION 1

Definition at line 58 of file gru_instructions.h.

#define CBS_IDLE 0

Definition at line 57 of file gru_instructions.h.

#define CBSS_AMO_NACKED 4

Definition at line 71 of file gru_instructions.h.

#define CBSS_IMPLICIT_ABORT_ACTIVE_MASK 8

Definition at line 64 of file gru_instructions.h.

#define CBSS_LB_OVERFLOWED 1

Definition at line 68 of file gru_instructions.h.

#define CBSS_MSG_QUEUE_MASK 7

Definition at line 63 of file gru_instructions.h.

#define CBSS_NO_ERROR 0

Definition at line 67 of file gru_instructions.h.

#define CBSS_PAGE_OVERFLOW 3

Definition at line 70 of file gru_instructions.h.

#define CBSS_PUT_NACKED 5

Definition at line 72 of file gru_instructions.h.

#define CBSS_QLIMIT_REACHED 2

Definition at line 69 of file gru_instructions.h.

#define EOP_ER_ADD 0x04 /* Add value to memory */

Definition at line 210 of file gru_instructions.h.

#define EOP_ER_AND 0x02 /* Logical AND with memory */

Definition at line 208 of file gru_instructions.h.

#define EOP_ER_CADD 0x0c /* Queue check, operand1*64 byte msg */

Definition at line 212 of file gru_instructions.h.

#define EOP_ER_CSWAP 0x08 /* Compare with operand2, write operand1 if match*/

Definition at line 211 of file gru_instructions.h.

#define EOP_ER_OR 0x01 /* Logical OR with memory */

Definition at line 207 of file gru_instructions.h.

#define EOP_ER_SWAP 0x00 /* Exchange argument and memory */

Definition at line 206 of file gru_instructions.h.

#define EOP_ER_XOR 0x03 /* Logical XOR with memory */

Definition at line 209 of file gru_instructions.h.

#define EOP_ERR_ADD 0x04 /* Add value to memory */

Definition at line 219 of file gru_instructions.h.

#define EOP_ERR_AND 0x02 /* Logical AND with memory */

Definition at line 217 of file gru_instructions.h.

#define EOP_ERR_CSWAP 0x08 /* Compare with operand2, write operand1 if match*/

Definition at line 220 of file gru_instructions.h.

#define EOP_ERR_EPOLL 0x09 /* Poll for equality */

Definition at line 221 of file gru_instructions.h.

#define EOP_ERR_NPOLL 0x0a /* Poll for inequality */

Definition at line 222 of file gru_instructions.h.

#define EOP_ERR_OR 0x01 /* Logical OR with memory */

Definition at line 216 of file gru_instructions.h.

#define EOP_ERR_SWAP 0x00 /* Exchange argument and memory */

Definition at line 215 of file gru_instructions.h.

#define EOP_ERR_XOR 0x03 /* Logical XOR with memory */

Definition at line 218 of file gru_instructions.h.

#define EOP_IR_CLR 0x02 /* Fetch and clear */

Definition at line 192 of file gru_instructions.h.

#define EOP_IR_DEC 0x07 /* Fetch and decrement */

Definition at line 194 of file gru_instructions.h.

#define EOP_IR_FETCH 0x01 /* Plain fetch of memory */

Definition at line 191 of file gru_instructions.h.

#define EOP_IR_INC 0x05 /* Fetch and increment */

Definition at line 193 of file gru_instructions.h.

#define EOP_IR_QCHK1 0x0d /* Queue check, 64 byte msg */

Definition at line 195 of file gru_instructions.h.

#define EOP_IR_QCHK2 0x0e /* Queue check, 128 byte msg */

Definition at line 196 of file gru_instructions.h.

#define EOP_IRR_CLR 0x02 /* Registered fetch and clear */

Definition at line 200 of file gru_instructions.h.

#define EOP_IRR_DEC 0x07 /* Registered fetch and decrement */

Definition at line 202 of file gru_instructions.h.

#define EOP_IRR_DECZ 0x0f /* Registered fetch and decrement, update on zero*/

Definition at line 203 of file gru_instructions.h.

#define EOP_IRR_FETCH 0x01 /* Registered fetch of memory */

Definition at line 199 of file gru_instructions.h.

#define EOP_IRR_INC 0x05 /* Registered fetch and increment */

Definition at line 201 of file gru_instructions.h.

#define EOP_XR_CSWAP 0x0b /* Masked compare exchange */

Definition at line 225 of file gru_instructions.h.

#define EXCEPTION_RETRY_BITS

Value:

(CBE_CAUSE_EXECUTION_HW_ERROR |     \
                  CBE_CAUSE_TLBHW_ERROR |           \
                  CBE_CAUSE_RA_REQUEST_TIMEOUT |        \
                  CBE_CAUSE_RA_RESPONSE_NON_FATAL |     \
                  CBE_CAUSE_HA_RESPONSE_NON_FATAL |     \
                  CBE_CAUSE_RA_RESPONSE_DATA_ERROR |    \
                  CBE_CAUSE_HA_RESPONSE_DATA_ERROR      \
                  )

Definition at line 292 of file gru_instructions.h.

#define GRU_CB_EXOPC_MASK 0xff

Definition at line 163 of file gru_instructions.h.

#define GRU_CB_EXOPC_SHFT 24

Definition at line 162 of file gru_instructions.h.

#define GRU_CB_IAA0_MASK 0x3

Definition at line 155 of file gru_instructions.h.

#define GRU_CB_IAA0_SHFT 11

Definition at line 154 of file gru_instructions.h.

#define GRU_CB_IAA1_MASK 0x3

Definition at line 157 of file gru_instructions.h.

#define GRU_CB_IAA1_SHFT 13

Definition at line 156 of file gru_instructions.h.

#define GRU_CB_ICMD_MASK 0x1

Definition at line 151 of file gru_instructions.h.

#define GRU_CB_ICMD_SHFT 0

Definition at line 150 of file gru_instructions.h.

#define GRU_CB_IMA_MASK 0x3

Definition at line 159 of file gru_instructions.h.

#define GRU_CB_IMA_SHFT 1

Definition at line 158 of file gru_instructions.h.

#define GRU_CB_OPC_MASK 0xff

Definition at line 161 of file gru_instructions.h.

#define GRU_CB_OPC_SHFT 16

Definition at line 160 of file gru_instructions.h.

#define GRU_CB_XTYPE_MASK 0x7

Definition at line 153 of file gru_instructions.h.

#define GRU_CB_XTYPE_SHFT 8

Definition at line 152 of file gru_instructions.h.

#define GRU_DINDEX ( i ) ((i) * GRU_CACHE_LINE_BYTES)

Definition at line 352 of file gru_instructions.h.

#define GRU_EXC_STR_SIZE 256

Definition at line 618 of file gru_instructions.h.

#define GRU_IDEF2_MASK 0x3ffff

Definition at line 165 of file gru_instructions.h.

#define GRU_IDEF2_SHFT 32

Definition at line 164 of file gru_instructions.h.

#define GRU_ISTATUS_MASK 0x3

Definition at line 167 of file gru_instructions.h.

#define GRU_ISTATUS_SHFT 56

Definition at line 166 of file gru_instructions.h.

#define IAA_MMIO 0x1 /* noncoherent memory-mapped I/O space */

Definition at line 239 of file gru_instructions.h.

#define IAA_NCRAM 0x2 /* noncoherent RAM access */

Definition at line 238 of file gru_instructions.h.

#define IAA_RAM 0x0 /* normal cached RAM access */

Definition at line 237 of file gru_instructions.h.

#define IAA_REGISTER 0x3 /* memory-mapped registers, etc. */

Definition at line 240 of file gru_instructions.h.

#define IMA_CB_DELAY 0x1 /* hold read responses until status changes */

Definition at line 245 of file gru_instructions.h.

#define IMA_INTERRUPT 0x4 /* Interrupt when instruction completes */

Definition at line 247 of file gru_instructions.h.

#define IMA_MAPPED 0x0 /* Virtual mode */

Definition at line 244 of file gru_instructions.h.

#define IMA_UNMAPPED 0x2 /* bypass the TLBs (OS only) */

Definition at line 246 of file gru_instructions.h.

#define OP_BCOPY 0x01

Definition at line 171 of file gru_instructions.h.

#define OP_BSTORE 0x0e

Definition at line 184 of file gru_instructions.h.

#define OP_GAMER 0x0c

Definition at line 182 of file gru_instructions.h.

#define OP_GAMERR 0x0d

Definition at line 183 of file gru_instructions.h.

#define OP_GAMIR 0x0a

Definition at line 180 of file gru_instructions.h.

#define OP_GAMIRR 0x0b

Definition at line 181 of file gru_instructions.h.

#define OP_GAMXR 0x09

Definition at line 179 of file gru_instructions.h.

#define OP_IVLOAD 0x03

Definition at line 173 of file gru_instructions.h.

#define OP_IVSET 0x07

Definition at line 177 of file gru_instructions.h.

#define OP_IVSTORE 0x05

Definition at line 175 of file gru_instructions.h.

#define OP_MESQ 0x08

Definition at line 178 of file gru_instructions.h.

#define OP_NOP 0x00

Definition at line 170 of file gru_instructions.h.

#define OP_VFLUSH 0x0f

Definition at line 185 of file gru_instructions.h.

#define OP_VLOAD 0x02

Definition at line 172 of file gru_instructions.h.

#define OP_VSET 0x06

Definition at line 176 of file gru_instructions.h.

#define OP_VSTORE 0x04

Definition at line 174 of file gru_instructions.h.

#define XTYPE_B 0x0 /* byte */

Definition at line 229 of file gru_instructions.h.

#define XTYPE_CL 0x6 /* cacheline (64-byte) */

Definition at line 233 of file gru_instructions.h.

#define XTYPE_DW 0x3 /* doubleword (8-byte) */

Definition at line 232 of file gru_instructions.h.

#define XTYPE_S 0x1 /* short (2-byte) */

Definition at line 230 of file gru_instructions.h.

#define XTYPE_W 0x2 /* word (4-byte) */

Definition at line 231 of file gru_instructions.h.

Function Documentation

int gru_check_status_proc ( void * cb )

Definition at line 483 of file grukservices.c.

int gru_get_cb_exception_detail	(	void *	cb,
		struct control_block_extended_exc_detail *	excdet
	)

Definition at line 394 of file grukservices.c.

void gru_wait_abort_proc ( void * cb )

Definition at line 516 of file grukservices.c.

int gru_wait_proc ( void * cb )

Definition at line 496 of file grukservices.c.

Data Structures

Macros

Functions

Macro Definition Documentation

Function Documentation