|
| enum | gp_registers {
GP_DST_OFFSET = 0,
GP_SRC_OFFSET,
GP_STRIDE,
GP_WID_HEIGHT,
GP_SRC_COLOR_FG,
GP_SRC_COLOR_BG,
GP_PAT_COLOR_0,
GP_PAT_COLOR_1,
GP_PAT_COLOR_2,
GP_PAT_COLOR_3,
GP_PAT_COLOR_4,
GP_PAT_COLOR_5,
GP_PAT_DATA_0,
GP_PAT_DATA_1,
GP_RASTER_MODE,
GP_VECTOR_MODE,
GP_BLT_MODE,
GP_BLT_STATUS,
GP_HST_SRC,
GP_BASE_OFFSET,
GP_DST_OFFSET = 0,
GP_SRC_OFFSET,
GP_STRIDE,
GP_WID_HEIGHT,
GP_SRC_COLOR_FG,
GP_SRC_COLOR_BG,
GP_PAT_COLOR_0,
GP_PAT_COLOR_1,
GP_PAT_COLOR_2,
GP_PAT_COLOR_3,
GP_PAT_COLOR_4,
GP_PAT_COLOR_5,
GP_PAT_DATA_0,
GP_PAT_DATA_1,
GP_RASTER_MODE,
GP_VECTOR_MODE,
GP_BLT_MODE,
GP_BLT_STATUS,
GP_HST_SRC,
GP_BASE_OFFSET,
GP_CMD_TOP,
GP_CMD_BOT,
GP_CMD_READ,
GP_CMD_WRITE,
GP_CH3_OFFSET,
GP_CH3_MODE_STR,
GP_CH3_WIDHI,
GP_CH3_HSRC,
GP_LUT_INDEX,
GP_LUT_DATA,
GP_INT_CNTRL
} |
| |
| enum | dc_registers {
DC_UNLOCK = 0,
DC_GENERAL_CFG,
DC_DISPLAY_CFG,
DC_RSVD_0,
DC_FB_ST_OFFSET,
DC_CB_ST_OFFSET,
DC_CURS_ST_OFFSET,
DC_ICON_ST_OFFSET,
DC_VID_Y_ST_OFFSET,
DC_VID_U_ST_OFFSET,
DC_VID_V_ST_OFFSET,
DC_RSVD_1,
DC_LINE_SIZE,
DC_GFX_PITCH,
DC_VID_YUV_PITCH,
DC_RSVD_2,
DC_H_ACTIVE_TIMING,
DC_H_BLANK_TIMING,
DC_H_SYNC_TIMING,
DC_RSVD_3,
DC_V_ACTIVE_TIMING,
DC_V_BLANK_TIMING,
DC_V_SYNC_TIMING,
DC_RSVD_4,
DC_CURSOR_X,
DC_CURSOR_Y,
DC_ICON_X,
DC_LINE_CNT,
DC_PAL_ADDRESS,
DC_PAL_DATA,
DC_DFIFO_DIAG,
DC_CFIFO_DIAG,
DC_VID_DS_DELTA,
DC_GLIU0_MEM_OFFSET,
DC_RSVD_5,
DC_DV_ACC,
DC_UNLOCK = 0,
DC_GENERAL_CFG,
DC_DISPLAY_CFG,
DC_ARB_CFG,
DC_FB_ST_OFFSET,
DC_CB_ST_OFFSET,
DC_CURS_ST_OFFSET,
DC_RSVD_0,
DC_VID_Y_ST_OFFSET,
DC_VID_U_ST_OFFSET,
DC_VID_V_ST_OFFSET,
DC_DV_TOP,
DC_LINE_SIZE,
DC_GFX_PITCH,
DC_VID_YUV_PITCH,
DC_RSVD_1,
DC_H_ACTIVE_TIMING,
DC_H_BLANK_TIMING,
DC_H_SYNC_TIMING,
DC_RSVD_2,
DC_V_ACTIVE_TIMING,
DC_V_BLANK_TIMING,
DC_V_SYNC_TIMING,
DC_FB_ACTIVE,
DC_CURSOR_X,
DC_CURSOR_Y,
DC_RSVD_3,
DC_LINE_CNT,
DC_PAL_ADDRESS,
DC_PAL_DATA,
DC_DFIFO_DIAG,
DC_CFIFO_DIAG,
DC_VID_DS_DELTA,
DC_GLIU0_MEM_OFFSET,
DC_DV_CTL,
DC_DV_ACCESS,
DC_GFX_SCALE,
DC_IRQ_FILT_CTL,
DC_FILT_COEFF1,
DC_FILT_COEFF2,
DC_VBI_EVEN_CTL,
DC_VBI_ODD_CTL,
DC_VBI_HOR,
DC_VBI_LN_ODD,
DC_VBI_LN_EVEN,
DC_VBI_PITCH,
DC_CLR_KEY,
DC_CLR_KEY_MASK,
DC_CLR_KEY_X,
DC_CLR_KEY_Y,
DC_IRQ,
DC_RSVD_4,
DC_RSVD_5,
DC_GENLK_CTL,
DC_VID_EVEN_Y_ST_OFFSET,
DC_VID_EVEN_U_ST_OFFSET,
DC_VID_EVEN_V_ST_OFFSET,
DC_V_ACTIVE_EVEN_TIMING,
DC_V_BLANK_EVEN_TIMING,
DC_V_SYNC_EVEN_TIMING
} |
| |
| enum | vp_registers {
VP_VCFG = 0,
VP_DCFG,
VP_VX,
VP_VY,
VP_VS,
VP_VCK,
VP_VCM,
VP_GAR,
VP_GDR,
VP_RSVD_0,
VP_MISC,
VP_CCS,
VP_RSVD_1,
VP_RSVD_2,
VP_RSVD_3,
VP_VDC,
VP_VCO,
VP_CRC,
VP_CRC32,
VP_VDE,
VP_CCK,
VP_CCM,
VP_CC1,
VP_CC2,
VP_A1X,
VP_A1Y,
VP_A1C,
VP_A1T,
VP_A2X,
VP_A2Y,
VP_A2C,
VP_A2T,
VP_A3X,
VP_A3Y,
VP_A3C,
VP_A3T,
VP_VRR,
VP_AWT,
VP_VTM,
VP_VCFG = 0,
VP_DCFG,
VP_VX,
VP_VY,
VP_SCL,
VP_VCK,
VP_VCM,
VP_PAR,
VP_PDR,
VP_SLR,
VP_MISC,
VP_CCS,
VP_VYS,
VP_VXS,
VP_RSVD_0,
VP_VDC,
VP_RSVD_1,
VP_CRC,
VP_CRC32,
VP_VDE,
VP_CCK,
VP_CCM,
VP_CC1,
VP_CC2,
VP_A1X,
VP_A1Y,
VP_A1C,
VP_A1T,
VP_A2X,
VP_A2Y,
VP_A2C,
VP_A2T,
VP_A3X,
VP_A3Y,
VP_A3C,
VP_A3T,
VP_VRR,
VP_AWT,
VP_VTM,
VP_VYE,
VP_A1YE,
VP_A2YE,
VP_A3YE,
VP_VCR = 0x1000
} |
| |
| enum | fp_registers {
FP_PT1 = 0,
FP_PT2,
FP_PM,
FP_DFC,
FP_BLFSR,
FP_RLFSR,
FP_FMI,
FP_FMD,
FP_RSVD_0,
FP_DCA,
FP_DMD,
FP_CRC,
FP_FBB,
FP_PT1 = 0,
FP_PT2,
FP_PM,
FP_DFC,
FP_RSVD_0,
FP_RSVD_1,
FP_RSVD_2,
FP_RSVD_3,
FP_RSVD_4,
FP_DCA,
FP_DMD,
FP_CRC
} |
| |
1.8.2