Linux Kernel
3.7.1
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Macros | |
#define | SERIAL2_OFS 0x2d000 |
#define | SERIAL2_BASE (IO_PHYS + SERIAL2_OFS) |
#define | SERIAL2_VIRT (IO_VIRT + SERIAL2_OFS) |
#define | SERIAL3_OFS 0x2e000 |
#define | SERIAL3_BASE (IO_PHYS + SERIAL3_OFS) |
#define | SERIAL3_VIRT (IO_VIRT + SERIAL3_OFS) |
#define | KBD_VIRT (IO_VIRT + 0x22000) |
#define | KBD_KBCR 0x00 |
#define | KBD_KBSC 0x04 |
#define | KBD_KBTR 0x08 |
#define | KBD_KBVR0 0x0C |
#define | KBD_KBVR1 0x10 |
#define | KBD_KBSR 0x18 |
#define | KBD_KBCR_SCANENABLE (1 << 7) |
#define | KBD_KBCR_NPOWERDOWN (1 << 2) |
#define | KBD_KBCR_CLKSEL_MASK (3) |
#define | KBD_KBCR_CLKSEL_PCLK2 0x0 |
#define | KBD_KBCR_CLKSEL_PCLK128 0x1 |
#define | KBD_KBCR_CLKSEL_PCLK256 0x2 |
#define | KBD_KBCR_CLKSEL_PCLK512 0x3 |
#define | KBD_KBSR_INTR (1 << 0) |
#define | KBD_KBSR_WAKEUP (1 << 1) |
#define | USBD_BASE (IO_VIRT + 0x12000) |
#define | USBD_LENGTH 0x3C |
#define | USBD_GCTRL 0x00 |
#define | USBD_EPCTRL 0x04 |
#define | USBD_INTMASK 0x08 |
#define | USBD_INTSTAT 0x0C |
#define | USBD_PWR 0x10 |
#define | USBD_DMARXTX 0x14 |
#define | USBD_DEVID 0x18 |
#define | USBD_DEVCLASS 0x1C |
#define | USBD_INTCLASS 0x20 |
#define | USBD_SETUP0 0x24 |
#define | USBD_SETUP1 0x28 |
#define | USBD_ENDP0RD 0x2C |
#define | USBD_ENDP0WT 0x30 |
#define | USBD_ENDP1RD 0x34 |
#define | USBD_ENDP2WT 0x38 |
#define | PSDATA 0x00 |
#define | PSSTAT 0x04 |
#define | PSSTAT_TXEMPTY (1<<0) |
#define | PSSTAT_TXBUSY (1<<1) |
#define | PSSTAT_RXFULL (1<<2) |
#define | PSSTAT_RXBUSY (1<<3) |
#define | PSSTAT_CLKIN (1<<4) |
#define | PSSTAT_DATAIN (1<<5) |
#define | PSSTAT_PARITY (1<<6) |
#define | PSCONF 0x08 |
#define | PSCONF_ENABLE (1<<0) |
#define | PSCONF_TXINTEN (1<<2) |
#define | PSCONF_RXINTEN (1<<3) |
#define | PSCONF_FORCECLKLOW (1<<4) |
#define | PSCONF_FORCEDATLOW (1<<5) |
#define | PSCONF_LCE (1<<6) |
#define | PSINTR 0x0C |
#define | PSINTR_TXINT (1<<0) |
#define | PSINTR_RXINT (1<<1) |
#define | PSINTR_PAR (1<<2) |
#define | PSINTR_RXTO (1<<3) |
#define | PSINTR_TXTO (1<<4) |
#define | PSTDLO 0x10 /* clk low before start transmission */ |
#define | PSTPRI 0x14 /* PRI clock */ |
#define | PSTXMT 0x18 /* maximum transmission time */ |
#define | PSTREC 0x20 /* maximum receive time */ |
#define | PSPWDN 0x3c |
#define | ADC_BASE (IO_VIRT + 0x29000) |
#define | ADC_CR 0x00 |
#define | ADC_TSCTRL 0x04 |
#define | ADC_BT_CTRL 0x08 |
#define | ADC_MC_CTRL 0x0C |
#define | ADC_STATUS 0x10 |
#define | ADC_CR_PW_CTRL 0x80 |
#define | ADC_CR_DIRECTC 0x04 |
#define | ADC_CR_CONTIME_NO 0x00 |
#define | ADC_CR_CONTIME_2 0x04 |
#define | ADC_CR_CONTIME_4 0x08 |
#define | ADC_CR_CONTIME_ADE 0x0c |
#define | ADC_CR_LONGCALTIME 0x01 |
#define | ADC_TSCTRL_ENABLE 0x80 |
#define | ADC_TSCTRL_INTR 0x40 |
#define | ADC_TSCTRL_SWBYPSS 0x20 |
#define | ADC_TSCTRL_SWINVT 0x10 |
#define | ADC_TSCTRL_S400 0x03 |
#define | ADC_TSCTRL_S200 0x02 |
#define | ADC_TSCTRL_S100 0x01 |
#define | ADC_TSCTRL_S50 0x00 |
#define | ADC_STATUS_TS_BIT 0x80 |
#define | ADC_STATUS_MBT_BIT 0x40 |
#define | ADC_STATUS_BBT_BIT 0x20 |
#define | ADC_STATUS_MIC_BIT 0x10 |
#define | ADC_TS_X0X1 0x30 |
#define | ADC_TS_X2X3 0x34 |
#define | ADC_TS_Y0Y1 0x38 |
#define | ADC_TS_Y2Y3 0x3c |
#define | ADC_TS_X4X5 0x40 |
#define | ADC_TS_X6X7 0x44 |
#define | ADC_TS_Y4Y5 0x48 |
#define | ADC_TS_Y6Y7 0x50 |
#define | ADC_MB_DATA 0x54 |
#define | ADC_BB_DATA 0x58 |
#define | ADC_SD_DAT0 0x60 |
#define | ADC_SD_DAT1 0x64 |
#define | ADC_SD_DAT2 0x68 |
#define | ADC_SD_DAT3 0x6c |
#define | ADC_SD_DAT4 0x70 |
#define | ADC_SD_DAT5 0x74 |
#define | ADC_SD_DAT6 0x78 |
#define | ADC_SD_DAT7 0x7c |
#define ADC_BASE (IO_VIRT + 0x29000) |
Definition at line 101 of file h7202-regs.h.
#define ADC_BB_DATA 0x58 |
Definition at line 145 of file h7202-regs.h.
#define ADC_BT_CTRL 0x08 |
Definition at line 104 of file h7202-regs.h.
#define ADC_CR 0x00 |
Definition at line 102 of file h7202-regs.h.
#define ADC_CR_CONTIME_2 0x04 |
Definition at line 112 of file h7202-regs.h.
#define ADC_CR_CONTIME_4 0x08 |
Definition at line 113 of file h7202-regs.h.
#define ADC_CR_CONTIME_ADE 0x0c |
Definition at line 114 of file h7202-regs.h.
#define ADC_CR_CONTIME_NO 0x00 |
Definition at line 111 of file h7202-regs.h.
#define ADC_CR_DIRECTC 0x04 |
Definition at line 110 of file h7202-regs.h.
#define ADC_CR_LONGCALTIME 0x01 |
Definition at line 115 of file h7202-regs.h.
#define ADC_CR_PW_CTRL 0x80 |
Definition at line 109 of file h7202-regs.h.
#define ADC_MB_DATA 0x54 |
Definition at line 144 of file h7202-regs.h.
#define ADC_MC_CTRL 0x0C |
Definition at line 105 of file h7202-regs.h.
#define ADC_SD_DAT0 0x60 |
Definition at line 148 of file h7202-regs.h.
#define ADC_SD_DAT1 0x64 |
Definition at line 149 of file h7202-regs.h.
#define ADC_SD_DAT2 0x68 |
Definition at line 150 of file h7202-regs.h.
#define ADC_SD_DAT3 0x6c |
Definition at line 151 of file h7202-regs.h.
#define ADC_SD_DAT4 0x70 |
Definition at line 152 of file h7202-regs.h.
#define ADC_SD_DAT5 0x74 |
Definition at line 153 of file h7202-regs.h.
#define ADC_SD_DAT6 0x78 |
Definition at line 154 of file h7202-regs.h.
#define ADC_SD_DAT7 0x7c |
Definition at line 155 of file h7202-regs.h.
#define ADC_STATUS 0x10 |
Definition at line 106 of file h7202-regs.h.
#define ADC_STATUS_BBT_BIT 0x20 |
Definition at line 130 of file h7202-regs.h.
#define ADC_STATUS_MBT_BIT 0x40 |
Definition at line 129 of file h7202-regs.h.
#define ADC_STATUS_MIC_BIT 0x10 |
Definition at line 131 of file h7202-regs.h.
#define ADC_STATUS_TS_BIT 0x80 |
Definition at line 128 of file h7202-regs.h.
#define ADC_TS_X0X1 0x30 |
Definition at line 134 of file h7202-regs.h.
#define ADC_TS_X2X3 0x34 |
Definition at line 135 of file h7202-regs.h.
#define ADC_TS_X4X5 0x40 |
Definition at line 138 of file h7202-regs.h.
#define ADC_TS_X6X7 0x44 |
Definition at line 139 of file h7202-regs.h.
#define ADC_TS_Y0Y1 0x38 |
Definition at line 136 of file h7202-regs.h.
#define ADC_TS_Y2Y3 0x3c |
Definition at line 137 of file h7202-regs.h.
#define ADC_TS_Y4Y5 0x48 |
Definition at line 140 of file h7202-regs.h.
#define ADC_TS_Y6Y7 0x50 |
Definition at line 141 of file h7202-regs.h.
#define ADC_TSCTRL 0x04 |
Definition at line 103 of file h7202-regs.h.
#define ADC_TSCTRL_ENABLE 0x80 |
Definition at line 118 of file h7202-regs.h.
#define ADC_TSCTRL_INTR 0x40 |
Definition at line 119 of file h7202-regs.h.
#define ADC_TSCTRL_S100 0x01 |
Definition at line 124 of file h7202-regs.h.
#define ADC_TSCTRL_S200 0x02 |
Definition at line 123 of file h7202-regs.h.
#define ADC_TSCTRL_S400 0x03 |
Definition at line 122 of file h7202-regs.h.
#define ADC_TSCTRL_S50 0x00 |
Definition at line 125 of file h7202-regs.h.
#define ADC_TSCTRL_SWBYPSS 0x20 |
Definition at line 120 of file h7202-regs.h.
#define ADC_TSCTRL_SWINVT 0x10 |
Definition at line 121 of file h7202-regs.h.
#define KBD_KBCR 0x00 |
Definition at line 29 of file h7202-regs.h.
#define KBD_KBCR_CLKSEL_MASK (3) |
Definition at line 38 of file h7202-regs.h.
#define KBD_KBCR_CLKSEL_PCLK128 0x1 |
Definition at line 40 of file h7202-regs.h.
#define KBD_KBCR_CLKSEL_PCLK2 0x0 |
Definition at line 39 of file h7202-regs.h.
#define KBD_KBCR_CLKSEL_PCLK256 0x2 |
Definition at line 41 of file h7202-regs.h.
#define KBD_KBCR_CLKSEL_PCLK512 0x3 |
Definition at line 42 of file h7202-regs.h.
#define KBD_KBCR_NPOWERDOWN (1 << 2) |
Definition at line 37 of file h7202-regs.h.
#define KBD_KBCR_SCANENABLE (1 << 7) |
Definition at line 36 of file h7202-regs.h.
#define KBD_KBSC 0x04 |
Definition at line 30 of file h7202-regs.h.
#define KBD_KBSR 0x18 |
Definition at line 34 of file h7202-regs.h.
#define KBD_KBSR_INTR (1 << 0) |
Definition at line 44 of file h7202-regs.h.
#define KBD_KBSR_WAKEUP (1 << 1) |
Definition at line 45 of file h7202-regs.h.
#define KBD_KBTR 0x08 |
Definition at line 31 of file h7202-regs.h.
#define KBD_KBVR0 0x0C |
Definition at line 32 of file h7202-regs.h.
#define KBD_KBVR1 0x10 |
Definition at line 33 of file h7202-regs.h.
#define KBD_VIRT (IO_VIRT + 0x22000) |
Definition at line 28 of file h7202-regs.h.
#define PSCONF 0x08 |
Definition at line 79 of file h7202-regs.h.
#define PSCONF_ENABLE (1<<0) |
Definition at line 80 of file h7202-regs.h.
#define PSCONF_FORCECLKLOW (1<<4) |
Definition at line 83 of file h7202-regs.h.
#define PSCONF_FORCEDATLOW (1<<5) |
Definition at line 84 of file h7202-regs.h.
#define PSCONF_LCE (1<<6) |
Definition at line 85 of file h7202-regs.h.
#define PSCONF_RXINTEN (1<<3) |
Definition at line 82 of file h7202-regs.h.
#define PSCONF_TXINTEN (1<<2) |
Definition at line 81 of file h7202-regs.h.
#define PSDATA 0x00 |
Definition at line 69 of file h7202-regs.h.
#define PSINTR 0x0C |
Definition at line 87 of file h7202-regs.h.
#define PSINTR_PAR (1<<2) |
Definition at line 90 of file h7202-regs.h.
#define PSINTR_RXINT (1<<1) |
Definition at line 89 of file h7202-regs.h.
#define PSINTR_RXTO (1<<3) |
Definition at line 91 of file h7202-regs.h.
#define PSINTR_TXINT (1<<0) |
Definition at line 88 of file h7202-regs.h.
#define PSINTR_TXTO (1<<4) |
Definition at line 92 of file h7202-regs.h.
#define PSPWDN 0x3c |
Definition at line 98 of file h7202-regs.h.
#define PSSTAT 0x04 |
Definition at line 70 of file h7202-regs.h.
#define PSSTAT_CLKIN (1<<4) |
Definition at line 75 of file h7202-regs.h.
#define PSSTAT_DATAIN (1<<5) |
Definition at line 76 of file h7202-regs.h.
#define PSSTAT_PARITY (1<<6) |
Definition at line 77 of file h7202-regs.h.
#define PSSTAT_RXBUSY (1<<3) |
Definition at line 74 of file h7202-regs.h.
#define PSSTAT_RXFULL (1<<2) |
Definition at line 73 of file h7202-regs.h.
#define PSSTAT_TXBUSY (1<<1) |
Definition at line 72 of file h7202-regs.h.
#define PSSTAT_TXEMPTY (1<<0) |
Definition at line 71 of file h7202-regs.h.
#define PSTDLO 0x10 /* clk low before start transmission */ |
Definition at line 94 of file h7202-regs.h.
#define PSTPRI 0x14 /* PRI clock */ |
Definition at line 95 of file h7202-regs.h.
#define PSTREC 0x20 /* maximum receive time */ |
Definition at line 97 of file h7202-regs.h.
#define PSTXMT 0x18 /* maximum transmission time */ |
Definition at line 96 of file h7202-regs.h.
#define SERIAL2_BASE (IO_PHYS + SERIAL2_OFS) |
Definition at line 21 of file h7202-regs.h.
#define SERIAL2_OFS 0x2d000 |
Definition at line 20 of file h7202-regs.h.
#define SERIAL2_VIRT (IO_VIRT + SERIAL2_OFS) |
Definition at line 22 of file h7202-regs.h.
#define SERIAL3_BASE (IO_PHYS + SERIAL3_OFS) |
Definition at line 24 of file h7202-regs.h.
#define SERIAL3_OFS 0x2e000 |
Definition at line 23 of file h7202-regs.h.
#define SERIAL3_VIRT (IO_VIRT + SERIAL3_OFS) |
Definition at line 25 of file h7202-regs.h.
#define USBD_BASE (IO_VIRT + 0x12000) |
Definition at line 49 of file h7202-regs.h.
#define USBD_DEVCLASS 0x1C |
Definition at line 59 of file h7202-regs.h.
#define USBD_DEVID 0x18 |
Definition at line 58 of file h7202-regs.h.
#define USBD_DMARXTX 0x14 |
Definition at line 57 of file h7202-regs.h.
#define USBD_ENDP0RD 0x2C |
Definition at line 63 of file h7202-regs.h.
#define USBD_ENDP0WT 0x30 |
Definition at line 64 of file h7202-regs.h.
#define USBD_ENDP1RD 0x34 |
Definition at line 65 of file h7202-regs.h.
#define USBD_ENDP2WT 0x38 |
Definition at line 66 of file h7202-regs.h.
#define USBD_EPCTRL 0x04 |
Definition at line 53 of file h7202-regs.h.
#define USBD_GCTRL 0x00 |
Definition at line 52 of file h7202-regs.h.
#define USBD_INTCLASS 0x20 |
Definition at line 60 of file h7202-regs.h.
#define USBD_INTMASK 0x08 |
Definition at line 54 of file h7202-regs.h.
#define USBD_INTSTAT 0x0C |
Definition at line 55 of file h7202-regs.h.
#define USBD_LENGTH 0x3C |
Definition at line 50 of file h7202-regs.h.
#define USBD_PWR 0x10 |
Definition at line 56 of file h7202-regs.h.
#define USBD_SETUP0 0x24 |
Definition at line 61 of file h7202-regs.h.
#define USBD_SETUP1 0x28 |
Definition at line 62 of file h7202-regs.h.