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#define HDLC_ERR_CER 0x04 |
#define HDLC_ERR_FAD 0x10 |
#define HDLC_ERR_RER 0x08 |
#define IOM_CTRL_ALAW 0x02 |
#define IOM_CTRL_ENA 0x80 |
#define IOM_CTRL_NOPCM 0x00 |
#define IOM_CTRL_RCV 0x01 |
#define IOM_CTRL_ULAW 0x04 |
#define ISAR_CTRL_STST 0x40 |
#define ISAR_CTRL_SWVER 0x10 |
#define ISAR_HIS_BSTREQ 0x0c |
#define ISAR_HIS_DIAG 0x05 |
#define ISAR_HIS_DKEY 0x02 |
#define ISAR_HIS_DPS1 0x40 |
#define ISAR_HIS_DPS2 0x80 |
#define ISAR_HIS_FIRM 0x1e |
#define ISAR_HIS_IOM2CFG 0x27 |
#define ISAR_HIS_IOM2CTRL 0x2b |
#define ISAR_HIS_IOM2REQ 0x07 |
#define ISAR_HIS_P0CFG 0x3c |
#define ISAR_HIS_P12CFG 0x24 |
#define ISAR_HIS_PSTREQ 0x0e |
#define ISAR_HIS_PUMPCFG 0x26 |
#define ISAR_HIS_PUMPCTRL 0x2a |
#define ISAR_HIS_SARTCFG 0x25 |
#define ISAR_HIS_SDATA 0x20 |
#define ISAR_HIS_STDSP 0x08 |
#define ISAR_HIS_VNR 0x14 |
#define ISAR_IIS_BSTEV 0x28 |
#define ISAR_IIS_BSTRSP 0x2c |
#define ISAR_IIS_DIAG 0x25 |
#define ISAR_IIS_DKEY 0x03 |
#define ISAR_IIS_FIRM 0x1f |
#define ISAR_IIS_GSTEV 0x00 |
#define ISAR_IIS_INVMSG 0x3f |
#define ISAR_IIS_IOM2RSP 0x27 |
#define ISAR_IIS_MSCMSD 0x3f |
#define ISAR_IIS_PSTEV 0x2a |
#define ISAR_IIS_PSTRSP 0x2e |
#define ISAR_IIS_RDATA 0x20 |
#define ISAR_IIS_STDSP 0x09 |
#define ISAR_IIS_VNR 0x15 |
#define ISAR_MSG_HWVER 0x20 |
#define PCTRL_CMD_CONT 0xa2 |
#define PCTRL_CMD_ESC 0xa4 |
#define PCTRL_CMD_FRH 0xa5 |
#define PCTRL_CMD_FRM 0xa6 |
#define PCTRL_CMD_FTH 0xa7 |
#define PCTRL_CMD_FTM 0xa8 |
#define PCTRL_CMD_HALT 0xa9 |
#define PCTRL_CMD_SILOFF 0xab |
#define PCTRL_CMD_SILON 0xac |
#define PCTRL_CMD_TDTMF 0x5a |
#define PCTRL_LOC_REN 0xce |
#define PCTRL_LOC_RET 0xcf |
#define PMOD_DTMF_TRANS 6 |
#define PMOD_HALFDUPLEX 3 |
#define PSEV_10MS_TIMER 0x02 |
#define PSEV_CON_OFF 0x19 |
#define PSEV_CTS_OFF 0x22 |
#define PSEV_DCD_OFF 0x24 |
#define PSEV_DSR_OFF 0x26 |
#define PSEV_FLAGS_DET 0xba |
#define PSEV_GSTN_CLR 0xd4 |
#define PSEV_LINE_RX_B 0xb0 |
#define PSEV_LINE_RX_H 0xb1 |
#define PSEV_LINE_TX_B 0xb2 |
#define PSEV_LINE_TX_H 0xb3 |
#define PSEV_REM_REN 0xcd |
#define PSEV_REM_RET 0xcc |
#define PSEV_RSP_CONN 0xb5 |
#define PSEV_RSP_DISC 0xb7 |
#define PSEV_RSP_FCERR 0xb9 |
#define PSEV_RSP_READY 0xbc |
#define PSEV_RSP_SILDET 0xbe |
#define PSEV_RSP_SILOFF 0xab |
#define PSEV_V24_OFF 0x20 |
#define PV32P4_UT120 0xf1 |
#define PV32P4_UT144 0xf9 |
#define PV32P4_UTB96 0xd1 |
#define PV32P5_UT120 0x0f |
#define PV32P5_UT144 0x0f |
#define PV32P5_UTB96 0x0f |
#define S_P2_BFT_DEF 0x10 |
#define SCTRL_HDMC_BOTH 0x00 |
#define SCTRL_HDMC_DRX 0x40 |
#define SCTRL_HDMC_DTX 0x80 |
#define SET_DPS |
( |
|
x | ) |
((x << 6) & 0xc0) |