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Data Structures | Macros
hd64570.h File Reference

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Data Structures

struct  __packed
 

Macros

#define LPR   0x00 /* Low Power */
 
#define PABR0   0x02 /* Physical Address Boundary 0 */
 
#define PABR1   0x03 /* Physical Address Boundary 1 */
 
#define WCRL   0x04 /* Wait Control L */
 
#define WCRM   0x05 /* Wait Control M */
 
#define WCRH   0x06 /* Wait Control H */
 
#define PCR   0x08 /* DMA Priority Control */
 
#define DMER   0x09 /* DMA Master Enable */
 
#define ISR0   0x10 /* Interrupt Status 0 */
 
#define ISR1   0x11 /* Interrupt Status 1 */
 
#define ISR2   0x12 /* Interrupt Status 2 */
 
#define IER0   0x14 /* Interrupt Enable 0 */
 
#define IER1   0x15 /* Interrupt Enable 1 */
 
#define IER2   0x16 /* Interrupt Enable 2 */
 
#define ITCR   0x18 /* Interrupt Control */
 
#define IVR   0x1A /* Interrupt Vector */
 
#define IMVR   0x1C /* Interrupt Modified Vector */
 
#define MSCI0_OFFSET   0x20
 
#define MSCI1_OFFSET   0x40
 
#define TRBL   0x00 /* TX/RX buffer L */
 
#define TRBH   0x01 /* TX/RX buffer H */
 
#define ST0   0x02 /* Status 0 */
 
#define ST1   0x03 /* Status 1 */
 
#define ST2   0x04 /* Status 2 */
 
#define ST3   0x05 /* Status 3 */
 
#define FST   0x06 /* Frame Status */
 
#define IE0   0x08 /* Interrupt Enable 0 */
 
#define IE1   0x09 /* Interrupt Enable 1 */
 
#define IE2   0x0A /* Interrupt Enable 2 */
 
#define FIE   0x0B /* Frame Interrupt Enable */
 
#define CMD   0x0C /* Command */
 
#define MD0   0x0E /* Mode 0 */
 
#define MD1   0x0F /* Mode 1 */
 
#define MD2   0x10 /* Mode 2 */
 
#define CTL   0x11 /* Control */
 
#define SA0   0x12 /* Sync/Address 0 */
 
#define SA1   0x13 /* Sync/Address 1 */
 
#define IDL   0x14 /* Idle Pattern */
 
#define TMC   0x15 /* Time Constant */
 
#define RXS   0x16 /* RX Clock Source */
 
#define TXS   0x17 /* TX Clock Source */
 
#define TRC0   0x18 /* TX Ready Control 0 */
 
#define TRC1   0x19 /* TX Ready Control 1 */
 
#define RRC   0x1A /* RX Ready Control */
 
#define CST0   0x1C /* Current Status 0 */
 
#define CST1   0x1D /* Current Status 1 */
 
#define TIMER0RX_OFFSET   0x60
 
#define TIMER0TX_OFFSET   0x68
 
#define TIMER1RX_OFFSET   0x70
 
#define TIMER1TX_OFFSET   0x78
 
#define TCNTL   0x00 /* Up-counter L */
 
#define TCNTH   0x01 /* Up-counter H */
 
#define TCONRL   0x02 /* Constant L */
 
#define TCONRH   0x03 /* Constant H */
 
#define TCSR   0x04 /* Control/Status */
 
#define TEPR   0x05 /* Expand Prescale */
 
#define DMAC0RX_OFFSET   0x80
 
#define DMAC0TX_OFFSET   0xA0
 
#define DMAC1RX_OFFSET   0xC0
 
#define DMAC1TX_OFFSET   0xE0
 
#define BARL   0x00 /* Buffer Address L (chained block) */
 
#define BARH   0x01 /* Buffer Address H (chained block) */
 
#define BARB   0x02 /* Buffer Address B (chained block) */
 
#define DARL   0x00 /* RX Destination Addr L (single block) */
 
#define DARH   0x01 /* RX Destination Addr H (single block) */
 
#define DARB   0x02 /* RX Destination Addr B (single block) */
 
#define SARL   0x04 /* TX Source Address L (single block) */
 
#define SARH   0x05 /* TX Source Address H (single block) */
 
#define SARB   0x06 /* TX Source Address B (single block) */
 
#define CPB   0x06 /* Chain Pointer Base (chained block) */
 
#define CDAL   0x08 /* Current Descriptor Addr L (chained block) */
 
#define CDAH   0x09 /* Current Descriptor Addr H (chained block) */
 
#define EDAL   0x0A /* Error Descriptor Addr L (chained block) */
 
#define EDAH   0x0B /* Error Descriptor Addr H (chained block) */
 
#define BFLL   0x0C /* RX Receive Buffer Length L (chained block)*/
 
#define BFLH   0x0D /* RX Receive Buffer Length H (chained block)*/
 
#define BCRL   0x0E /* Byte Count L */
 
#define BCRH   0x0F /* Byte Count H */
 
#define DSR   0x10 /* DMA Status */
 
#define DSR_RX(node)   (DSR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
 
#define DSR_TX(node)   (DSR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
 
#define DMR   0x11 /* DMA Mode */
 
#define DMR_RX(node)   (DMR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
 
#define DMR_TX(node)   (DMR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
 
#define FCT   0x13 /* Frame End Interrupt Counter */
 
#define FCT_RX(node)   (FCT + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
 
#define FCT_TX(node)   (FCT + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
 
#define DIR   0x14 /* DMA Interrupt Enable */
 
#define DIR_RX(node)   (DIR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
 
#define DIR_TX(node)   (DIR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
 
#define DCR   0x15 /* DMA Command */
 
#define DCR_RX(node)   (DCR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
 
#define DCR_TX(node)   (DCR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
 
#define ST_TX_EOM   0x80 /* End of frame */
 
#define ST_TX_EOT   0x01 /* End of transmition */
 
#define ST_RX_EOM   0x80 /* End of frame */
 
#define ST_RX_SHORT   0x40 /* Short frame */
 
#define ST_RX_ABORT   0x20 /* Abort */
 
#define ST_RX_RESBIT   0x10 /* Residual bit */
 
#define ST_RX_OVERRUN   0x08 /* Overrun */
 
#define ST_RX_CRC   0x04 /* CRC */
 
#define ST_ERROR_MASK   0x7C
 
#define DIR_EOTE   0x80 /* Transfer completed */
 
#define DIR_EOME   0x40 /* Frame Transfer Completed (chained-block) */
 
#define DIR_BOFE   0x20 /* Buffer Overflow/Underflow (chained-block)*/
 
#define DIR_COFE   0x10 /* Counter Overflow (chained-block) */
 
#define DSR_EOT   0x80 /* Transfer completed */
 
#define DSR_EOM   0x40 /* Frame Transfer Completed (chained-block) */
 
#define DSR_BOF   0x20 /* Buffer Overflow/Underflow (chained-block)*/
 
#define DSR_COF   0x10 /* Counter Overflow (chained-block) */
 
#define DSR_DE   0x02 /* DMA Enable */
 
#define DSR_DWE   0x01 /* DMA Write Disable */
 
#define DMER_DME   0x80 /* DMA Master Enable */
 
#define CMD_RESET   0x21 /* Reset Channel */
 
#define CMD_TX_ENABLE   0x02 /* Start transmitter */
 
#define CMD_RX_ENABLE   0x12 /* Start receiver */
 
#define MD0_HDLC   0x80 /* Bit-sync HDLC mode */
 
#define MD0_CRC_ENA   0x04 /* Enable CRC code calculation */
 
#define MD0_CRC_CCITT   0x02 /* CCITT CRC instead of CRC-16 */
 
#define MD0_CRC_PR1   0x01 /* Initial all-ones instead of all-zeros */
 
#define MD0_CRC_NONE   0x00
 
#define MD0_CRC_16_0   0x04
 
#define MD0_CRC_16   0x05
 
#define MD0_CRC_ITU_0   0x06
 
#define MD0_CRC_ITU   0x07
 
#define MD2_NRZ   0x00
 
#define MD2_NRZI   0x20
 
#define MD2_MANCHESTER   0x80
 
#define MD2_FM_MARK   0xA0
 
#define MD2_FM_SPACE   0xC0
 
#define MD2_LOOPBACK   0x03 /* Local data Loopback */
 
#define CTL_NORTS   0x01
 
#define CTL_IDLE   0x10 /* Transmit an idle pattern */
 
#define CTL_UDRNC   0x20 /* Idle after CRC or FCS+flag transmition */
 
#define ST0_TXRDY   0x02 /* TX ready */
 
#define ST0_RXRDY   0x01 /* RX ready */
 
#define ST1_UDRN   0x80 /* MSCI TX underrun */
 
#define ST1_CDCD   0x04 /* DCD level changed */
 
#define ST3_CTS   0x08 /* modem input - /CTS */
 
#define ST3_DCD   0x04 /* modem input - /DCD */
 
#define IE0_TXINT   0x80 /* TX INT MSCI interrupt enable */
 
#define IE0_RXINTA   0x40 /* RX INT A MSCI interrupt enable */
 
#define IE1_UDRN   0x80 /* TX underrun MSCI interrupt enable */
 
#define IE1_CDCD   0x04 /* DCD level changed */
 
#define DCR_ABORT   0x01 /* Software abort command */
 
#define DCR_CLEAR_EOF   0x02 /* Clear EOF interrupt */
 
#define CLK_BRG_MASK   0x0F
 
#define CLK_LINE_RX   0x00 /* TX/RX clock line input */
 
#define CLK_LINE_TX   0x00 /* TX/RX line input */
 
#define CLK_BRG_RX   0x40 /* internal baud rate generator */
 
#define CLK_BRG_TX   0x40 /* internal baud rate generator */
 
#define CLK_RXCLK_TX   0x60 /* TX clock from RX clock */
 

Macro Definition Documentation

#define BARB   0x02 /* Buffer Address B (chained block) */

Definition at line 109 of file hd64570.h.

#define BARH   0x01 /* Buffer Address H (chained block) */

Definition at line 108 of file hd64570.h.

#define BARL   0x00 /* Buffer Address L (chained block) */

Definition at line 107 of file hd64570.h.

#define BCRH   0x0F /* Byte Count H */

Definition at line 128 of file hd64570.h.

#define BCRL   0x0E /* Byte Count L */

Definition at line 127 of file hd64570.h.

#define BFLH   0x0D /* RX Receive Buffer Length H (chained block)*/

Definition at line 126 of file hd64570.h.

#define BFLL   0x0C /* RX Receive Buffer Length L (chained block)*/

Definition at line 125 of file hd64570.h.

#define CDAH   0x09 /* Current Descriptor Addr H (chained block) */

Definition at line 122 of file hd64570.h.

#define CDAL   0x08 /* Current Descriptor Addr L (chained block) */

Definition at line 121 of file hd64570.h.

#define CLK_BRG_MASK   0x0F

Definition at line 234 of file hd64570.h.

#define CLK_BRG_RX   0x40 /* internal baud rate generator */

Definition at line 237 of file hd64570.h.

#define CLK_BRG_TX   0x40 /* internal baud rate generator */

Definition at line 238 of file hd64570.h.

#define CLK_LINE_RX   0x00 /* TX/RX clock line input */

Definition at line 235 of file hd64570.h.

#define CLK_LINE_TX   0x00 /* TX/RX line input */

Definition at line 236 of file hd64570.h.

#define CLK_RXCLK_TX   0x60 /* TX clock from RX clock */

Definition at line 239 of file hd64570.h.

#define CMD   0x0C /* Command */

Definition at line 58 of file hd64570.h.

#define CMD_RESET   0x21 /* Reset Channel */

Definition at line 190 of file hd64570.h.

#define CMD_RX_ENABLE   0x12 /* Start receiver */

Definition at line 192 of file hd64570.h.

#define CMD_TX_ENABLE   0x02 /* Start transmitter */

Definition at line 191 of file hd64570.h.

#define CPB   0x06 /* Chain Pointer Base (chained block) */

Definition at line 119 of file hd64570.h.

#define CST0   0x1C /* Current Status 0 */

Definition at line 72 of file hd64570.h.

#define CST1   0x1D /* Current Status 1 */

Definition at line 73 of file hd64570.h.

#define CTL   0x11 /* Control */

Definition at line 62 of file hd64570.h.

#define CTL_IDLE   0x10 /* Transmit an idle pattern */

Definition at line 213 of file hd64570.h.

#define CTL_NORTS   0x01

Definition at line 212 of file hd64570.h.

#define CTL_UDRNC   0x20 /* Idle after CRC or FCS+flag transmition */

Definition at line 214 of file hd64570.h.

#define DARB   0x02 /* RX Destination Addr B (single block) */

Definition at line 113 of file hd64570.h.

#define DARH   0x01 /* RX Destination Addr H (single block) */

Definition at line 112 of file hd64570.h.

#define DARL   0x00 /* RX Destination Addr L (single block) */

Definition at line 111 of file hd64570.h.

#define DCR   0x15 /* DMA Command */

Definition at line 141 of file hd64570.h.

#define DCR_ABORT   0x01 /* Software abort command */

Definition at line 230 of file hd64570.h.

#define DCR_CLEAR_EOF   0x02 /* Clear EOF interrupt */

Definition at line 231 of file hd64570.h.

#define DCR_RX (   node)    (DCR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))

Definition at line 142 of file hd64570.h.

#define DCR_TX (   node)    (DCR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))

Definition at line 143 of file hd64570.h.

#define DIR   0x14 /* DMA Interrupt Enable */

Definition at line 138 of file hd64570.h.

#define DIR_BOFE   0x20 /* Buffer Overflow/Underflow (chained-block)*/

Definition at line 175 of file hd64570.h.

#define DIR_COFE   0x10 /* Counter Overflow (chained-block) */

Definition at line 176 of file hd64570.h.

#define DIR_EOME   0x40 /* Frame Transfer Completed (chained-block) */

Definition at line 174 of file hd64570.h.

#define DIR_EOTE   0x80 /* Transfer completed */

Definition at line 173 of file hd64570.h.

#define DIR_RX (   node)    (DIR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))

Definition at line 139 of file hd64570.h.

#define DIR_TX (   node)    (DIR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))

Definition at line 140 of file hd64570.h.

#define DMAC0RX_OFFSET   0x80

Definition at line 102 of file hd64570.h.

#define DMAC0TX_OFFSET   0xA0

Definition at line 103 of file hd64570.h.

#define DMAC1RX_OFFSET   0xC0

Definition at line 104 of file hd64570.h.

#define DMAC1TX_OFFSET   0xE0

Definition at line 105 of file hd64570.h.

#define DMER   0x09 /* DMA Master Enable */

Definition at line 23 of file hd64570.h.

#define DMER_DME   0x80 /* DMA Master Enable */

Definition at line 187 of file hd64570.h.

#define DMR   0x11 /* DMA Mode */

Definition at line 132 of file hd64570.h.

#define DMR_RX (   node)    (DMR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))

Definition at line 133 of file hd64570.h.

#define DMR_TX (   node)    (DMR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))

Definition at line 134 of file hd64570.h.

#define DSR   0x10 /* DMA Status */

Definition at line 129 of file hd64570.h.

#define DSR_BOF   0x20 /* Buffer Overflow/Underflow (chained-block)*/

Definition at line 181 of file hd64570.h.

#define DSR_COF   0x10 /* Counter Overflow (chained-block) */

Definition at line 182 of file hd64570.h.

#define DSR_DE   0x02 /* DMA Enable */

Definition at line 183 of file hd64570.h.

#define DSR_DWE   0x01 /* DMA Write Disable */

Definition at line 184 of file hd64570.h.

#define DSR_EOM   0x40 /* Frame Transfer Completed (chained-block) */

Definition at line 180 of file hd64570.h.

#define DSR_EOT   0x80 /* Transfer completed */

Definition at line 179 of file hd64570.h.

#define DSR_RX (   node)    (DSR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))

Definition at line 130 of file hd64570.h.

#define DSR_TX (   node)    (DSR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))

Definition at line 131 of file hd64570.h.

#define EDAH   0x0B /* Error Descriptor Addr H (chained block) */

Definition at line 124 of file hd64570.h.

#define EDAL   0x0A /* Error Descriptor Addr L (chained block) */

Definition at line 123 of file hd64570.h.

#define FCT   0x13 /* Frame End Interrupt Counter */

Definition at line 135 of file hd64570.h.

#define FCT_RX (   node)    (FCT + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))

Definition at line 136 of file hd64570.h.

#define FCT_TX (   node)    (FCT + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))

Definition at line 137 of file hd64570.h.

#define FIE   0x0B /* Frame Interrupt Enable */

Definition at line 57 of file hd64570.h.

#define FST   0x06 /* Frame Status */

Definition at line 53 of file hd64570.h.

#define IDL   0x14 /* Idle Pattern */

Definition at line 65 of file hd64570.h.

#define IE0   0x08 /* Interrupt Enable 0 */

Definition at line 54 of file hd64570.h.

#define IE0_RXINTA   0x40 /* RX INT A MSCI interrupt enable */

Definition at line 226 of file hd64570.h.

#define IE0_TXINT   0x80 /* TX INT MSCI interrupt enable */

Definition at line 225 of file hd64570.h.

#define IE1   0x09 /* Interrupt Enable 1 */

Definition at line 55 of file hd64570.h.

#define IE1_CDCD   0x04 /* DCD level changed */

Definition at line 228 of file hd64570.h.

#define IE1_UDRN   0x80 /* TX underrun MSCI interrupt enable */

Definition at line 227 of file hd64570.h.

#define IE2   0x0A /* Interrupt Enable 2 */

Definition at line 56 of file hd64570.h.

#define IER0   0x14 /* Interrupt Enable 0 */

Definition at line 31 of file hd64570.h.

#define IER1   0x15 /* Interrupt Enable 1 */

Definition at line 32 of file hd64570.h.

#define IER2   0x16 /* Interrupt Enable 2 */

Definition at line 33 of file hd64570.h.

#define IMVR   0x1C /* Interrupt Modified Vector */

Definition at line 37 of file hd64570.h.

#define ISR0   0x10 /* Interrupt Status 0 */

Definition at line 27 of file hd64570.h.

#define ISR1   0x11 /* Interrupt Status 1 */

Definition at line 28 of file hd64570.h.

#define ISR2   0x12 /* Interrupt Status 2 */

Definition at line 29 of file hd64570.h.

#define ITCR   0x18 /* Interrupt Control */

Definition at line 35 of file hd64570.h.

#define IVR   0x1A /* Interrupt Vector */

Definition at line 36 of file hd64570.h.

#define LPR   0x00 /* Low Power */

Definition at line 13 of file hd64570.h.

#define MD0   0x0E /* Mode 0 */

Definition at line 59 of file hd64570.h.

#define MD0_CRC_16   0x05

Definition at line 201 of file hd64570.h.

#define MD0_CRC_16_0   0x04

Definition at line 200 of file hd64570.h.

#define MD0_CRC_CCITT   0x02 /* CCITT CRC instead of CRC-16 */

Definition at line 196 of file hd64570.h.

#define MD0_CRC_ENA   0x04 /* Enable CRC code calculation */

Definition at line 195 of file hd64570.h.

#define MD0_CRC_ITU   0x07

Definition at line 203 of file hd64570.h.

#define MD0_CRC_ITU_0   0x06

Definition at line 202 of file hd64570.h.

#define MD0_CRC_NONE   0x00

Definition at line 199 of file hd64570.h.

#define MD0_CRC_PR1   0x01 /* Initial all-ones instead of all-zeros */

Definition at line 197 of file hd64570.h.

#define MD0_HDLC   0x80 /* Bit-sync HDLC mode */

Definition at line 194 of file hd64570.h.

#define MD1   0x0F /* Mode 1 */

Definition at line 60 of file hd64570.h.

#define MD2   0x10 /* Mode 2 */

Definition at line 61 of file hd64570.h.

#define MD2_FM_MARK   0xA0

Definition at line 208 of file hd64570.h.

#define MD2_FM_SPACE   0xC0

Definition at line 209 of file hd64570.h.

#define MD2_LOOPBACK   0x03 /* Local data Loopback */

Definition at line 210 of file hd64570.h.

#define MD2_MANCHESTER   0x80

Definition at line 207 of file hd64570.h.

#define MD2_NRZ   0x00

Definition at line 205 of file hd64570.h.

#define MD2_NRZI   0x20

Definition at line 206 of file hd64570.h.

#define MSCI0_OFFSET   0x20

Definition at line 44 of file hd64570.h.

#define MSCI1_OFFSET   0x40

Definition at line 45 of file hd64570.h.

#define PABR0   0x02 /* Physical Address Boundary 0 */

Definition at line 16 of file hd64570.h.

#define PABR1   0x03 /* Physical Address Boundary 1 */

Definition at line 17 of file hd64570.h.

#define PCR   0x08 /* DMA Priority Control */

Definition at line 22 of file hd64570.h.

#define RRC   0x1A /* RX Ready Control */

Definition at line 71 of file hd64570.h.

#define RXS   0x16 /* RX Clock Source */

Definition at line 67 of file hd64570.h.

#define SA0   0x12 /* Sync/Address 0 */

Definition at line 63 of file hd64570.h.

#define SA1   0x13 /* Sync/Address 1 */

Definition at line 64 of file hd64570.h.

#define SARB   0x06 /* TX Source Address B (single block) */

Definition at line 117 of file hd64570.h.

#define SARH   0x05 /* TX Source Address H (single block) */

Definition at line 116 of file hd64570.h.

#define SARL   0x04 /* TX Source Address L (single block) */

Definition at line 115 of file hd64570.h.

#define ST0   0x02 /* Status 0 */

Definition at line 49 of file hd64570.h.

#define ST0_RXRDY   0x01 /* RX ready */

Definition at line 217 of file hd64570.h.

#define ST0_TXRDY   0x02 /* TX ready */

Definition at line 216 of file hd64570.h.

#define ST1   0x03 /* Status 1 */

Definition at line 50 of file hd64570.h.

#define ST1_CDCD   0x04 /* DCD level changed */

Definition at line 220 of file hd64570.h.

#define ST1_UDRN   0x80 /* MSCI TX underrun */

Definition at line 219 of file hd64570.h.

#define ST2   0x04 /* Status 2 */

Definition at line 51 of file hd64570.h.

#define ST3   0x05 /* Status 3 */

Definition at line 52 of file hd64570.h.

#define ST3_CTS   0x08 /* modem input - /CTS */

Definition at line 222 of file hd64570.h.

#define ST3_DCD   0x04 /* modem input - /DCD */

Definition at line 223 of file hd64570.h.

#define ST_ERROR_MASK   0x7C

Definition at line 171 of file hd64570.h.

#define ST_RX_ABORT   0x20 /* Abort */

Definition at line 166 of file hd64570.h.

#define ST_RX_CRC   0x04 /* CRC */

Definition at line 169 of file hd64570.h.

#define ST_RX_EOM   0x80 /* End of frame */

Definition at line 164 of file hd64570.h.

#define ST_RX_OVERRUN   0x08 /* Overrun */

Definition at line 168 of file hd64570.h.

#define ST_RX_RESBIT   0x10 /* Residual bit */

Definition at line 167 of file hd64570.h.

#define ST_RX_SHORT   0x40 /* Short frame */

Definition at line 165 of file hd64570.h.

#define ST_TX_EOM   0x80 /* End of frame */

Definition at line 161 of file hd64570.h.

#define ST_TX_EOT   0x01 /* End of transmition */

Definition at line 162 of file hd64570.h.

#define TCNTH   0x01 /* Up-counter H */

Definition at line 88 of file hd64570.h.

#define TCNTL   0x00 /* Up-counter L */

Definition at line 87 of file hd64570.h.

#define TCONRH   0x03 /* Constant H */

Definition at line 90 of file hd64570.h.

#define TCONRL   0x02 /* Constant L */

Definition at line 89 of file hd64570.h.

#define TCSR   0x04 /* Control/Status */

Definition at line 91 of file hd64570.h.

#define TEPR   0x05 /* Expand Prescale */

Definition at line 92 of file hd64570.h.

#define TIMER0RX_OFFSET   0x60

Definition at line 82 of file hd64570.h.

#define TIMER0TX_OFFSET   0x68

Definition at line 83 of file hd64570.h.

#define TIMER1RX_OFFSET   0x70

Definition at line 84 of file hd64570.h.

#define TIMER1TX_OFFSET   0x78

Definition at line 85 of file hd64570.h.

#define TMC   0x15 /* Time Constant */

Definition at line 66 of file hd64570.h.

#define TRBH   0x01 /* TX/RX buffer H */

Definition at line 48 of file hd64570.h.

#define TRBL   0x00 /* TX/RX buffer L */

Definition at line 47 of file hd64570.h.

#define TRC0   0x18 /* TX Ready Control 0 */

Definition at line 69 of file hd64570.h.

#define TRC1   0x19 /* TX Ready Control 1 */

Definition at line 70 of file hd64570.h.

#define TXS   0x17 /* TX Clock Source */

Definition at line 68 of file hd64570.h.

#define WCRH   0x06 /* Wait Control H */

Definition at line 20 of file hd64570.h.

#define WCRL   0x04 /* Wait Control L */

Definition at line 18 of file hd64570.h.

#define WCRM   0x05 /* Wait Control M */

Definition at line 19 of file hd64570.h.