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hda_codec.h
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1 /*
2  * Universal Interface for Intel High Definition Audio Codec
3  *
4  * Copyright (c) 2004 Takashi Iwai <[email protected]>
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License as published by the Free
8  * Software Foundation; either version 2 of the License, or (at your option)
9  * any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program; if not, write to the Free Software Foundation, Inc., 59
18  * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20 
21 #ifndef __SOUND_HDA_CODEC_H
22 #define __SOUND_HDA_CODEC_H
23 
24 #include <sound/info.h>
25 #include <sound/control.h>
26 #include <sound/pcm.h>
27 #include <sound/hwdep.h>
28 
29 /*
30  * nodes
31  */
32 #define AC_NODE_ROOT 0x00
33 
34 /*
35  * function group types
36  */
37 enum {
40 };
41 
42 /*
43  * widget types
44  */
45 enum {
46  AC_WID_AUD_OUT, /* Audio Out */
47  AC_WID_AUD_IN, /* Audio In */
48  AC_WID_AUD_MIX, /* Audio Mixer */
49  AC_WID_AUD_SEL, /* Audio Selector */
50  AC_WID_PIN, /* Pin Complex */
51  AC_WID_POWER, /* Power */
52  AC_WID_VOL_KNB, /* Volume Knob */
53  AC_WID_BEEP, /* Beep Generator */
54  AC_WID_VENDOR = 0x0f /* Vendor specific */
55 };
56 
57 /*
58  * GET verbs
59  */
60 #define AC_VERB_GET_STREAM_FORMAT 0x0a00
61 #define AC_VERB_GET_AMP_GAIN_MUTE 0x0b00
62 #define AC_VERB_GET_PROC_COEF 0x0c00
63 #define AC_VERB_GET_COEF_INDEX 0x0d00
64 #define AC_VERB_PARAMETERS 0x0f00
65 #define AC_VERB_GET_CONNECT_SEL 0x0f01
66 #define AC_VERB_GET_CONNECT_LIST 0x0f02
67 #define AC_VERB_GET_PROC_STATE 0x0f03
68 #define AC_VERB_GET_SDI_SELECT 0x0f04
69 #define AC_VERB_GET_POWER_STATE 0x0f05
70 #define AC_VERB_GET_CONV 0x0f06
71 #define AC_VERB_GET_PIN_WIDGET_CONTROL 0x0f07
72 #define AC_VERB_GET_UNSOLICITED_RESPONSE 0x0f08
73 #define AC_VERB_GET_PIN_SENSE 0x0f09
74 #define AC_VERB_GET_BEEP_CONTROL 0x0f0a
75 #define AC_VERB_GET_EAPD_BTLENABLE 0x0f0c
76 #define AC_VERB_GET_DIGI_CONVERT_1 0x0f0d
77 #define AC_VERB_GET_DIGI_CONVERT_2 0x0f0e /* unused */
78 #define AC_VERB_GET_VOLUME_KNOB_CONTROL 0x0f0f
79 /* f10-f1a: GPIO */
80 #define AC_VERB_GET_GPIO_DATA 0x0f15
81 #define AC_VERB_GET_GPIO_MASK 0x0f16
82 #define AC_VERB_GET_GPIO_DIRECTION 0x0f17
83 #define AC_VERB_GET_GPIO_WAKE_MASK 0x0f18
84 #define AC_VERB_GET_GPIO_UNSOLICITED_RSP_MASK 0x0f19
85 #define AC_VERB_GET_GPIO_STICKY_MASK 0x0f1a
86 #define AC_VERB_GET_CONFIG_DEFAULT 0x0f1c
87 /* f20: AFG/MFG */
88 #define AC_VERB_GET_SUBSYSTEM_ID 0x0f20
89 #define AC_VERB_GET_CVT_CHAN_COUNT 0x0f2d
90 #define AC_VERB_GET_HDMI_DIP_SIZE 0x0f2e
91 #define AC_VERB_GET_HDMI_ELDD 0x0f2f
92 #define AC_VERB_GET_HDMI_DIP_INDEX 0x0f30
93 #define AC_VERB_GET_HDMI_DIP_DATA 0x0f31
94 #define AC_VERB_GET_HDMI_DIP_XMIT 0x0f32
95 #define AC_VERB_GET_HDMI_CP_CTRL 0x0f33
96 #define AC_VERB_GET_HDMI_CHAN_SLOT 0x0f34
97 
98 /*
99  * SET verbs
100  */
101 #define AC_VERB_SET_STREAM_FORMAT 0x200
102 #define AC_VERB_SET_AMP_GAIN_MUTE 0x300
103 #define AC_VERB_SET_PROC_COEF 0x400
104 #define AC_VERB_SET_COEF_INDEX 0x500
105 #define AC_VERB_SET_CONNECT_SEL 0x701
106 #define AC_VERB_SET_PROC_STATE 0x703
107 #define AC_VERB_SET_SDI_SELECT 0x704
108 #define AC_VERB_SET_POWER_STATE 0x705
109 #define AC_VERB_SET_CHANNEL_STREAMID 0x706
110 #define AC_VERB_SET_PIN_WIDGET_CONTROL 0x707
111 #define AC_VERB_SET_UNSOLICITED_ENABLE 0x708
112 #define AC_VERB_SET_PIN_SENSE 0x709
113 #define AC_VERB_SET_BEEP_CONTROL 0x70a
114 #define AC_VERB_SET_EAPD_BTLENABLE 0x70c
115 #define AC_VERB_SET_DIGI_CONVERT_1 0x70d
116 #define AC_VERB_SET_DIGI_CONVERT_2 0x70e
117 #define AC_VERB_SET_VOLUME_KNOB_CONTROL 0x70f
118 #define AC_VERB_SET_GPIO_DATA 0x715
119 #define AC_VERB_SET_GPIO_MASK 0x716
120 #define AC_VERB_SET_GPIO_DIRECTION 0x717
121 #define AC_VERB_SET_GPIO_WAKE_MASK 0x718
122 #define AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK 0x719
123 #define AC_VERB_SET_GPIO_STICKY_MASK 0x71a
124 #define AC_VERB_SET_CONFIG_DEFAULT_BYTES_0 0x71c
125 #define AC_VERB_SET_CONFIG_DEFAULT_BYTES_1 0x71d
126 #define AC_VERB_SET_CONFIG_DEFAULT_BYTES_2 0x71e
127 #define AC_VERB_SET_CONFIG_DEFAULT_BYTES_3 0x71f
128 #define AC_VERB_SET_EAPD 0x788
129 #define AC_VERB_SET_CODEC_RESET 0x7ff
130 #define AC_VERB_SET_CVT_CHAN_COUNT 0x72d
131 #define AC_VERB_SET_HDMI_DIP_INDEX 0x730
132 #define AC_VERB_SET_HDMI_DIP_DATA 0x731
133 #define AC_VERB_SET_HDMI_DIP_XMIT 0x732
134 #define AC_VERB_SET_HDMI_CP_CTRL 0x733
135 #define AC_VERB_SET_HDMI_CHAN_SLOT 0x734
136 
137 /*
138  * Parameter IDs
139  */
140 #define AC_PAR_VENDOR_ID 0x00
141 #define AC_PAR_SUBSYSTEM_ID 0x01
142 #define AC_PAR_REV_ID 0x02
143 #define AC_PAR_NODE_COUNT 0x04
144 #define AC_PAR_FUNCTION_TYPE 0x05
145 #define AC_PAR_AUDIO_FG_CAP 0x08
146 #define AC_PAR_AUDIO_WIDGET_CAP 0x09
147 #define AC_PAR_PCM 0x0a
148 #define AC_PAR_STREAM 0x0b
149 #define AC_PAR_PIN_CAP 0x0c
150 #define AC_PAR_AMP_IN_CAP 0x0d
151 #define AC_PAR_CONNLIST_LEN 0x0e
152 #define AC_PAR_POWER_STATE 0x0f
153 #define AC_PAR_PROC_CAP 0x10
154 #define AC_PAR_GPIO_CAP 0x11
155 #define AC_PAR_AMP_OUT_CAP 0x12
156 #define AC_PAR_VOL_KNB_CAP 0x13
157 #define AC_PAR_HDMI_LPCM_CAP 0x20
158 
159 /*
160  * AC_VERB_PARAMETERS results (32bit)
161  */
162 
163 /* Function Group Type */
164 #define AC_FGT_TYPE (0xff<<0)
165 #define AC_FGT_TYPE_SHIFT 0
166 #define AC_FGT_UNSOL_CAP (1<<8)
167 
168 /* Audio Function Group Capabilities */
169 #define AC_AFG_OUT_DELAY (0xf<<0)
170 #define AC_AFG_IN_DELAY (0xf<<8)
171 #define AC_AFG_BEEP_GEN (1<<16)
172 
173 /* Audio Widget Capabilities */
174 #define AC_WCAP_STEREO (1<<0) /* stereo I/O */
175 #define AC_WCAP_IN_AMP (1<<1) /* AMP-in present */
176 #define AC_WCAP_OUT_AMP (1<<2) /* AMP-out present */
177 #define AC_WCAP_AMP_OVRD (1<<3) /* AMP-parameter override */
178 #define AC_WCAP_FORMAT_OVRD (1<<4) /* format override */
179 #define AC_WCAP_STRIPE (1<<5) /* stripe */
180 #define AC_WCAP_PROC_WID (1<<6) /* Proc Widget */
181 #define AC_WCAP_UNSOL_CAP (1<<7) /* Unsol capable */
182 #define AC_WCAP_CONN_LIST (1<<8) /* connection list */
183 #define AC_WCAP_DIGITAL (1<<9) /* digital I/O */
184 #define AC_WCAP_POWER (1<<10) /* power control */
185 #define AC_WCAP_LR_SWAP (1<<11) /* L/R swap */
186 #define AC_WCAP_CP_CAPS (1<<12) /* content protection */
187 #define AC_WCAP_CHAN_CNT_EXT (7<<13) /* channel count ext */
188 #define AC_WCAP_DELAY (0xf<<16)
189 #define AC_WCAP_DELAY_SHIFT 16
190 #define AC_WCAP_TYPE (0xf<<20)
191 #define AC_WCAP_TYPE_SHIFT 20
192 
193 /* supported PCM rates and bits */
194 #define AC_SUPPCM_RATES (0xfff << 0)
195 #define AC_SUPPCM_BITS_8 (1<<16)
196 #define AC_SUPPCM_BITS_16 (1<<17)
197 #define AC_SUPPCM_BITS_20 (1<<18)
198 #define AC_SUPPCM_BITS_24 (1<<19)
199 #define AC_SUPPCM_BITS_32 (1<<20)
200 
201 /* supported PCM stream format */
202 #define AC_SUPFMT_PCM (1<<0)
203 #define AC_SUPFMT_FLOAT32 (1<<1)
204 #define AC_SUPFMT_AC3 (1<<2)
205 
206 /* GP I/O count */
207 #define AC_GPIO_IO_COUNT (0xff<<0)
208 #define AC_GPIO_O_COUNT (0xff<<8)
209 #define AC_GPIO_O_COUNT_SHIFT 8
210 #define AC_GPIO_I_COUNT (0xff<<16)
211 #define AC_GPIO_I_COUNT_SHIFT 16
212 #define AC_GPIO_UNSOLICITED (1<<30)
213 #define AC_GPIO_WAKE (1<<31)
214 
215 /* Converter stream, channel */
216 #define AC_CONV_CHANNEL (0xf<<0)
217 #define AC_CONV_STREAM (0xf<<4)
218 #define AC_CONV_STREAM_SHIFT 4
219 
220 /* Input converter SDI select */
221 #define AC_SDI_SELECT (0xf<<0)
222 
223 /* stream format id */
224 #define AC_FMT_CHAN_SHIFT 0
225 #define AC_FMT_CHAN_MASK (0x0f << 0)
226 #define AC_FMT_BITS_SHIFT 4
227 #define AC_FMT_BITS_MASK (7 << 4)
228 #define AC_FMT_BITS_8 (0 << 4)
229 #define AC_FMT_BITS_16 (1 << 4)
230 #define AC_FMT_BITS_20 (2 << 4)
231 #define AC_FMT_BITS_24 (3 << 4)
232 #define AC_FMT_BITS_32 (4 << 4)
233 #define AC_FMT_DIV_SHIFT 8
234 #define AC_FMT_DIV_MASK (7 << 8)
235 #define AC_FMT_MULT_SHIFT 11
236 #define AC_FMT_MULT_MASK (7 << 11)
237 #define AC_FMT_BASE_SHIFT 14
238 #define AC_FMT_BASE_48K (0 << 14)
239 #define AC_FMT_BASE_44K (1 << 14)
240 #define AC_FMT_TYPE_SHIFT 15
241 #define AC_FMT_TYPE_PCM (0 << 15)
242 #define AC_FMT_TYPE_NON_PCM (1 << 15)
243 
244 /* Unsolicited response control */
245 #define AC_UNSOL_TAG (0x3f<<0)
246 #define AC_UNSOL_ENABLED (1<<7)
247 #define AC_USRSP_EN AC_UNSOL_ENABLED
248 
249 /* Unsolicited responses */
250 #define AC_UNSOL_RES_TAG (0x3f<<26)
251 #define AC_UNSOL_RES_TAG_SHIFT 26
252 #define AC_UNSOL_RES_SUBTAG (0x1f<<21)
253 #define AC_UNSOL_RES_SUBTAG_SHIFT 21
254 #define AC_UNSOL_RES_ELDV (1<<1) /* ELD Data valid (for HDMI) */
255 #define AC_UNSOL_RES_PD (1<<0) /* pinsense detect */
256 #define AC_UNSOL_RES_CP_STATE (1<<1) /* content protection */
257 #define AC_UNSOL_RES_CP_READY (1<<0) /* content protection */
258 
259 /* Pin widget capabilies */
260 #define AC_PINCAP_IMP_SENSE (1<<0) /* impedance sense capable */
261 #define AC_PINCAP_TRIG_REQ (1<<1) /* trigger required */
262 #define AC_PINCAP_PRES_DETECT (1<<2) /* presence detect capable */
263 #define AC_PINCAP_HP_DRV (1<<3) /* headphone drive capable */
264 #define AC_PINCAP_OUT (1<<4) /* output capable */
265 #define AC_PINCAP_IN (1<<5) /* input capable */
266 #define AC_PINCAP_BALANCE (1<<6) /* balanced I/O capable */
267 /* Note: This LR_SWAP pincap is defined in the Realtek ALC883 specification,
268  * but is marked reserved in the Intel HDA specification.
269  */
270 #define AC_PINCAP_LR_SWAP (1<<7) /* L/R swap */
271 /* Note: The same bit as LR_SWAP is newly defined as HDMI capability
272  * in HD-audio specification
273  */
274 #define AC_PINCAP_HDMI (1<<7) /* HDMI pin */
275 #define AC_PINCAP_DP (1<<24) /* DisplayPort pin, can
276  * coexist with AC_PINCAP_HDMI
277  */
278 #define AC_PINCAP_VREF (0x37<<8)
279 #define AC_PINCAP_VREF_SHIFT 8
280 #define AC_PINCAP_EAPD (1<<16) /* EAPD capable */
281 #define AC_PINCAP_HBR (1<<27) /* High Bit Rate */
282 /* Vref status (used in pin cap) */
283 #define AC_PINCAP_VREF_HIZ (1<<0) /* Hi-Z */
284 #define AC_PINCAP_VREF_50 (1<<1) /* 50% */
285 #define AC_PINCAP_VREF_GRD (1<<2) /* ground */
286 #define AC_PINCAP_VREF_80 (1<<4) /* 80% */
287 #define AC_PINCAP_VREF_100 (1<<5) /* 100% */
289 /* Amplifier capabilities */
290 #define AC_AMPCAP_OFFSET (0x7f<<0) /* 0dB offset */
291 #define AC_AMPCAP_OFFSET_SHIFT 0
292 #define AC_AMPCAP_NUM_STEPS (0x7f<<8) /* number of steps */
293 #define AC_AMPCAP_NUM_STEPS_SHIFT 8
294 #define AC_AMPCAP_STEP_SIZE (0x7f<<16) /* step size 0-32dB
295  * in 0.25dB
296  */
297 #define AC_AMPCAP_STEP_SIZE_SHIFT 16
298 #define AC_AMPCAP_MUTE (1<<31) /* mute capable */
299 #define AC_AMPCAP_MUTE_SHIFT 31
300 
301 /* driver-specific amp-caps: using bits 24-30 */
302 #define AC_AMPCAP_MIN_MUTE (1 << 30) /* min-volume = mute */
303 
304 /* Connection list */
305 #define AC_CLIST_LENGTH (0x7f<<0)
306 #define AC_CLIST_LONG (1<<7)
308 /* Supported power status */
309 #define AC_PWRST_D0SUP (1<<0)
310 #define AC_PWRST_D1SUP (1<<1)
311 #define AC_PWRST_D2SUP (1<<2)
312 #define AC_PWRST_D3SUP (1<<3)
313 #define AC_PWRST_D3COLDSUP (1<<4)
314 #define AC_PWRST_S3D3COLDSUP (1<<29)
315 #define AC_PWRST_CLKSTOP (1<<30)
316 #define AC_PWRST_EPSS (1U<<31)
318 /* Power state values */
319 #define AC_PWRST_SETTING (0xf<<0)
320 #define AC_PWRST_ACTUAL (0xf<<4)
321 #define AC_PWRST_ACTUAL_SHIFT 4
322 #define AC_PWRST_D0 0x00
323 #define AC_PWRST_D1 0x01
324 #define AC_PWRST_D2 0x02
325 #define AC_PWRST_D3 0x03
326 #define AC_PWRST_ERROR (1<<8)
327 #define AC_PWRST_CLK_STOP_OK (1<<9)
328 #define AC_PWRST_SETTING_RESET (1<<10)
330 /* Processing capabilies */
331 #define AC_PCAP_BENIGN (1<<0)
332 #define AC_PCAP_NUM_COEF (0xff<<8)
333 #define AC_PCAP_NUM_COEF_SHIFT 8
334 
335 /* Volume knobs capabilities */
336 #define AC_KNBCAP_NUM_STEPS (0x7f<<0)
337 #define AC_KNBCAP_DELTA (1<<7)
339 /* HDMI LPCM capabilities */
340 #define AC_LPCMCAP_48K_CP_CHNS (0x0f<<0) /* max channels w/ CP-on */
341 #define AC_LPCMCAP_48K_NO_CHNS (0x0f<<4) /* max channels w/o CP-on */
342 #define AC_LPCMCAP_48K_20BIT (1<<8) /* 20b bitrate supported */
343 #define AC_LPCMCAP_48K_24BIT (1<<9) /* 24b bitrate supported */
344 #define AC_LPCMCAP_96K_CP_CHNS (0x0f<<10) /* max channels w/ CP-on */
345 #define AC_LPCMCAP_96K_NO_CHNS (0x0f<<14) /* max channels w/o CP-on */
346 #define AC_LPCMCAP_96K_20BIT (1<<18) /* 20b bitrate supported */
347 #define AC_LPCMCAP_96K_24BIT (1<<19) /* 24b bitrate supported */
348 #define AC_LPCMCAP_192K_CP_CHNS (0x0f<<20) /* max channels w/ CP-on */
349 #define AC_LPCMCAP_192K_NO_CHNS (0x0f<<24) /* max channels w/o CP-on */
350 #define AC_LPCMCAP_192K_20BIT (1<<28) /* 20b bitrate supported */
351 #define AC_LPCMCAP_192K_24BIT (1<<29) /* 24b bitrate supported */
352 #define AC_LPCMCAP_44K (1<<30) /* 44.1kHz support */
353 #define AC_LPCMCAP_44K_MS (1<<31) /* 44.1kHz-multiplies support */
354 
355 /*
356  * Control Parameters
357  */
359 /* Amp gain/mute */
360 #define AC_AMP_MUTE (1<<7)
361 #define AC_AMP_GAIN (0x7f)
362 #define AC_AMP_GET_INDEX (0xf<<0)
364 #define AC_AMP_GET_LEFT (1<<13)
365 #define AC_AMP_GET_RIGHT (0<<13)
366 #define AC_AMP_GET_OUTPUT (1<<15)
367 #define AC_AMP_GET_INPUT (0<<15)
369 #define AC_AMP_SET_INDEX (0xf<<8)
370 #define AC_AMP_SET_INDEX_SHIFT 8
371 #define AC_AMP_SET_RIGHT (1<<12)
372 #define AC_AMP_SET_LEFT (1<<13)
373 #define AC_AMP_SET_INPUT (1<<14)
374 #define AC_AMP_SET_OUTPUT (1<<15)
376 /* DIGITAL1 bits */
377 #define AC_DIG1_ENABLE (1<<0)
378 #define AC_DIG1_V (1<<1)
379 #define AC_DIG1_VCFG (1<<2)
380 #define AC_DIG1_EMPHASIS (1<<3)
381 #define AC_DIG1_COPYRIGHT (1<<4)
382 #define AC_DIG1_NONAUDIO (1<<5)
383 #define AC_DIG1_PROFESSIONAL (1<<6)
384 #define AC_DIG1_LEVEL (1<<7)
385 
386 /* DIGITAL2 bits */
387 #define AC_DIG2_CC (0x7f<<0)
388 
389 /* DIGITAL3 bits */
390 #define AC_DIG3_ICT (0xf<<0)
391 #define AC_DIG3_KAE (1<<7)
393 /* Pin widget control - 8bit */
394 #define AC_PINCTL_EPT (0x3<<0)
395 #define AC_PINCTL_EPT_NATIVE 0
396 #define AC_PINCTL_EPT_HBR 3
397 #define AC_PINCTL_VREFEN (0x7<<0)
398 #define AC_PINCTL_VREF_HIZ 0 /* Hi-Z */
399 #define AC_PINCTL_VREF_50 1 /* 50% */
400 #define AC_PINCTL_VREF_GRD 2 /* ground */
401 #define AC_PINCTL_VREF_80 4 /* 80% */
402 #define AC_PINCTL_VREF_100 5 /* 100% */
403 #define AC_PINCTL_IN_EN (1<<5)
404 #define AC_PINCTL_OUT_EN (1<<6)
405 #define AC_PINCTL_HP_EN (1<<7)
407 /* Pin sense - 32bit */
408 #define AC_PINSENSE_IMPEDANCE_MASK (0x7fffffff)
409 #define AC_PINSENSE_PRESENCE (1<<31)
410 #define AC_PINSENSE_ELDV (1<<30) /* ELD valid (HDMI) */
412 /* EAPD/BTL enable - 32bit */
413 #define AC_EAPDBTL_BALANCED (1<<0)
414 #define AC_EAPDBTL_EAPD (1<<1)
415 #define AC_EAPDBTL_LR_SWAP (1<<2)
416 
417 /* HDMI ELD data */
418 #define AC_ELDD_ELD_VALID (1<<31)
419 #define AC_ELDD_ELD_DATA 0xff
420 
421 /* HDMI DIP size */
422 #define AC_DIPSIZE_ELD_BUF (1<<3) /* ELD buf size of packet size */
423 #define AC_DIPSIZE_PACK_IDX (0x07<<0) /* packet index */
424 
425 /* HDMI DIP index */
426 #define AC_DIPIDX_PACK_IDX (0x07<<5) /* packet idnex */
427 #define AC_DIPIDX_BYTE_IDX (0x1f<<0) /* byte index */
429 /* HDMI DIP xmit (transmit) control */
430 #define AC_DIPXMIT_MASK (0x3<<6)
431 #define AC_DIPXMIT_DISABLE (0x0<<6) /* disable xmit */
432 #define AC_DIPXMIT_ONCE (0x2<<6) /* xmit once then disable */
433 #define AC_DIPXMIT_BEST (0x3<<6) /* best effort */
435 /* HDMI content protection (CP) control */
436 #define AC_CPCTRL_CES (1<<9) /* current encryption state */
437 #define AC_CPCTRL_READY (1<<8) /* ready bit */
438 #define AC_CPCTRL_SUBTAG (0x1f<<3) /* subtag for unsol-resp */
439 #define AC_CPCTRL_STATE (3<<0) /* current CP request state */
440 
441 /* Converter channel <-> HDMI slot mapping */
442 #define AC_CVTMAP_HDMI_SLOT (0xf<<0) /* HDMI slot number */
443 #define AC_CVTMAP_CHAN (0xf<<4) /* converter channel number */
445 /* configuration default - 32bit */
446 #define AC_DEFCFG_SEQUENCE (0xf<<0)
447 #define AC_DEFCFG_DEF_ASSOC (0xf<<4)
448 #define AC_DEFCFG_ASSOC_SHIFT 4
449 #define AC_DEFCFG_MISC (0xf<<8)
450 #define AC_DEFCFG_MISC_SHIFT 8
451 #define AC_DEFCFG_MISC_NO_PRESENCE (1<<0)
452 #define AC_DEFCFG_COLOR (0xf<<12)
453 #define AC_DEFCFG_COLOR_SHIFT 12
454 #define AC_DEFCFG_CONN_TYPE (0xf<<16)
455 #define AC_DEFCFG_CONN_TYPE_SHIFT 16
456 #define AC_DEFCFG_DEVICE (0xf<<20)
457 #define AC_DEFCFG_DEVICE_SHIFT 20
458 #define AC_DEFCFG_LOCATION (0x3f<<24)
459 #define AC_DEFCFG_LOCATION_SHIFT 24
460 #define AC_DEFCFG_PORT_CONN (0x3<<30)
461 #define AC_DEFCFG_PORT_CONN_SHIFT 30
463 /* device device types (0x0-0xf) */
464 enum {
479  AC_JACK_OTHER = 0xf,
480 };
482 /* jack connection types (0x0-0xf) */
483 enum {
496  AC_JACK_CONN_OTHER = 0xf,
497 };
499 /* jack colors (0x0-0xf) */
500 enum {
511  AC_JACK_COLOR_WHITE = 0xe,
513 };
515 /* Jack location (0x0-0x3f) */
516 /* common case */
517 enum {
525 };
526 /* bits 4-5 */
527 enum {
528  AC_JACK_LOC_EXTERNAL = 0x00,
529  AC_JACK_LOC_INTERNAL = 0x10,
530  AC_JACK_LOC_SEPARATE = 0x20,
532 };
533 enum {
534  /* external on primary chasis */
537  /* internal */
541  /* others */
542  AC_JACK_LOC_MOBILE_IN = 0x37,
544 };
546 /* Port connectivity (0-3) */
547 enum {
552 };
553 
554 /* max. connections to a widget */
555 #define HDA_MAX_CONNECTIONS 32
556 
557 /* max. codec address */
558 #define HDA_MAX_CODEC_ADDRESS 0x0f
560 /*
561  * generic arrays
562  */
563 struct snd_array {
564  unsigned int used;
565  unsigned int alloced;
566  unsigned int elem_size;
567  unsigned int alloc_align;
568  void *list;
569 };
570 
571 void *snd_array_new(struct snd_array *array);
572 void snd_array_free(struct snd_array *array);
573 static inline void snd_array_init(struct snd_array *array, unsigned int size,
574  unsigned int align)
575 {
576  array->elem_size = size;
577  array->alloc_align = align;
578 }
579 
580 static inline void *snd_array_elem(struct snd_array *array, unsigned int idx)
581 {
582  return array->list + idx * array->elem_size;
583 }
584 
585 static inline unsigned int snd_array_index(struct snd_array *array, void *ptr)
586 {
587  return (unsigned long)(ptr - array->list) / array->elem_size;
588 }
589 
590 /*
591  * Structures
592  */
593 
594 struct hda_bus;
595 struct hda_beep;
596 struct hda_codec;
597 struct hda_pcm;
598 struct hda_pcm_stream;
599 struct hda_bus_unsolicited;
600 
601 /* NID type */
602 typedef u16 hda_nid_t;
604 /* bus operators */
605 struct hda_bus_ops {
606  /* send a single command */
607  int (*command)(struct hda_bus *bus, unsigned int cmd);
608  /* get a response from the last command */
609  unsigned int (*get_response)(struct hda_bus *bus, unsigned int addr);
610  /* free the private data */
611  void (*private_free)(struct hda_bus *);
612  /* attach a PCM stream */
613  int (*attach_pcm)(struct hda_bus *bus, struct hda_codec *codec,
614  struct hda_pcm *pcm);
615  /* reset bus for retry verb */
616  void (*bus_reset)(struct hda_bus *bus);
617 #ifdef CONFIG_PM
618  /* notify power-up/down from codec to controller */
619  void (*pm_notify)(struct hda_bus *bus, bool power_up);
620 #endif
621 };
623 /* template to pass to the bus constructor */
626  struct pci_dev *pci;
627  const char *modelname;
628  int *power_save;
629  struct hda_bus_ops ops;
630 };
631 
632 /*
633  * codec bus
634  *
635  * each controller needs to creata a hda_bus to assign the accessor.
636  * A hda_bus contains several codecs in the list codec_list.
637  */
638 struct hda_bus {
639  struct snd_card *card;
641  /* copied from template */
643  struct pci_dev *pci;
644  const char *modelname;
646  struct hda_bus_ops ops;
648  /* codec linked list */
650  /* link caddr -> codec */
652 
653  struct mutex cmd_mutex;
656  /* unsolicited event queue */
657  struct hda_bus_unsolicited *unsol;
658  char workq_name[16];
659  struct workqueue_struct *workq; /* common workqueue for codecs */
660 
661  /* assigned PCMs */
664  /* misc op flags */
665  unsigned int needs_damn_long_delay :1;
666  unsigned int allow_bus_reset:1; /* allow bus reset at fatal error */
667  unsigned int sync_write:1; /* sync after verb write */
668  /* status for codec/controller */
669  unsigned int shutdown :1; /* being unloaded */
670  unsigned int rirb_error:1; /* error in codec communication */
671  unsigned int response_reset:1; /* controller was reset */
672  unsigned int in_reset:1; /* during reset operation */
673  unsigned int power_keep_link_on:1; /* don't power off HDA link */
674 };
675 
676 /*
677  * codec preset
678  *
679  * Known codecs have the patch to build and set up the controls/PCMs
680  * better than the generic parser.
681  */
683  unsigned int id;
684  unsigned int mask;
685  unsigned int subs;
686  unsigned int subs_mask;
687  unsigned int rev;
688  hda_nid_t afg, mfg;
689  const char *name;
690  int (*patch)(struct hda_codec *codec);
691 };
692 
693 struct hda_codec_preset_list {
694  const struct hda_codec_preset *preset;
695  struct module *owner;
696  struct list_head list;
697 };
698 
699 /* initial hook */
703 /* ops set by the preset patch */
707  int (*init)(struct hda_codec *codec);
708  void (*free)(struct hda_codec *codec);
709  void (*unsol_event)(struct hda_codec *codec, unsigned int res);
710  void (*set_power_state)(struct hda_codec *codec, hda_nid_t fg,
711  unsigned int power_state);
712 #ifdef CONFIG_PM
713  int (*suspend)(struct hda_codec *codec);
714  int (*resume)(struct hda_codec *codec);
715  int (*check_power_status)(struct hda_codec *codec, hda_nid_t nid);
716 #endif
718 };
720 /* record for amp information cache */
721 struct hda_cache_head {
722  u32 key; /* hash key */
723  u16 val; /* assigned value */
724  u16 next; /* next link; -1 = terminal */
725 };
727 struct hda_amp_info {
728  struct hda_cache_head head;
729  u32 amp_caps; /* amp capabilities */
730  u16 vol[2]; /* current volume & mute */
731 };
732 
733 struct hda_cache_rec {
734  u16 hash[64]; /* hash table for index */
735  struct snd_array buf; /* record entries */
736 };
737 
738 /* PCM callbacks */
739 struct hda_pcm_ops {
740  int (*open)(struct hda_pcm_stream *info, struct hda_codec *codec,
741  struct snd_pcm_substream *substream);
742  int (*close)(struct hda_pcm_stream *info, struct hda_codec *codec,
743  struct snd_pcm_substream *substream);
744  int (*prepare)(struct hda_pcm_stream *info, struct hda_codec *codec,
745  unsigned int stream_tag, unsigned int format,
746  struct snd_pcm_substream *substream);
747  int (*cleanup)(struct hda_pcm_stream *info, struct hda_codec *codec,
748  struct snd_pcm_substream *substream);
749 };
751 /* PCM information for each substream */
753  unsigned int substreams; /* number of substreams, 0 = not exist*/
754  unsigned int channels_min; /* min. number of channels */
755  unsigned int channels_max; /* max. number of channels */
756  hda_nid_t nid; /* default NID to query rates/formats/bps, or set up */
757  u32 rates; /* supported rates */
758  u64 formats; /* supported formats (SNDRV_PCM_FMTBIT_) */
759  unsigned int maxbps; /* supported max. bit per sample */
760  struct hda_pcm_ops ops;
761 };
763 /* PCM types */
764 enum {
770 };
772 /* for PCM creation */
773 struct hda_pcm {
774  char *name;
776  unsigned int pcm_type; /* HDA_PCM_TYPE_XXX */
777  int device; /* device number to assign */
778  struct snd_pcm *pcm; /* assigned PCM instance */
779  bool own_chmap; /* codec driver provides own channel maps */
780 };
782 /* codec information */
783 struct hda_codec {
784  struct hda_bus *bus;
785  unsigned int addr; /* codec addr*/
786  struct list_head list; /* list point */
787 
788  hda_nid_t afg; /* AFG node id */
789  hda_nid_t mfg; /* MFG node id */
791  /* ids */
795  u8 mfg_unsol;
796  u32 vendor_id;
800  /* detected preset */
801  const struct hda_codec_preset *preset;
802  struct module *owner;
803  const char *vendor_name; /* codec vendor name */
804  const char *chip_name; /* codec chip name */
805  const char *modelname; /* model name for preset */
806 
807  /* set by patch */
809 
810  /* PCM to create, set by patch_ops.build_pcms callback */
811  unsigned int num_pcms;
812  struct hda_pcm *pcm_info;
813 
814  /* codec specific info */
815  void *spec;
816 
817  /* beep device */
818  struct hda_beep *beep;
819  unsigned int beep_mode;
821  /* widget capabilities cache */
822  unsigned int num_nodes;
823  hda_nid_t start_nid;
824  u32 *wcaps;
826  struct snd_array mixers; /* list of assigned mixer elements */
827  struct snd_array nids; /* list of mapped mixer elements */
829  struct hda_cache_rec amp_cache; /* cache for amp access */
830  struct hda_cache_rec cmd_cache; /* cache for other commands */
832  struct snd_array conn_lists; /* connection-list array */
838  unsigned int spdif_in_enable; /* SPDIF input enable? */
839  const hda_nid_t *slave_dig_outs; /* optional digital out slave widgets */
840  struct snd_array init_pins; /* initial (BIOS) pin configurations */
841  struct snd_array driver_pins; /* pin configs set by codec parser */
842  struct snd_array cvt_setups; /* audio convert setups */
843 
844 #ifdef CONFIG_SND_HDA_HWDEP
845  struct snd_hwdep *hwdep; /* assigned hwdep device */
846  struct snd_array init_verbs; /* additional init verbs */
847  struct snd_array hints; /* additional hints */
848  struct snd_array user_pins; /* default pin configs to override */
849 #endif
850 
851  /* misc flags */
852  unsigned int spdif_status_reset :1; /* needs to toggle SPDIF for each
853  * status change
854  * (e.g. Realtek codecs)
855  */
856  unsigned int pin_amp_workaround:1; /* pin out-amp takes index
857  * (e.g. Conexant codecs)
858  */
859  unsigned int single_adc_amp:1; /* adc in-amp takes no index
860  * (e.g. CX20549 codec)
861  */
862  unsigned int no_sticky_stream:1; /* no sticky-PCM stream assignment */
863  unsigned int pins_shutup:1; /* pins are shut up */
864  unsigned int no_trigger_sense:1; /* don't trigger at pin-sensing */
865  unsigned int no_jack_detect:1; /* Machine has no jack-detection */
866  unsigned int pcm_format_first:1; /* PCM format must be set first */
867  unsigned int epss:1; /* supporting EPSS? */
868 #ifdef CONFIG_PM
869  unsigned int power_on :1; /* current (global) power-state */
870  unsigned int d3_stop_clk:1; /* support D3 operation without BCLK */
871  unsigned int pm_down_notified:1; /* PM notified to controller */
872  unsigned int in_pm:1; /* suspend/resume being performed */
873  int power_transition; /* power-state in transition */
874  int power_count; /* current (global) power refcount */
875  struct delayed_work power_work; /* delayed task for powerdown */
876  unsigned long power_on_acct;
877  unsigned long power_off_acct;
878  unsigned long power_jiffies;
879  spinlock_t power_lock;
880 #endif
881 
882  /* codec-specific additional proc output */
884  struct hda_codec *codec, hda_nid_t nid);
885 
886  /* jack detection */
887  struct snd_array jacktbl;
888 
889 #ifdef CONFIG_SND_HDA_INPUT_JACK
890  /* jack detection */
891  struct snd_array jacks;
892 #endif
893 };
894 
895 /* direction */
896 enum {
898 };
899 
900 
901 /*
902  * constructors
903  */
904 int snd_hda_bus_new(struct snd_card *card, const struct hda_bus_template *temp,
905  struct hda_bus **busp);
906 int snd_hda_codec_new(struct hda_bus *bus, unsigned int codec_addr,
907  struct hda_codec **codecp);
909 
910 /*
911  * low level functions
912  */
913 unsigned int snd_hda_codec_read(struct hda_codec *codec, hda_nid_t nid,
914  int direct,
915  unsigned int verb, unsigned int parm);
916 int snd_hda_codec_write(struct hda_codec *codec, hda_nid_t nid, int direct,
917  unsigned int verb, unsigned int parm);
918 #define snd_hda_param_read(codec, nid, param) \
919  snd_hda_codec_read(codec, nid, 0, AC_VERB_PARAMETERS, param)
920 int snd_hda_get_sub_nodes(struct hda_codec *codec, hda_nid_t nid,
921  hda_nid_t *start_id);
922 int snd_hda_get_connections(struct hda_codec *codec, hda_nid_t nid,
923  hda_nid_t *conn_list, int max_conns);
924 static inline int
925 snd_hda_get_num_conns(struct hda_codec *codec, hda_nid_t nid)
926 {
927  return snd_hda_get_connections(codec, nid, NULL, 0);
928 }
929 int snd_hda_get_raw_connections(struct hda_codec *codec, hda_nid_t nid,
930  hda_nid_t *conn_list, int max_conns);
931 int snd_hda_override_conn_list(struct hda_codec *codec, hda_nid_t nid, int nums,
932  const hda_nid_t *list);
933 int snd_hda_get_conn_index(struct hda_codec *codec, hda_nid_t mux,
934  hda_nid_t nid, int recursive);
935 int snd_hda_query_supported_pcm(struct hda_codec *codec, hda_nid_t nid,
936  u32 *ratesp, u64 *formatsp, unsigned int *bpsp);
938 struct hda_verb {
939  hda_nid_t nid;
940  u32 verb;
941  u32 param;
942 };
943 
945  const struct hda_verb *seq);
946 
947 /* unsolicited event */
948 int snd_hda_queue_unsol_event(struct hda_bus *bus, u32 res, u32 res_ex);
949 
950 /* cached write */
951 #ifdef CONFIG_PM
952 int snd_hda_codec_write_cache(struct hda_codec *codec, hda_nid_t nid,
953  int direct, unsigned int verb, unsigned int parm);
955  const struct hda_verb *seq);
956 int snd_hda_codec_update_cache(struct hda_codec *codec, hda_nid_t nid,
957  int direct, unsigned int verb, unsigned int parm);
958 void snd_hda_codec_resume_cache(struct hda_codec *codec);
959 #else
960 #define snd_hda_codec_write_cache snd_hda_codec_write
961 #define snd_hda_codec_update_cache snd_hda_codec_write
962 #define snd_hda_sequence_write_cache snd_hda_sequence_write
963 #endif
965 /* the struct for codec->pin_configs */
966 struct hda_pincfg {
967  hda_nid_t nid;
968  unsigned char ctrl; /* current pin control value */
969  unsigned char pad; /* reserved */
970  unsigned int cfg; /* default configuration */
971 };
972 
973 unsigned int snd_hda_codec_get_pincfg(struct hda_codec *codec, hda_nid_t nid);
974 int snd_hda_codec_set_pincfg(struct hda_codec *codec, hda_nid_t nid,
975  unsigned int cfg);
976 int snd_hda_add_pincfg(struct hda_codec *codec, struct snd_array *list,
977  hda_nid_t nid, unsigned int cfg); /* for hwdep */
980 /* SPDIF controls */
981 struct hda_spdif_out {
982  hda_nid_t nid; /* Converter nid values relate to */
983  unsigned int status; /* IEC958 status bits */
984  unsigned short ctls; /* SPDIF control bits */
985 };
987  hda_nid_t nid);
989 void snd_hda_spdif_ctls_assign(struct hda_codec *codec, int idx, hda_nid_t nid);
990 
991 /*
992  * Mixer
993  */
994 int snd_hda_build_controls(struct hda_bus *bus);
996 
997 /*
998  * PCM
999  */
1000 int snd_hda_build_pcms(struct hda_bus *bus);
1002 
1004  struct hda_pcm_stream *hinfo,
1005  unsigned int stream,
1006  unsigned int format,
1007  struct snd_pcm_substream *substream);
1009  struct hda_pcm_stream *hinfo,
1010  struct snd_pcm_substream *substream);
1011 
1012 void snd_hda_codec_setup_stream(struct hda_codec *codec, hda_nid_t nid,
1013  u32 stream_tag,
1014  int channel_id, int format);
1015 void __snd_hda_codec_cleanup_stream(struct hda_codec *codec, hda_nid_t nid,
1016  int do_now);
1017 #define snd_hda_codec_cleanup_stream(codec, nid) \
1018  __snd_hda_codec_cleanup_stream(codec, nid, 0)
1019 unsigned int snd_hda_calc_stream_format(unsigned int rate,
1020  unsigned int channels,
1021  unsigned int format,
1022  unsigned int maxbps,
1023  unsigned short spdif_ctls);
1024 int snd_hda_is_supported_format(struct hda_codec *codec, hda_nid_t nid,
1025  unsigned int format);
1026 
1027 /*
1028  * Misc
1029  */
1030 void snd_hda_get_codec_name(struct hda_codec *codec, char *name, int namelen);
1031 void snd_hda_bus_reboot_notify(struct hda_bus *bus);
1032 void snd_hda_codec_set_power_to_all(struct hda_codec *codec, hda_nid_t fg,
1033  unsigned int power_state,
1034  bool eapd_workaround);
1035 
1036 int snd_hda_lock_devices(struct hda_bus *bus);
1037 void snd_hda_unlock_devices(struct hda_bus *bus);
1038 
1039 /*
1040  * power management
1041  */
1042 #ifdef CONFIG_PM
1043 int snd_hda_suspend(struct hda_bus *bus);
1044 int snd_hda_resume(struct hda_bus *bus);
1045 #endif
1046 
1047 static inline
1048 int hda_call_check_power_status(struct hda_codec *codec, hda_nid_t nid)
1049 {
1050 #ifdef CONFIG_PM
1051  if (codec->patch_ops.check_power_status)
1052  return codec->patch_ops.check_power_status(codec, nid);
1053 #endif
1054  return 0;
1055 }
1056 
1057 /*
1058  * get widget information
1059  */
1061 const char *snd_hda_get_jack_type(u32 cfg);
1062 const char *snd_hda_get_jack_location(u32 cfg);
1063 
1064 /*
1065  * power saving
1066  */
1067 #ifdef CONFIG_PM
1068 void snd_hda_power_save(struct hda_codec *codec, int delta, bool d3wait);
1069 void snd_hda_update_power_acct(struct hda_codec *codec);
1070 #else
1071 static inline void snd_hda_power_save(struct hda_codec *codec, int delta,
1072  bool d3wait) {}
1073 #endif
1074 
1082 static inline void snd_hda_power_up(struct hda_codec *codec)
1083 {
1084  snd_hda_power_save(codec, 1, false);
1085 }
1086 
1097 static inline void snd_hda_power_up_d3wait(struct hda_codec *codec)
1098 {
1099  snd_hda_power_save(codec, 1, true);
1100 }
1101 
1109 static inline void snd_hda_power_down(struct hda_codec *codec)
1110 {
1111  snd_hda_power_save(codec, -1, false);
1112 }
1113 
1121 static inline void snd_hda_power_sync(struct hda_codec *codec)
1122 {
1123  snd_hda_power_save(codec, 0, false);
1124 }
1125 
1126 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1127 /*
1128  * patch firmware
1129  */
1130 int snd_hda_load_patch(struct hda_bus *bus, size_t size, const void *buf);
1131 #endif
1132 
1133 /*
1134  * Codec modularization
1135  */
1136 
1137 /* Export symbols only for communication with codec drivers;
1138  * When built in kernel, all HD-audio drivers are supposed to be statically
1139  * linked to the kernel. Thus, the symbols don't have to (or shouldn't) be
1140  * exported unless it's built as a module.
1141  */
1142 #ifdef MODULE
1143 #define EXPORT_SYMBOL_HDA(sym) EXPORT_SYMBOL_GPL(sym)
1144 #else
1145 #define EXPORT_SYMBOL_HDA(sym)
1146 #endif
1147 
1148 #endif /* __SOUND_HDA_CODEC_H */