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#define | HDSP_MAX_CHANNELS 26 |
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#define | HDSP_MAX_DS_CHANNELS 14 |
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#define | HDSP_MAX_QS_CHANNELS 8 |
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#define | DIGIFACE_SS_CHANNELS 26 |
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#define | DIGIFACE_DS_CHANNELS 14 |
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#define | MULTIFACE_SS_CHANNELS 18 |
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#define | MULTIFACE_DS_CHANNELS 14 |
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#define | H9652_SS_CHANNELS 26 |
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#define | H9652_DS_CHANNELS 14 |
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#define | H9632_SS_CHANNELS 12 |
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#define | H9632_DS_CHANNELS 8 |
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#define | H9632_QS_CHANNELS 4 |
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#define | RPM_CHANNELS 6 |
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#define | HDSP_resetPointer 0 |
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#define | HDSP_freqReg 0 |
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#define | HDSP_outputBufferAddress 32 |
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#define | HDSP_inputBufferAddress 36 |
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#define | HDSP_controlRegister 64 |
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#define | HDSP_interruptConfirmation 96 |
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#define | HDSP_outputEnable 128 |
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#define | HDSP_control2Reg 256 |
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#define | HDSP_midiDataOut0 352 |
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#define | HDSP_midiDataOut1 356 |
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#define | HDSP_fifoData 368 |
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#define | HDSP_inputEnable 384 |
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#define | HDSP_statusRegister 0 |
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#define | HDSP_timecode 128 |
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#define | HDSP_status2Register 192 |
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#define | HDSP_midiDataIn0 360 |
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#define | HDSP_midiDataIn1 364 |
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#define | HDSP_midiStatusOut0 384 |
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#define | HDSP_midiStatusOut1 388 |
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#define | HDSP_midiStatusIn0 392 |
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#define | HDSP_midiStatusIn1 396 |
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#define | HDSP_fifoStatus 400 |
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#define | HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */ |
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#define | HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */ |
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#define | HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */ |
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#define | HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */ |
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#define | HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */ |
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#define | HDSP_9652_peakBase 7164 |
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#define | HDSP_9652_rmsBase 4096 |
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#define | HDSP_9632_metersBase 4096 |
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#define | HDSP_IO_EXTENT 7168 |
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#define | HDSP_TMS 0x01 |
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#define | HDSP_TCK 0x02 |
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#define | HDSP_TDI 0x04 |
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#define | HDSP_JTAG 0x08 |
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#define | HDSP_PWDN 0x10 |
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#define | HDSP_PROGRAM 0x020 |
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#define | HDSP_CONFIG_MODE_0 0x040 |
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#define | HDSP_CONFIG_MODE_1 0x080 |
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#define | HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD) |
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#define | HDSP_BIGENDIAN_MODE 0x200 |
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#define | HDSP_RD_MULTIPLE 0x400 |
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#define | HDSP_9652_ENABLE_MIXER 0x800 |
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#define | HDSP_TDO 0x10000000 |
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#define | HDSP_S_PROGRAM (HDSP_PROGRAM|HDSP_CONFIG_MODE_0) |
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#define | HDSP_S_LOAD (HDSP_PROGRAM|HDSP_CONFIG_MODE_1) |
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#define | HDSP_Start (1<<0) /* start engine */ |
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#define | HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */ |
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#define | HDSP_Latency1 (1<<2) /* [ see above ] */ |
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#define | HDSP_Latency2 (1<<3) /* [ see above ] */ |
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#define | HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */ |
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#define | HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */ |
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#define | HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */ |
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#define | HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */ |
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#define | HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ |
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#define | HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */ |
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#define | HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */ |
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#define | HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */ |
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#define | HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */ |
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#define | HDSP_SyncRef2 (1<<13) |
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#define | HDSP_SPDIFInputSelect0 (1<<14) |
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#define | HDSP_SPDIFInputSelect1 (1<<15) |
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#define | HDSP_SyncRef0 (1<<16) |
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#define | HDSP_SyncRef1 (1<<17) |
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#define | HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */ |
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#define | HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */ |
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#define | HDSP_Midi0InterruptEnable (1<<22) |
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#define | HDSP_Midi1InterruptEnable (1<<23) |
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#define | HDSP_LineOut (1<<24) |
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#define | HDSP_ADGain0 (1<<25) /* From here : H9632 specific */ |
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#define | HDSP_ADGain1 (1<<26) |
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#define | HDSP_DAGain0 (1<<27) |
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#define | HDSP_DAGain1 (1<<28) |
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#define | HDSP_PhoneGain0 (1<<29) |
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#define | HDSP_PhoneGain1 (1<<30) |
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#define | HDSP_QuadSpeed (1<<31) |
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#define | HDSP_RPM_Inp12 0x04A00 |
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#define | HDSP_RPM_Inp12_Phon_6dB 0x00800 /* Dolby */ |
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#define | HDSP_RPM_Inp12_Phon_0dB 0x00000 /* .. */ |
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#define | HDSP_RPM_Inp12_Phon_n6dB 0x04000 /* inp_0 */ |
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#define | HDSP_RPM_Inp12_Line_0dB 0x04200 /* Dolby+PRO */ |
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#define | HDSP_RPM_Inp12_Line_n6dB 0x00200 /* PRO */ |
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#define | HDSP_RPM_Inp34 0x32000 |
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#define | HDSP_RPM_Inp34_Phon_6dB 0x20000 /* SyncRef1 */ |
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#define | HDSP_RPM_Inp34_Phon_0dB 0x00000 /* .. */ |
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#define | HDSP_RPM_Inp34_Phon_n6dB 0x02000 /* SyncRef2 */ |
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#define | HDSP_RPM_Inp34_Line_0dB 0x30000 /* SyncRef1+SyncRef0 */ |
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#define | HDSP_RPM_Inp34_Line_n6dB 0x10000 /* SyncRef0 */ |
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#define | HDSP_RPM_Bypass 0x01000 |
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#define | HDSP_RPM_Disconnect 0x00001 |
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#define | HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1) |
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#define | HDSP_ADGainMinus10dBV HDSP_ADGainMask |
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#define | HDSP_ADGainPlus4dBu (HDSP_ADGain0) |
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#define | HDSP_ADGainLowGain 0 |
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#define | HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1) |
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#define | HDSP_DAGainHighGain HDSP_DAGainMask |
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#define | HDSP_DAGainPlus4dBu (HDSP_DAGain0) |
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#define | HDSP_DAGainMinus10dBV 0 |
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#define | HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1) |
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#define | HDSP_PhoneGain0dB HDSP_PhoneGainMask |
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#define | HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0) |
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#define | HDSP_PhoneGainMinus12dB 0 |
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#define | HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2) |
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#define | HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed) |
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#define | HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) |
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#define | HDSP_SPDIFInputADAT1 0 |
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#define | HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0) |
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#define | HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1) |
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#define | HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) |
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#define | HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2) |
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#define | HDSP_SyncRef_ADAT1 0 |
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#define | HDSP_SyncRef_ADAT2 (HDSP_SyncRef0) |
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#define | HDSP_SyncRef_ADAT3 (HDSP_SyncRef1) |
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#define | HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1) |
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#define | HDSP_SyncRef_WORD (HDSP_SyncRef2) |
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#define | HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2) |
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#define | HDSP_CLOCK_SOURCE_AUTOSYNC 0 |
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#define | HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1 |
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#define | HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2 |
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#define | HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3 |
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#define | HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4 |
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#define | HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5 |
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#define | HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6 |
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#define | HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7 |
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#define | HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8 |
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#define | HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9 |
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#define | HDSP_SYNC_FROM_WORD 0 |
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#define | HDSP_SYNC_FROM_SPDIF 1 |
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#define | HDSP_SYNC_FROM_ADAT1 2 |
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#define | HDSP_SYNC_FROM_ADAT_SYNC 3 |
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#define | HDSP_SYNC_FROM_ADAT2 4 |
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#define | HDSP_SYNC_FROM_ADAT3 5 |
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#define | HDSP_SYNC_CHECK_NO_LOCK 0 |
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#define | HDSP_SYNC_CHECK_LOCK 1 |
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#define | HDSP_SYNC_CHECK_SYNC 2 |
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#define | HDSP_AUTOSYNC_FROM_WORD 0 |
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#define | HDSP_AUTOSYNC_FROM_ADAT_SYNC 1 |
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#define | HDSP_AUTOSYNC_FROM_SPDIF 2 |
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#define | HDSP_AUTOSYNC_FROM_NONE 3 |
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#define | HDSP_AUTOSYNC_FROM_ADAT1 4 |
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#define | HDSP_AUTOSYNC_FROM_ADAT2 5 |
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#define | HDSP_AUTOSYNC_FROM_ADAT3 6 |
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#define | HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */ |
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#define | HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */ |
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#define | HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */ |
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#define | HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/ |
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#define | HDSP_Frequency32KHz HDSP_Frequency0 |
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#define | HDSP_Frequency44_1KHz HDSP_Frequency1 |
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#define | HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0) |
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#define | HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0) |
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#define | HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1) |
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#define | HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) |
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#define | HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0) |
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#define | HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1) |
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#define | HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) |
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#define | DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */ |
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#define | hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask) |
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#define | hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1) |
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#define | hdsp_encode_spdif_in(x) (((x)&0x3)<<14) |
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#define | hdsp_decode_spdif_in(x) (((x)>>14)&0x3) |
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#define | HDSP_audioIRQPending (1<<0) |
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#define | HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */ |
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#define | HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */ |
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#define | HDSP_Lock1 (1<<2) |
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#define | HDSP_Lock0 (1<<3) |
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#define | HDSP_SPDIFSync (1<<4) |
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#define | HDSP_TimecodeLock (1<<5) |
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#define | HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ |
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#define | HDSP_Sync2 (1<<16) |
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#define | HDSP_Sync1 (1<<17) |
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#define | HDSP_Sync0 (1<<18) |
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#define | HDSP_DoubleSpeedStatus (1<<19) |
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#define | HDSP_ConfigError (1<<20) |
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#define | HDSP_DllError (1<<21) |
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#define | HDSP_spdifFrequency0 (1<<22) |
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#define | HDSP_spdifFrequency1 (1<<23) |
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#define | HDSP_spdifFrequency2 (1<<24) |
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#define | HDSP_SPDIFErrorFlag (1<<25) |
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#define | HDSP_BufferID (1<<26) |
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#define | HDSP_TimecodeSync (1<<27) |
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#define | HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */ |
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#define | HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */ |
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#define | HDSP_midi0IRQPending (1<<30) |
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#define | HDSP_midi1IRQPending (1<<31) |
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#define | HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2) |
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#define | HDSP_spdifFrequencyMask_9632 |
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#define | HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0) |
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#define | HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1) |
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#define | HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1) |
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#define | HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2) |
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#define | HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2) |
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#define | HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1) |
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#define | HDSP_spdifFrequency128KHz |
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#define | HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3 |
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#define | HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0) |
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#define | HDSP_version0 (1<<0) |
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#define | HDSP_version1 (1<<1) |
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#define | HDSP_version2 (1<<2) |
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#define | HDSP_wc_lock (1<<3) |
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#define | HDSP_wc_sync (1<<4) |
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#define | HDSP_inp_freq0 (1<<5) |
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#define | HDSP_inp_freq1 (1<<6) |
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#define | HDSP_inp_freq2 (1<<7) |
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#define | HDSP_SelSyncRef0 (1<<8) |
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#define | HDSP_SelSyncRef1 (1<<9) |
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#define | HDSP_SelSyncRef2 (1<<10) |
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#define | HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync) |
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#define | HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2) |
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#define | HDSP_systemFrequency32 (HDSP_inp_freq0) |
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#define | HDSP_systemFrequency44_1 (HDSP_inp_freq1) |
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#define | HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1) |
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#define | HDSP_systemFrequency64 (HDSP_inp_freq2) |
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#define | HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2) |
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#define | HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2) |
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#define | HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2) |
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#define | HDSP_SelSyncRef_ADAT1 0 |
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#define | HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0) |
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#define | HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1) |
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#define | HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1) |
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#define | HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2) |
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#define | HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2) |
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#define | HDSP_InitializationComplete (1<<0) |
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#define | HDSP_FirmwareLoaded (1<<1) |
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#define | HDSP_FirmwareCached (1<<2) |
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#define | HDSP_LONG_WAIT 5000 |
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#define | HDSP_SHORT_WAIT 30 |
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#define | UNITY_GAIN 32768 |
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#define | MINUS_INFINITY_GAIN 0 |
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#define | HDSP_CHANNEL_BUFFER_SAMPLES (16*1024) |
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#define | HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES) |
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#define | HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES) |
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#define | HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024) |
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#define | HDSP_SPDIF_IN(xname, xindex) |
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#define | HDSP_SPDIF_OUT(xname, xindex) |
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#define | snd_hdsp_info_spdif_bits snd_ctl_boolean_mono_info |
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#define | HDSP_SPDIF_PROFESSIONAL(xname, xindex) |
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#define | HDSP_SPDIF_EMPHASIS(xname, xindex) |
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#define | HDSP_SPDIF_NON_AUDIO(xname, xindex) |
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#define | HDSP_SPDIF_SAMPLE_RATE(xname, xindex) |
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#define | HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) |
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#define | HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) |
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#define | HDSP_SYSTEM_CLOCK_MODE(xname, xindex) |
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#define | HDSP_CLOCK_SOURCE(xname, xindex) |
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#define | snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info |
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#define | HDSP_DA_GAIN(xname, xindex) |
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#define | HDSP_AD_GAIN(xname, xindex) |
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#define | HDSP_PHONE_GAIN(xname, xindex) |
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#define | HDSP_XLR_BREAKOUT_CABLE(xname, xindex) |
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#define | snd_hdsp_info_xlr_breakout_cable snd_ctl_boolean_mono_info |
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#define | HDSP_AEB(xname, xindex) |
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#define | snd_hdsp_info_aeb snd_ctl_boolean_mono_info |
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#define | HDSP_PREF_SYNC_REF(xname, xindex) |
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#define | HDSP_AUTOSYNC_REF(xname, xindex) |
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#define | HDSP_LINE_OUT(xname, xindex) |
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#define | snd_hdsp_info_line_out snd_ctl_boolean_mono_info |
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#define | HDSP_PRECISE_POINTER(xname, xindex) |
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#define | snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info |
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#define | HDSP_USE_MIDI_TASKLET(xname, xindex) |
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#define | snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info |
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#define | HDSP_MIXER(xname, xindex) |
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#define | HDSP_WC_SYNC_CHECK(xname, xindex) |
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#define | HDSP_SPDIF_SYNC_CHECK(xname, xindex) |
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#define | HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) |
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#define | HDSP_ADAT_SYNC_CHECK |
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#define | HDSP_DDS_OFFSET(xname, xindex) |
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