|
| #define | ED_DEQUEUE (1 << 27) |
| |
| #define | ED_ISO (1 << 15) |
| |
| #define | ED_SKIP (1 << 14) |
| |
| #define | ED_LOWSPEED (1 << 13) |
| |
| #define | ED_OUT (0x01 << 11) |
| |
| #define | ED_IN (0x02 << 11) |
| |
| #define | ED_C (0x02) /* toggle carry */ |
| |
| #define | ED_H (0x01) /* halted */ |
| |
| #define | ED_IDLE 0x00 /* NOT linked to HC */ |
| |
| #define | ED_UNLINK 0x01 /* being unlinked from hc */ |
| |
| #define | ED_OPER 0x02 /* IS linked to hc */ |
| |
| #define | ED_MASK ((u32)~0x0f) /* strip hw status in low addr bits */ |
| |
| #define | TD_CC 0xf0000000 /* condition code */ |
| |
| #define | TD_CC_GET(td_p) ((td_p >>28) & 0x0f) |
| |
| #define | TD_DI 0x00E00000 /* frames before interrupt */ |
| |
| #define | TD_DI_SET(X) (((X) & 0x07)<< 21) |
| |
| #define | TD_DONE 0x00020000 /* retired to donelist */ |
| |
| #define | TD_ISO 0x00010000 /* copy of ED_ISO */ |
| |
| #define | TD_EC 0x0C000000 /* error count */ |
| |
| #define | TD_T 0x03000000 /* data toggle state */ |
| |
| #define | TD_T_DATA0 0x02000000 /* DATA0 */ |
| |
| #define | TD_T_DATA1 0x03000000 /* DATA1 */ |
| |
| #define | TD_T_TOGGLE 0x00000000 /* uses ED_C */ |
| |
| #define | TD_DP 0x00180000 /* direction/pid */ |
| |
| #define | TD_DP_SETUP 0x00000000 /* SETUP pid */ |
| |
| #define | TD_DP_IN 0x00100000 /* IN pid */ |
| |
| #define | TD_DP_OUT 0x00080000 /* OUT pid */ |
| |
| #define | TD_R 0x00040000 /* round: short packets OK? */ |
| |
| #define | MAXPSW 2 |
| |
| #define | TD_MASK ((u32)~0x1f) /* strip hw status in low addr bits */ |
| |
| #define | TD_CC_NOERROR 0x00 |
| |
| #define | TD_CC_CRC 0x01 |
| |
| #define | TD_CC_BITSTUFFING 0x02 |
| |
| #define | TD_CC_DATATOGGLEM 0x03 |
| |
| #define | TD_CC_STALL 0x04 |
| |
| #define | TD_DEVNOTRESP 0x05 |
| |
| #define | TD_PIDCHECKFAIL 0x06 |
| |
| #define | TD_UNEXPECTEDPID 0x07 |
| |
| #define | TD_DATAOVERRUN 0x08 |
| |
| #define | TD_DATAUNDERRUN 0x09 |
| |
| #define | TD_BUFFEROVERRUN 0x0C |
| |
| #define | TD_BUFFERUNDERRUN 0x0D |
| |
| #define | TD_NOTACCESSED 0x0F |
| |
| #define | NUM_INTS 32 |
| |
| #define | MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports (RH_A_NDP) */ |
| |
| #define | OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ |
| |
| #define | OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ |
| |
| #define | OHCI_CTRL_IE (1 << 3) /* isochronous enable */ |
| |
| #define | OHCI_CTRL_CLE (1 << 4) /* control list enable */ |
| |
| #define | OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ |
| |
| #define | OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ |
| |
| #define | OHCI_CTRL_IR (1 << 8) /* interrupt routing */ |
| |
| #define | OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ |
| |
| #define | OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ |
| |
| #define | OHCI_USB_RESET (0 << 6) |
| |
| #define | OHCI_USB_RESUME (1 << 6) |
| |
| #define | OHCI_USB_OPER (2 << 6) |
| |
| #define | OHCI_USB_SUSPEND (3 << 6) |
| |
| #define | OHCI_HCR (1 << 0) /* host controller reset */ |
| |
| #define | OHCI_CLF (1 << 1) /* control list filled */ |
| |
| #define | OHCI_BLF (1 << 2) /* bulk list filled */ |
| |
| #define | OHCI_OCR (1 << 3) /* ownership change request */ |
| |
| #define | OHCI_SOC (3 << 16) /* scheduling overrun count */ |
| |
| #define | OHCI_INTR_SO (1 << 0) /* scheduling overrun */ |
| |
| #define | OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ |
| |
| #define | OHCI_INTR_SF (1 << 2) /* start frame */ |
| |
| #define | OHCI_INTR_RD (1 << 3) /* resume detect */ |
| |
| #define | OHCI_INTR_UE (1 << 4) /* unrecoverable error */ |
| |
| #define | OHCI_INTR_FNO (1 << 5) /* frame number overflow */ |
| |
| #define | OHCI_INTR_RHSC (1 << 6) /* root hub status change */ |
| |
| #define | OHCI_INTR_OC (1 << 30) /* ownership change */ |
| |
| #define | OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ |
| |
| #define | RH_PS_CCS 0x00000001 /* current connect status */ |
| |
| #define | RH_PS_PES 0x00000002 /* port enable status*/ |
| |
| #define | RH_PS_PSS 0x00000004 /* port suspend status */ |
| |
| #define | RH_PS_POCI 0x00000008 /* port over current indicator */ |
| |
| #define | RH_PS_PRS 0x00000010 /* port reset status */ |
| |
| #define | RH_PS_PPS 0x00000100 /* port power status */ |
| |
| #define | RH_PS_LSDA 0x00000200 /* low speed device attached */ |
| |
| #define | RH_PS_CSC 0x00010000 /* connect status change */ |
| |
| #define | RH_PS_PESC 0x00020000 /* port enable status change */ |
| |
| #define | RH_PS_PSSC 0x00040000 /* port suspend status change */ |
| |
| #define | RH_PS_OCIC 0x00080000 /* over current indicator change */ |
| |
| #define | RH_PS_PRSC 0x00100000 /* port reset status change */ |
| |
| #define | RH_HS_LPS 0x00000001 /* local power status */ |
| |
| #define | RH_HS_OCI 0x00000002 /* over current indicator */ |
| |
| #define | RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ |
| |
| #define | RH_HS_LPSC 0x00010000 /* local power status change */ |
| |
| #define | RH_HS_OCIC 0x00020000 /* over current indicator change */ |
| |
| #define | RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ |
| |
| #define | RH_B_DR 0x0000ffff /* device removable flags */ |
| |
| #define | RH_B_PPCM 0xffff0000 /* port power control mask */ |
| |
| #define | RH_A_NDP (0xff << 0) /* number of downstream ports */ |
| |
| #define | RH_A_PSM (1 << 8) /* power switching mode */ |
| |
| #define | RH_A_NPS (1 << 9) /* no power switching */ |
| |
| #define | RH_A_DT (1 << 10) /* device type (mbz) */ |
| |
| #define | RH_A_OCPM (1 << 11) /* over current protection mode */ |
| |
| #define | RH_A_NOCP (1 << 12) /* no over current protection */ |
| |
| #define | RH_A_POTPGT (0xff << 24) /* power on to power good time */ |
| |
| #define | TD_HASH_SIZE 64 /* power'o'two */ |
| |
| #define | TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE) |
| |
| #define | OHCI_QUIRK_AMD756 0x01 /* erratum #4 */ |
| |
| #define | OHCI_QUIRK_SUPERIO 0x02 /* natsemi */ |
| |
| #define | OHCI_QUIRK_INITRESET 0x04 /* SiS, OPTi, ... */ |
| |
| #define | OHCI_QUIRK_BE_DESC 0x08 /* BE descriptors */ |
| |
| #define | OHCI_QUIRK_BE_MMIO 0x10 /* BE registers */ |
| |
| #define | OHCI_QUIRK_ZFMICRO 0x20 /* Compaq ZFMicro chipset*/ |
| |
| #define | OHCI_QUIRK_NEC 0x40 /* lost interrupts */ |
| |
| #define | OHCI_QUIRK_FRAME_NO 0x80 /* no big endian frame_no shift */ |
| |
| #define | OHCI_QUIRK_HUB_POWER 0x100 /* distrust firmware power/oc setup */ |
| |
| #define | OHCI_QUIRK_AMD_PLL 0x200 /* AMD PLL quirk*/ |
| |
| #define | OHCI_QUIRK_AMD_PREFETCH 0x400 /* pre-fetch for ISO transfer */ |
| |
| #define | STUB_DEBUG_FILES |
| |
| #define | ohci_dbg(ohci, fmt, args...) dev_dbg (ohci_to_hcd(ohci)->self.controller , fmt , ## args ) |
| |
| #define | ohci_err(ohci, fmt, args...) dev_err (ohci_to_hcd(ohci)->self.controller , fmt , ## args ) |
| |
| #define | ohci_info(ohci, fmt, args...) dev_info (ohci_to_hcd(ohci)->self.controller , fmt , ## args ) |
| |
| #define | ohci_warn(ohci, fmt, args...) dev_warn (ohci_to_hcd(ohci)->self.controller , fmt , ## args ) |
| |
| #define | ohci_vdbg(ohci, fmt, args...) do { } while (0) |
| |
| #define | big_endian_desc(ohci) 0 /* only little endian */ |
| |
| #define | big_endian_mmio(ohci) 0 /* only little endian */ |
| |
| #define | ohci_readl(o, r) _ohci_readl(o,r) |
| |
| #define | ohci_writel(o, v, r) _ohci_writel(o,v,r) |
| |
| #define | big_endian_frame_no_quirk(ohci) 0 |
| |
| #define | FI 0x2edf /* 12000 bits per frame (-1) */ |
| |
| #define | FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7)) |
| |
| #define | FIT (1 << 31) |
| |
| #define | LSTHRESH 0x628 /* lowspeed bit threshold */ |
| |
| #define | read_roothub(hc, register, mask) |
| |
1.8.2