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#define | EHCA_MAX_MTU 4 |
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#define | QPX_SQADDER EHCA_BMASK_IBM(48, 63) |
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#define | QPX_RQADDER EHCA_BMASK_IBM(48, 63) |
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#define | QPX_AAELOG_RESET_SRQ_LIMIT EHCA_BMASK_IBM(3, 3) |
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#define | QPTEMM_OFFSET(x) offsetof(struct hipz_qptemm, x) |
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#define | MRMWMM_OFFSET(x) offsetof(struct hipz_mrmwmm, x) |
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#define | QPEDMM_OFFSET(x) offsetof(struct hipz_qpedmm, x) |
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#define | CQX_FEC_CQE_CNT EHCA_BMASK_IBM(32, 63) |
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#define | CQX_FECADDER EHCA_BMASK_IBM(32, 63) |
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#define | CQX_N0_GENERATE_SOLICITED_COMP_EVENT EHCA_BMASK_IBM(0, 0) |
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#define | CQX_N1_GENERATE_COMP_EVENT EHCA_BMASK_IBM(0, 0) |
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#define | CQTEMM_OFFSET(x) offsetof(struct hipz_cqtemm, x) |
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#define | EQTEMM_OFFSET(x) offsetof(struct hipz_eqtemm, x) |
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#define | HIPZ_ACCESSCTRL_L_WRITE 0x00800000 |
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#define | HIPZ_ACCESSCTRL_R_WRITE 0x00400000 |
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#define | HIPZ_ACCESSCTRL_R_READ 0x00200000 |
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#define | HIPZ_ACCESSCTRL_R_ATOMIC 0x00100000 |
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#define | HIPZ_ACCESSCTRL_MW_BIND 0x00080000 |
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#define | HCA_CAP_AH_PORT_NR_CHECK EHCA_BMASK_IBM( 0, 0) |
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#define | HCA_CAP_ATOMIC EHCA_BMASK_IBM( 1, 1) |
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#define | HCA_CAP_AUTO_PATH_MIG EHCA_BMASK_IBM( 2, 2) |
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#define | HCA_CAP_BAD_P_KEY_CTR EHCA_BMASK_IBM( 3, 3) |
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#define | HCA_CAP_SQD_RTS_PORT_CHANGE EHCA_BMASK_IBM( 4, 4) |
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#define | HCA_CAP_CUR_QP_STATE_MOD EHCA_BMASK_IBM( 5, 5) |
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#define | HCA_CAP_INIT_TYPE EHCA_BMASK_IBM( 6, 6) |
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#define | HCA_CAP_PORT_ACTIVE_EVENT EHCA_BMASK_IBM( 7, 7) |
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#define | HCA_CAP_Q_KEY_VIOL_CTR EHCA_BMASK_IBM( 8, 8) |
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#define | HCA_CAP_WQE_RESIZE EHCA_BMASK_IBM( 9, 9) |
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#define | HCA_CAP_RAW_PACKET_MCAST EHCA_BMASK_IBM(10, 10) |
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#define | HCA_CAP_SHUTDOWN_PORT EHCA_BMASK_IBM(11, 11) |
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#define | HCA_CAP_RC_LL_QP EHCA_BMASK_IBM(12, 12) |
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#define | HCA_CAP_SRQ EHCA_BMASK_IBM(13, 13) |
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#define | HCA_CAP_UD_LL_QP EHCA_BMASK_IBM(16, 16) |
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#define | HCA_CAP_RESIZE_MR EHCA_BMASK_IBM(17, 17) |
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#define | HCA_CAP_MINI_QP EHCA_BMASK_IBM(18, 18) |
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#define | HCA_CAP_H_ALLOC_RES_SYNC EHCA_BMASK_IBM(19, 19) |
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