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| #define | DEV_LABEL "hrz" |
| |
| #define | PCI_VENDOR_ID_MADGE 0x10B6 |
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| #define | PCI_DEVICE_ID_MADGE_HORIZON 0x1000 |
| |
| #define | PRINTK(severity, format, args...) printk(severity DEV_LABEL ": " format "\n" , ## args) |
| |
| #define | PRINTD(bits, format, args...) |
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| #define | PRINTDB(bits, format, args...) |
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| #define | PRINTDM(bits, format, args...) |
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| #define | PRINTDE(bits, format, args...) |
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| #define | PRINTDD(sec, fmt, args...) |
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| #define | PRINTDDB(sec, fmt, args...) |
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| #define | PRINTDDM(sec, fmt, args...) |
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| #define | PRINTDDE(sec, fmt, args...) |
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| #define | SPARE_BUFFER_POOL_SIZE MAX_VCS |
| |
| #define | HRZ_MAX_VPI 4 |
| |
| #define | MIN_PCI_LATENCY 48 |
| |
| #define | HRZ_IO_EXTENT 0x80 |
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| #define | DATA_PORT_OFF 0x00 |
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| #define | TX_CHANNEL_PORT_OFF 0x04 |
| |
| #define | TX_DESCRIPTOR_PORT_OFF 0x08 |
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| #define | MEMORY_PORT_OFF 0x0C |
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| #define | MEM_WR_ADDR_REG_OFF 0x14 |
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| #define | MEM_RD_ADDR_REG_OFF 0x18 |
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| #define | CONTROL_0_REG 0x1C |
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| #define | INT_SOURCE_REG_OFF 0x20 |
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| #define | INT_ENABLE_REG_OFF 0x24 |
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| #define | MASTER_RX_ADDR_REG_OFF 0x28 |
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| #define | MASTER_RX_COUNT_REG_OFF 0x2C |
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| #define | MASTER_TX_ADDR_REG_OFF 0x30 |
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| #define | MASTER_TX_COUNT_REG_OFF 0x34 |
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| #define | TX_DESCRIPTOR_REG_OFF 0x38 |
| |
| #define | TX_CHANNEL_CONFIG_COMMAND_OFF 0x40 |
| |
| #define | TX_CHANNEL_CONFIG_DATA_OFF 0x44 |
| |
| #define | TX_FREE_BUFFER_COUNT_OFF 0x48 |
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| #define | RX_FREE_BUFFER_COUNT_OFF 0x4C |
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| #define | TX_CONFIG_OFF 0x50 |
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| #define | TX_STATUS_OFF 0x54 |
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| #define | RX_CONFIG_OFF 0x58 |
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| #define | RX_LINE_CONFIG_OFF 0x5C |
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| #define | RX_QUEUE_RD_PTR_OFF 0x60 |
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| #define | RX_QUEUE_WR_PTR_OFF 0x64 |
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| #define | MAX_AAL5_CELL_COUNT_OFF 0x68 |
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| #define | RX_CHANNEL_PORT_OFF 0x6C |
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| #define | TX_CELL_COUNT_OFF 0x70 |
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| #define | RX_CELL_COUNT_OFF 0x74 |
| |
| #define | HEC_ERROR_COUNT_OFF 0x78 |
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| #define | UNASSIGNED_CELL_COUNT_OFF 0x7C |
| |
| #define | SEEPROM_DO 0x00000001 |
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| #define | SEEPROM_DI 0x00000002 |
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| #define | SEEPROM_SK 0x00000004 |
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| #define | SEEPROM_CS 0x00000008 |
| |
| #define | DEBUG_BIT_0 0x00000010 |
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| #define | DEBUG_BIT_1 0x00000020 |
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| #define | DEBUG_BIT_2 0x00000040 |
| |
| #define | DEBUG_BIT_0_OE 0x00000100 |
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| #define | DEBUG_BIT_1_OE 0x00000200 |
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| #define | DEBUG_BIT_2_OE 0x00000400 |
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| #define | DEBUG_BIT_0_STATE 0x00001000 |
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| #define | DEBUG_BIT_1_STATE 0x00002000 |
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| #define | DEBUG_BIT_2_STATE 0x00004000 |
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| #define | GENERAL_BIT_0 0x00010000 |
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| #define | GENERAL_BIT_1 0x00020000 |
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| #define | GENERAL_BIT_2 0x00040000 |
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| #define | GENERAL_BIT_3 0x00080000 |
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| #define | RESET_HORIZON 0x00100000 |
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| #define | RESET_ATM 0x00200000 |
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| #define | RESET_RX 0x00400000 |
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| #define | RESET_TX 0x00800000 |
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| #define | RESET_HOST 0x01000000 |
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| #define | TARGET_RETRY_DISABLE 0x04000000 |
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| #define | ATM_LAYER_SELECT 0x08000000 |
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| #define | ATM_LAYER_STATUS 0x10000000 |
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| #define | RX_DATA_AV 0x00000001 |
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| #define | RX_DISABLED 0x00000002 |
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| #define | TIMING_MARKER 0x00000004 |
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| #define | FORCED 0x00000008 |
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| #define | RX_BUS_MASTER_COMPLETE 0x00000010 |
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| #define | TX_BUS_MASTER_COMPLETE 0x00000020 |
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| #define | ABR_TX_CELL_COUNT_INT 0x00000040 |
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| #define | DEBUG_INT 0x00000080 |
| |
| #define | MAX_PIO_COUNT 0x000000ff |
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| #define | MAX_TRANSFER_COUNT 0x00001ffc |
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| #define | MASTER_TX_AUTO_APPEND_DESC 0x80000000 |
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| #define | PCR_TIMER_ACCESS 0x0000 |
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| #define | SCR_TIMER_ACCESS 0x0001 |
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| #define | BUCKET_CAPACITY_ACCESS 0x0002 |
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| #define | BUCKET_FULLNESS_ACCESS 0x0003 |
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| #define | RATE_TYPE_ACCESS 0x0004 |
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| #define | TX_CHANNEL_CONFIG_MULT 0x0100 |
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| #define | BUCKET_MAX_SIZE 0x003f |
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| #define | CLOCK_SELECT_SHIFT 4 |
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| #define | CLOCK_DISABLE 0x00ff |
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| #define | IDLE_RATE_TYPE 0x0 |
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| #define | ABR_RATE_TYPE 0x1 |
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| #define | VBR_RATE_TYPE 0x2 |
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| #define | CBR_RATE_TYPE 0x3 |
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| #define | DRVR_DRVRBAR_ENABLE 0x0001 |
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| #define | TXCLK_MUX_SELECT_RCLK 0x0002 |
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| #define | TRANSMIT_TIMING_MARKER 0x0004 |
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| #define | LOOPBACK_TIMING_MARKER 0x0008 |
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| #define | TX_TEST_MODE_16MHz 0x0000 |
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| #define | TX_TEST_MODE_8MHz 0x0010 |
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| #define | TX_TEST_MODE_5_33MHz 0x0020 |
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| #define | TX_TEST_MODE_4MHz 0x0030 |
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| #define | TX_TEST_MODE_3_2MHz 0x0040 |
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| #define | TX_TEST_MODE_2_66MHz 0x0050 |
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| #define | TX_TEST_MODE_2_29MHz 0x0060 |
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| #define | TX_NORMAL_OPERATION 0x0070 |
| |
| #define | ABR_ROUND_ROBIN 0x0080 |
| |
| #define | IDLE_CHANNELS_MASK 0x00FF |
| |
| #define | ABR_CELL_COUNT_REACHED_MULT 0x0100 |
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| #define | ABR_CELL_COUNT_REACHED_MASK 0xFF |
| |
| #define | NON_USER_CELLS_IN_ONE_CHANNEL 0x0008 |
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| #define | RX_ENABLE 0x0010 |
| |
| #define | IGNORE_UNUSED_VPI_VCI_BITS_SET 0x0000 |
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| #define | NON_USER_UNUSED_VPI_VCI_BITS_SET 0x0020 |
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| #define | DISCARD_UNUSED_VPI_VCI_BITS_SET 0x0040 |
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| #define | SIGNAL_LOSS 0x0001 |
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| #define | FREQUENCY_DETECT_ERROR 0x0002 |
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| #define | LOCK_DETECT_ERROR 0x0004 |
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| #define | SELECT_INTERNAL_LOOPBACK 0x0008 |
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| #define | LOCK_DETECT_ENABLE 0x0010 |
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| #define | FREQUENCY_DETECT_ENABLE 0x0020 |
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| #define | USER_FRAQ 0x0040 |
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| #define | GXTALOUT_SELECT_DIV4 0x0080 |
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| #define | GXTALOUT_SELECT_NO_GATING 0x0100 |
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| #define | TIMING_MARKER_RECEIVED 0x0200 |
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| #define | RX_CHANNEL_MASK 0x03FF |
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| #define | FLUSH_CHANNEL 0x4000 |
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| #define | RX_CHANNEL_UPDATE_IN_PROGRESS 0x8000 |
| |
| #define | RX_Q_ENTRY_LENGTH_MASK 0x0000FFFF |
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| #define | RX_Q_ENTRY_CHANNEL_SHIFT 16 |
| |
| #define | SIMONS_DODGEY_MARKER 0x08000000 |
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| #define | RX_CONGESTION_EXPERIENCED 0x10000000 |
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| #define | RX_CRC_10_OK 0x20000000 |
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| #define | RX_CRC_32_OK 0x40000000 |
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| #define | RX_COMPLETE_FRAME 0x80000000 |
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| #define | BUFFER_PTR_MASK 0x0000FFFF |
| |
| #define | RX_INT_THRESHOLD_MULT 0x00010000 |
| |
| #define | RX_INT_THRESHOLD_MASK 0x07FF |
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| #define | INT_EVERY_N_CELLS 0x08000000 |
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| #define | CONGESTION_EXPERIENCED 0x10000000 |
| |
| #define | FIRST_CELL_OF_AAL5_FRAME 0x20000000 |
| |
| #define | CHANNEL_TYPE_AAL5 0x00000000 |
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| #define | CHANNEL_TYPE_RAW_CELLS 0x40000000 |
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| #define | CHANNEL_TYPE_AAL3_4 0x80000000 |
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| #define | BUFF_STATUS_MASK 0x00030000 |
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| #define | BUFF_STATUS_EMPTY 0x00000000 |
| |
| #define | BUFF_STATUS_CELL_AV 0x00010000 |
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| #define | BUFF_STATUS_LAST_CELL_AV 0x00020000 |
| |
| #define | RX_CHANNEL_DISABLED 0x00000000 |
| |
| #define | RX_CHANNEL_IDLE 0x00000001 |
| |
| #define | INITIAL_CRC 0xFFFFFFFF |
| |
| #define | TX_CHANS 8 |
| |
| #define | RX_CHANS 1024 |
| |
| #define | RX_QS 1024 |
| |
| #define | MAX_VCS RX_CHANS |
| |
| #define | BUFN1_SIZE 118 |
| |
| #define | BUFN2_SIZE 124 |
| |
| #define | BUFN3_SIZE 192 |
| |
| #define | BUFN4_SIZE 1408 |
| |
| #define | memmap ((MEMMAP *)0) |
| |
| #define | BUF_PTR(cbptr) ((cbptr) - (cell_buf *) 0) |
| |
| #define | INTERESTING_INTERRUPTS (RX_DATA_AV | RX_DISABLED | TX_BUS_MASTER_COMPLETE | RX_BUS_MASTER_COMPLETE) |
| |
| #define | TX_AAL5_LIMIT (190*ATM_CELL_PAYLOAD-ATM_AAL5_TRAILER) |
| |
| #define | RX_AAL5_LIMIT ATM_MAX_AAL5_PDU |
| |
| #define | DW(x) do{ x } while(0) |
| |
| #define | HRZ_DEV(atm_dev) ((hrz_dev *) (atm_dev)->dev_data) |
| |
| #define | HRZ_VCC(atm_vcc) ((hrz_vcc *) (atm_vcc)->dev_data) |
| |
| #define | YELLOW_LED DEBUG_BIT_0 |
| |
| #define | GREEN_LED DEBUG_BIT_1 |
| |
| #define | YELLOW_LED_OE DEBUG_BIT_0_OE |
| |
| #define | GREEN_LED_OE DEBUG_BIT_1_OE |
| |
| #define | GREEN_LED_OFF(dev) wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | GREEN_LED) |
| |
| #define | GREEN_LED_ON(dev) wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ GREEN_LED) |
| |
| #define | YELLOW_LED_OFF(dev) wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | YELLOW_LED) |
| |
| #define | YELLOW_LED_ON(dev) wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ YELLOW_LED) |
| |
1.8.2