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hpc3.h File Reference
#include <linux/types.h>
#include <asm/page.h>

Go to the source code of this file.

Data Structures

struct  hpc_dma_desc
 
struct  hpc3_pbus_dmacregs
 
struct  hpc3_scsiregs
 
struct  hpc3_ethregs
 
struct  hpc3_regs
 

Macros

#define HPCDMA_EOX   0x80000000 /* last desc in chain for tx */
 
#define HPCDMA_EOR   0x80000000 /* last desc in chain for rx */
 
#define HPCDMA_EOXP   0x40000000 /* end of packet for tx */
 
#define HPCDMA_EORP   0x40000000 /* end of packet for rx */
 
#define HPCDMA_XIE   0x20000000 /* irq generated when at end of this desc */
 
#define HPCDMA_XIU   0x01000000 /* Tx buffer in use by CPU. */
 
#define HPCDMA_EIPC   0x00ff0000 /* SEEQ ethernet special xternal bytecount */
 
#define HPCDMA_ETXD   0x00008000 /* set to one by HPC when packet tx'd */
 
#define HPCDMA_OWN   0x00004000 /* Denotes ring buffer ownership on rx */
 
#define HPCDMA_BCNT   0x00003fff /* size in bytes of this dma buffer */
 
#define HPC3_PDMACTRL_INT   0x00000001 /* interrupt (cleared after read) */
 
#define HPC3_PDMACTRL_ISACT   0x00000002 /* channel active */
 
#define HPC3_PDMACTRL_SEL   0x00000002 /* little endian transfer */
 
#define HPC3_PDMACTRL_RCV   0x00000004 /* direction is receive */
 
#define HPC3_PDMACTRL_FLSH   0x00000008 /* enable flush for receive DMA */
 
#define HPC3_PDMACTRL_ACT   0x00000010 /* start dma transfer */
 
#define HPC3_PDMACTRL_LD   0x00000020 /* load enable for ACT */
 
#define HPC3_PDMACTRL_RT   0x00000040 /* Use realtime GIO bus servicing */
 
#define HPC3_PDMACTRL_HW   0x0000ff00 /* DMA High-water mark */
 
#define HPC3_PDMACTRL_FB   0x003f0000 /* Ptr to beginning of fifo */
 
#define HPC3_PDMACTRL_FE   0x3f000000 /* Ptr to end of fifo */
 
#define HPC3_SBCD_BCNTMSK   0x00003fff /* bytes to transfer from/to memory */
 
#define HPC3_SBCD_XIE   0x00004000 /* Send IRQ when done with cur buf */
 
#define HPC3_SBCD_EOX   0x00008000 /* Indicates this is last buf in chain */
 
#define HPC3_SCTRL_IRQ   0x01 /* IRQ asserted, either dma done or parity */
 
#define HPC3_SCTRL_ENDIAN   0x02 /* DMA endian mode, 0=big 1=little */
 
#define HPC3_SCTRL_DIR   0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
 
#define HPC3_SCTRL_FLUSH   0x08 /* Tells HPC3 to flush scsi fifos */
 
#define HPC3_SCTRL_ACTIVE   0x10 /* SCSI DMA channel is active */
 
#define HPC3_SCTRL_AMASK   0x20 /* DMA active inhibits PIO */
 
#define HPC3_SCTRL_CRESET   0x40 /* Resets dma channel and external controller */
 
#define HPC3_SCTRL_PERR   0x80 /* Bad parity on HPC3 iface to scsi controller */
 
#define HPC3_SDCFG_HCLK   0x00001 /* Enable DMA half clock mode */
 
#define HPC3_SDCFG_D1   0x00006 /* Cycles to spend in D1 state */
 
#define HPC3_SDCFG_D2   0x00038 /* Cycles to spend in D2 state */
 
#define HPC3_SDCFG_D3   0x001c0 /* Cycles to spend in D3 state */
 
#define HPC3_SDCFG_HWAT   0x00e00 /* DMA high water mark */
 
#define HPC3_SDCFG_HW   0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
 
#define HPC3_SDCFG_SWAP   0x02000 /* Byte swap all DMA accesses */
 
#define HPC3_SDCFG_EPAR   0x04000 /* Enable parity checking for DMA */
 
#define HPC3_SDCFG_POLL   0x08000 /* hd_dreq polarity control */
 
#define HPC3_SDCFG_ERLY   0x30000 /* hd_dreq behavior control bits */
 
#define HPC3_SPCFG_P3   0x0003 /* Cycles to spend in P3 state */
 
#define HPC3_SPCFG_P2W   0x001c /* Cycles to spend in P2 state for writes */
 
#define HPC3_SPCFG_P2R   0x01e0 /* Cycles to spend in P2 state for reads */
 
#define HPC3_SPCFG_P1   0x0e00 /* Cycles to spend in P1 state */
 
#define HPC3_SPCFG_HW   0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
 
#define HPC3_SPCFG_SWAP   0x2000 /* Byte swap all PIO accesses */
 
#define HPC3_SPCFG_EPAR   0x4000 /* Enable parity checking for PIO */
 
#define HPC3_SPCFG_FUJI   0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
 
#define HPC3_ERXBCD_BCNTMSK   0x00003fff /* bytes to be sent to memory */
 
#define HPC3_ERXBCD_XIE   0x20000000 /* HPC3 interrupts cpu at end of this buf */
 
#define HPC3_ERXBCD_EOX   0x80000000 /* flags this as end of descriptor chain */
 
#define HPC3_ERXCTRL_STAT50   0x0000003f /* Receive status reg bits of Seeq8003 */
 
#define HPC3_ERXCTRL_STAT6   0x00000040 /* Rdonly irq status */
 
#define HPC3_ERXCTRL_STAT7   0x00000080 /* Rdonlt old/new status bit from Seeq */
 
#define HPC3_ERXCTRL_ENDIAN   0x00000100 /* Endian for dma channel, little=1 big=0 */
 
#define HPC3_ERXCTRL_ACTIVE   0x00000200 /* Tells if DMA transfer is in progress */
 
#define HPC3_ERXCTRL_AMASK   0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
 
#define HPC3_ERXCTRL_RBO   0x00000800 /* Receive buffer overflow if set to 1 */
 
#define HPC3_ERST_CRESET   0x1 /* Reset dma channel and external controller */
 
#define HPC3_ERST_CLRIRQ   0x2 /* Clear channel interrupt */
 
#define HPC3_ERST_LBACK   0x4 /* Enable diagnostic loopback mode of Seeq8003 */
 
#define HPC3_EDCFG_D1   0x0000f /* Cycles to spend in D1 state for PIO */
 
#define HPC3_EDCFG_D2   0x000f0 /* Cycles to spend in D2 state for PIO */
 
#define HPC3_EDCFG_D3   0x00f00 /* Cycles to spend in D3 state for PIO */
 
#define HPC3_EDCFG_WCTRL   0x01000 /* Enable writes of desc into ex ctrl port */
 
#define HPC3_EDCFG_FRXDC   0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
 
#define HPC3_EDCFG_FEOP   0x04000 /* Bad packet marker timeout enable */
 
#define HPC3_EDCFG_FIRQ   0x08000 /* Another bad packet timeout enable */
 
#define HPC3_EDCFG_PTO   0x30000 /* Programmed timeout value for above two */
 
#define HPC3_EPCFG_P1   0x000f /* Cycles to spend in P1 state for PIO */
 
#define HPC3_EPCFG_P2   0x00f0 /* Cycles to spend in P2 state for PIO */
 
#define HPC3_EPCFG_P3   0x0f00 /* Cycles to spend in P3 state for PIO */
 
#define HPC3_EPCFG_TST   0x1000 /* Diagnistic ram test feature bit */
 
#define HPC3_ETXBCD_BCNTMSK   0x00003fff /* bytes to be read from memory */
 
#define HPC3_ETXBCD_ESAMP   0x10000000 /* if set, too late to add descriptor */
 
#define HPC3_ETXBCD_XIE   0x20000000 /* Interrupt cpu at end of cur desc */
 
#define HPC3_ETXBCD_EOP   0x40000000 /* Last byte of cur buf is end of packet */
 
#define HPC3_ETXBCD_EOX   0x80000000 /* This buf is the end of desc chain */
 
#define HPC3_ETXCTRL_STAT30   0x0000000f /* Rdonly copy of seeq tx stat reg */
 
#define HPC3_ETXCTRL_STAT4   0x00000010 /* Indicate late collision occurred */
 
#define HPC3_ETXCTRL_STAT75   0x000000e0 /* Rdonly irq status from seeq */
 
#define HPC3_ETXCTRL_ENDIAN   0x00000100 /* DMA channel endian mode, 1=little 0=big */
 
#define HPC3_ETXCTRL_ACTIVE   0x00000200 /* DMA tx channel is active */
 
#define HPC3_ETXCTRL_AMASK   0x00000400 /* Indicates ACTIVE inhibits PIO's */
 
#define HPC3_ISTAT_PBIMASK   0x0ff /* irq bits for pbus devs 0 --> 7 */
 
#define HPC3_ISTAT_SC0MASK   0x100 /* irq bit for scsi channel 0 */
 
#define HPC3_ISTAT_SC1MASK   0x200 /* irq bit for scsi channel 1 */
 
#define HPC3_GIOMISC_ERTIME   0x1 /* Enable external timer real time. */
 
#define HPC3_GIOMISC_DENDIAN   0x2 /* dma descriptor endian, 1=lit 0=big */
 
#define HPC3_EEPROM_EPROT   0x01 /* Protect register enable */
 
#define HPC3_EEPROM_CSEL   0x02 /* Chip select */
 
#define HPC3_EEPROM_ECLK   0x04 /* EEPROM clock */
 
#define HPC3_EEPROM_DATO   0x08 /* Data out */
 
#define HPC3_EEPROM_DATI   0x10 /* Data in */
 
#define HPC3_BESTAT_BLMASK   0x000ff /* Bus lane where bad parity occurred */
 
#define HPC3_BESTAT_CTYPE   0x00100 /* Bus cycle type, 0=PIO 1=DMA */
 
#define HPC3_BESTAT_PIDSHIFT   9
 
#define HPC3_BESTAT_PIDMASK   0x3f700 /* DMA channel parity identifier */
 
#define HPC3_DMACFG_D3R_MASK   0x00000001
 
#define HPC3_DMACFG_D3R_SHIFT   0
 
#define HPC3_DMACFG_D4R_MASK   0x0000001e
 
#define HPC3_DMACFG_D4R_SHIFT   1
 
#define HPC3_DMACFG_D5R_MASK   0x000001e0
 
#define HPC3_DMACFG_D5R_SHIFT   5
 
#define HPC3_DMACFG_D3W_MASK   0x00000200
 
#define HPC3_DMACFG_D3W_SHIFT   9
 
#define HPC3_DMACFG_D4W_MASK   0x00003c00
 
#define HPC3_DMACFG_D4W_SHIFT   10
 
#define HPC3_DMACFG_D5W_MASK   0x0003c000
 
#define HPC3_DMACFG_D5W_SHIFT   14
 
#define HPC3_DMACFG_DS16   0x00040000
 
#define HPC3_DMACFG_EVENHI   0x00080000
 
#define HPC3_DMACFG_RTIME   0x00200000
 
#define HPC3_DMACFG_BURST_MASK   0x07c00000
 
#define HPC3_DMACFG_BURST_SHIFT   22
 
#define HPC3_DMACFG_DRQLIVE   0x08000000
 
#define HPC3_PIOCFG_P2R_MASK   0x00001
 
#define HPC3_PIOCFG_P2R_SHIFT   0
 
#define HPC3_PIOCFG_P3R_MASK   0x0001e
 
#define HPC3_PIOCFG_P3R_SHIFT   1
 
#define HPC3_PIOCFG_P4R_MASK   0x001e0
 
#define HPC3_PIOCFG_P4R_SHIFT   5
 
#define HPC3_PIOCFG_P2W_MASK   0x00200
 
#define HPC3_PIOCFG_P2W_SHIFT   9
 
#define HPC3_PIOCFG_P3W_MASK   0x03c00
 
#define HPC3_PIOCFG_P3W_SHIFT   10
 
#define HPC3_PIOCFG_P4W_MASK   0x3c000
 
#define HPC3_PIOCFG_P4W_SHIFT   14
 
#define HPC3_PIOCFG_DS16   0x40000
 
#define HPC3_PIOCFG_EVENHI   0x80000
 
#define HPC3_PROM_WENAB   0x1 /* Enable writes to the PROM */
 
#define HPC3_PROM_SWAP   0x1 /* invert GIO addr bit to select prom0 or prom1 */
 
#define HPC3_PROM_STAT   0x1 /* General purpose status bit in gout */
 
#define HPC3_CHIP0_BASE   0x1fb80000 /* physical */
 
#define HPC3_CHIP1_BASE   0x1fb00000 /* physical */
 

Functions

void sgihpc_init (void)
 

Variables

struct hpc3_regshpc3c0
 
struct hpc3_regshpc3c1
 

Macro Definition Documentation

#define HPC3_BESTAT_BLMASK   0x000ff /* Bus lane where bad parity occurred */

Definition at line 218 of file hpc3.h.

#define HPC3_BESTAT_CTYPE   0x00100 /* Bus cycle type, 0=PIO 1=DMA */

Definition at line 219 of file hpc3.h.

#define HPC3_BESTAT_PIDMASK   0x3f700 /* DMA channel parity identifier */

Definition at line 221 of file hpc3.h.

#define HPC3_BESTAT_PIDSHIFT   9

Definition at line 220 of file hpc3.h.

#define HPC3_CHIP0_BASE   0x1fb80000 /* physical */

Definition at line 312 of file hpc3.h.

#define HPC3_CHIP1_BASE   0x1fb00000 /* physical */

Definition at line 313 of file hpc3.h.

#define HPC3_DMACFG_BURST_MASK   0x07c00000

Definition at line 261 of file hpc3.h.

#define HPC3_DMACFG_BURST_SHIFT   22

Definition at line 262 of file hpc3.h.

#define HPC3_DMACFG_D3R_MASK   0x00000001

Definition at line 237 of file hpc3.h.

#define HPC3_DMACFG_D3R_SHIFT   0

Definition at line 238 of file hpc3.h.

#define HPC3_DMACFG_D3W_MASK   0x00000200

Definition at line 246 of file hpc3.h.

#define HPC3_DMACFG_D3W_SHIFT   9

Definition at line 247 of file hpc3.h.

#define HPC3_DMACFG_D4R_MASK   0x0000001e

Definition at line 240 of file hpc3.h.

#define HPC3_DMACFG_D4R_SHIFT   1

Definition at line 241 of file hpc3.h.

#define HPC3_DMACFG_D4W_MASK   0x00003c00

Definition at line 249 of file hpc3.h.

#define HPC3_DMACFG_D4W_SHIFT   10

Definition at line 250 of file hpc3.h.

#define HPC3_DMACFG_D5R_MASK   0x000001e0

Definition at line 243 of file hpc3.h.

#define HPC3_DMACFG_D5R_SHIFT   5

Definition at line 244 of file hpc3.h.

#define HPC3_DMACFG_D5W_MASK   0x0003c000

Definition at line 252 of file hpc3.h.

#define HPC3_DMACFG_D5W_SHIFT   14

Definition at line 253 of file hpc3.h.

#define HPC3_DMACFG_DRQLIVE   0x08000000

Definition at line 264 of file hpc3.h.

#define HPC3_DMACFG_DS16   0x00040000

Definition at line 255 of file hpc3.h.

#define HPC3_DMACFG_EVENHI   0x00080000

Definition at line 257 of file hpc3.h.

#define HPC3_DMACFG_RTIME   0x00200000

Definition at line 259 of file hpc3.h.

#define HPC3_EDCFG_D1   0x0000f /* Cycles to spend in D1 state for PIO */

Definition at line 137 of file hpc3.h.

#define HPC3_EDCFG_D2   0x000f0 /* Cycles to spend in D2 state for PIO */

Definition at line 138 of file hpc3.h.

#define HPC3_EDCFG_D3   0x00f00 /* Cycles to spend in D3 state for PIO */

Definition at line 139 of file hpc3.h.

#define HPC3_EDCFG_FEOP   0x04000 /* Bad packet marker timeout enable */

Definition at line 142 of file hpc3.h.

#define HPC3_EDCFG_FIRQ   0x08000 /* Another bad packet timeout enable */

Definition at line 143 of file hpc3.h.

#define HPC3_EDCFG_FRXDC   0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */

Definition at line 141 of file hpc3.h.

#define HPC3_EDCFG_PTO   0x30000 /* Programmed timeout value for above two */

Definition at line 144 of file hpc3.h.

#define HPC3_EDCFG_WCTRL   0x01000 /* Enable writes of desc into ex ctrl port */

Definition at line 140 of file hpc3.h.

#define HPC3_EEPROM_CSEL   0x02 /* Chip select */

Definition at line 211 of file hpc3.h.

#define HPC3_EEPROM_DATI   0x10 /* Data in */

Definition at line 214 of file hpc3.h.

#define HPC3_EEPROM_DATO   0x08 /* Data out */

Definition at line 213 of file hpc3.h.

#define HPC3_EEPROM_ECLK   0x04 /* EEPROM clock */

Definition at line 212 of file hpc3.h.

#define HPC3_EEPROM_EPROT   0x01 /* Protect register enable */

Definition at line 210 of file hpc3.h.

#define HPC3_EPCFG_P1   0x000f /* Cycles to spend in P1 state for PIO */

Definition at line 147 of file hpc3.h.

#define HPC3_EPCFG_P2   0x00f0 /* Cycles to spend in P2 state for PIO */

Definition at line 148 of file hpc3.h.

#define HPC3_EPCFG_P3   0x0f00 /* Cycles to spend in P3 state for PIO */

Definition at line 149 of file hpc3.h.

#define HPC3_EPCFG_TST   0x1000 /* Diagnistic ram test feature bit */

Definition at line 150 of file hpc3.h.

#define HPC3_ERST_CLRIRQ   0x2 /* Clear channel interrupt */

Definition at line 133 of file hpc3.h.

#define HPC3_ERST_CRESET   0x1 /* Reset dma channel and external controller */

Definition at line 132 of file hpc3.h.

#define HPC3_ERST_LBACK   0x4 /* Enable diagnostic loopback mode of Seeq8003 */

Definition at line 134 of file hpc3.h.

#define HPC3_ERXBCD_BCNTMSK   0x00003fff /* bytes to be sent to memory */

Definition at line 115 of file hpc3.h.

#define HPC3_ERXBCD_EOX   0x80000000 /* flags this as end of descriptor chain */

Definition at line 117 of file hpc3.h.

#define HPC3_ERXBCD_XIE   0x20000000 /* HPC3 interrupts cpu at end of this buf */

Definition at line 116 of file hpc3.h.

#define HPC3_ERXCTRL_ACTIVE   0x00000200 /* Tells if DMA transfer is in progress */

Definition at line 124 of file hpc3.h.

#define HPC3_ERXCTRL_AMASK   0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */

Definition at line 125 of file hpc3.h.

#define HPC3_ERXCTRL_ENDIAN   0x00000100 /* Endian for dma channel, little=1 big=0 */

Definition at line 123 of file hpc3.h.

#define HPC3_ERXCTRL_RBO   0x00000800 /* Receive buffer overflow if set to 1 */

Definition at line 126 of file hpc3.h.

#define HPC3_ERXCTRL_STAT50   0x0000003f /* Receive status reg bits of Seeq8003 */

Definition at line 120 of file hpc3.h.

#define HPC3_ERXCTRL_STAT6   0x00000040 /* Rdonly irq status */

Definition at line 121 of file hpc3.h.

#define HPC3_ERXCTRL_STAT7   0x00000080 /* Rdonlt old/new status bit from Seeq */

Definition at line 122 of file hpc3.h.

#define HPC3_ETXBCD_BCNTMSK   0x00003fff /* bytes to be read from memory */

Definition at line 159 of file hpc3.h.

#define HPC3_ETXBCD_EOP   0x40000000 /* Last byte of cur buf is end of packet */

Definition at line 162 of file hpc3.h.

#define HPC3_ETXBCD_EOX   0x80000000 /* This buf is the end of desc chain */

Definition at line 163 of file hpc3.h.

#define HPC3_ETXBCD_ESAMP   0x10000000 /* if set, too late to add descriptor */

Definition at line 160 of file hpc3.h.

#define HPC3_ETXBCD_XIE   0x20000000 /* Interrupt cpu at end of cur desc */

Definition at line 161 of file hpc3.h.

#define HPC3_ETXCTRL_ACTIVE   0x00000200 /* DMA tx channel is active */

Definition at line 170 of file hpc3.h.

#define HPC3_ETXCTRL_AMASK   0x00000400 /* Indicates ACTIVE inhibits PIO's */

Definition at line 171 of file hpc3.h.

#define HPC3_ETXCTRL_ENDIAN   0x00000100 /* DMA channel endian mode, 1=little 0=big */

Definition at line 169 of file hpc3.h.

#define HPC3_ETXCTRL_STAT30   0x0000000f /* Rdonly copy of seeq tx stat reg */

Definition at line 166 of file hpc3.h.

#define HPC3_ETXCTRL_STAT4   0x00000010 /* Indicate late collision occurred */

Definition at line 167 of file hpc3.h.

#define HPC3_ETXCTRL_STAT75   0x000000e0 /* Rdonly irq status from seeq */

Definition at line 168 of file hpc3.h.

#define HPC3_GIOMISC_DENDIAN   0x2 /* dma descriptor endian, 1=lit 0=big */

Definition at line 207 of file hpc3.h.

#define HPC3_GIOMISC_ERTIME   0x1 /* Enable external timer real time. */

Definition at line 206 of file hpc3.h.

#define HPC3_ISTAT_PBIMASK   0x0ff /* irq bits for pbus devs 0 --> 7 */

Definition at line 201 of file hpc3.h.

#define HPC3_ISTAT_SC0MASK   0x100 /* irq bit for scsi channel 0 */

Definition at line 202 of file hpc3.h.

#define HPC3_ISTAT_SC1MASK   0x200 /* irq bit for scsi channel 1 */

Definition at line 203 of file hpc3.h.

#define HPC3_PDMACTRL_ACT   0x00000010 /* start dma transfer */

Definition at line 51 of file hpc3.h.

#define HPC3_PDMACTRL_FB   0x003f0000 /* Ptr to beginning of fifo */

Definition at line 55 of file hpc3.h.

#define HPC3_PDMACTRL_FE   0x3f000000 /* Ptr to end of fifo */

Definition at line 56 of file hpc3.h.

#define HPC3_PDMACTRL_FLSH   0x00000008 /* enable flush for receive DMA */

Definition at line 50 of file hpc3.h.

#define HPC3_PDMACTRL_HW   0x0000ff00 /* DMA High-water mark */

Definition at line 54 of file hpc3.h.

#define HPC3_PDMACTRL_INT   0x00000001 /* interrupt (cleared after read) */

Definition at line 45 of file hpc3.h.

#define HPC3_PDMACTRL_ISACT   0x00000002 /* channel active */

Definition at line 46 of file hpc3.h.

#define HPC3_PDMACTRL_LD   0x00000020 /* load enable for ACT */

Definition at line 52 of file hpc3.h.

#define HPC3_PDMACTRL_RCV   0x00000004 /* direction is receive */

Definition at line 49 of file hpc3.h.

#define HPC3_PDMACTRL_RT   0x00000040 /* Use realtime GIO bus servicing */

Definition at line 53 of file hpc3.h.

#define HPC3_PDMACTRL_SEL   0x00000002 /* little endian transfer */

Definition at line 48 of file hpc3.h.

#define HPC3_PIOCFG_DS16   0x40000

Definition at line 285 of file hpc3.h.

#define HPC3_PIOCFG_EVENHI   0x80000

Definition at line 287 of file hpc3.h.

#define HPC3_PIOCFG_P2R_MASK   0x00001

Definition at line 267 of file hpc3.h.

#define HPC3_PIOCFG_P2R_SHIFT   0

Definition at line 268 of file hpc3.h.

#define HPC3_PIOCFG_P2W_MASK   0x00200

Definition at line 276 of file hpc3.h.

#define HPC3_PIOCFG_P2W_SHIFT   9

Definition at line 277 of file hpc3.h.

#define HPC3_PIOCFG_P3R_MASK   0x0001e

Definition at line 270 of file hpc3.h.

#define HPC3_PIOCFG_P3R_SHIFT   1

Definition at line 271 of file hpc3.h.

#define HPC3_PIOCFG_P3W_MASK   0x03c00

Definition at line 279 of file hpc3.h.

#define HPC3_PIOCFG_P3W_SHIFT   10

Definition at line 280 of file hpc3.h.

#define HPC3_PIOCFG_P4R_MASK   0x001e0

Definition at line 273 of file hpc3.h.

#define HPC3_PIOCFG_P4R_SHIFT   5

Definition at line 274 of file hpc3.h.

#define HPC3_PIOCFG_P4W_MASK   0x3c000

Definition at line 282 of file hpc3.h.

#define HPC3_PIOCFG_P4W_SHIFT   14

Definition at line 283 of file hpc3.h.

#define HPC3_PROM_STAT   0x1 /* General purpose status bit in gout */

Definition at line 299 of file hpc3.h.

#define HPC3_PROM_SWAP   0x1 /* invert GIO addr bit to select prom0 or prom1 */

Definition at line 295 of file hpc3.h.

#define HPC3_PROM_WENAB   0x1 /* Enable writes to the PROM */

Definition at line 291 of file hpc3.h.

#define HPC3_SBCD_BCNTMSK   0x00003fff /* bytes to transfer from/to memory */

Definition at line 67 of file hpc3.h.

#define HPC3_SBCD_EOX   0x00008000 /* Indicates this is last buf in chain */

Definition at line 69 of file hpc3.h.

#define HPC3_SBCD_XIE   0x00004000 /* Send IRQ when done with cur buf */

Definition at line 68 of file hpc3.h.

#define HPC3_SCTRL_ACTIVE   0x10 /* SCSI DMA channel is active */

Definition at line 76 of file hpc3.h.

#define HPC3_SCTRL_AMASK   0x20 /* DMA active inhibits PIO */

Definition at line 77 of file hpc3.h.

#define HPC3_SCTRL_CRESET   0x40 /* Resets dma channel and external controller */

Definition at line 78 of file hpc3.h.

#define HPC3_SCTRL_DIR   0x04 /* DMA direction, 1=dev2mem 0=mem2dev */

Definition at line 74 of file hpc3.h.

#define HPC3_SCTRL_ENDIAN   0x02 /* DMA endian mode, 0=big 1=little */

Definition at line 73 of file hpc3.h.

#define HPC3_SCTRL_FLUSH   0x08 /* Tells HPC3 to flush scsi fifos */

Definition at line 75 of file hpc3.h.

#define HPC3_SCTRL_IRQ   0x01 /* IRQ asserted, either dma done or parity */

Definition at line 72 of file hpc3.h.

#define HPC3_SCTRL_PERR   0x80 /* Bad parity on HPC3 iface to scsi controller */

Definition at line 79 of file hpc3.h.

#define HPC3_SDCFG_D1   0x00006 /* Cycles to spend in D1 state */

Definition at line 85 of file hpc3.h.

#define HPC3_SDCFG_D2   0x00038 /* Cycles to spend in D2 state */

Definition at line 86 of file hpc3.h.

#define HPC3_SDCFG_D3   0x001c0 /* Cycles to spend in D3 state */

Definition at line 87 of file hpc3.h.

#define HPC3_SDCFG_EPAR   0x04000 /* Enable parity checking for DMA */

Definition at line 91 of file hpc3.h.

#define HPC3_SDCFG_ERLY   0x30000 /* hd_dreq behavior control bits */

Definition at line 93 of file hpc3.h.

#define HPC3_SDCFG_HCLK   0x00001 /* Enable DMA half clock mode */

Definition at line 84 of file hpc3.h.

#define HPC3_SDCFG_HW   0x01000 /* Enable 16-bit halfword DMA accesses to scsi */

Definition at line 89 of file hpc3.h.

#define HPC3_SDCFG_HWAT   0x00e00 /* DMA high water mark */

Definition at line 88 of file hpc3.h.

#define HPC3_SDCFG_POLL   0x08000 /* hd_dreq polarity control */

Definition at line 92 of file hpc3.h.

#define HPC3_SDCFG_SWAP   0x02000 /* Byte swap all DMA accesses */

Definition at line 90 of file hpc3.h.

#define HPC3_SPCFG_EPAR   0x4000 /* Enable parity checking for PIO */

Definition at line 102 of file hpc3.h.

#define HPC3_SPCFG_FUJI   0x8000 /* Fujitsu scsi controller mode for faster dma/pio */

Definition at line 103 of file hpc3.h.

#define HPC3_SPCFG_HW   0x1000 /* Enable 16-bit halfword PIO accesses to scsi */

Definition at line 100 of file hpc3.h.

#define HPC3_SPCFG_P1   0x0e00 /* Cycles to spend in P1 state */

Definition at line 99 of file hpc3.h.

#define HPC3_SPCFG_P2R   0x01e0 /* Cycles to spend in P2 state for reads */

Definition at line 98 of file hpc3.h.

#define HPC3_SPCFG_P2W   0x001c /* Cycles to spend in P2 state for writes */

Definition at line 97 of file hpc3.h.

#define HPC3_SPCFG_P3   0x0003 /* Cycles to spend in P3 state */

Definition at line 96 of file hpc3.h.

#define HPC3_SPCFG_SWAP   0x2000 /* Byte swap all PIO accesses */

Definition at line 101 of file hpc3.h.

#define HPCDMA_BCNT   0x00003fff /* size in bytes of this dma buffer */

Definition at line 31 of file hpc3.h.

#define HPCDMA_EIPC   0x00ff0000 /* SEEQ ethernet special xternal bytecount */

Definition at line 28 of file hpc3.h.

#define HPCDMA_EOR   0x80000000 /* last desc in chain for rx */

Definition at line 23 of file hpc3.h.

#define HPCDMA_EORP   0x40000000 /* end of packet for rx */

Definition at line 25 of file hpc3.h.

#define HPCDMA_EOX   0x80000000 /* last desc in chain for tx */

Definition at line 22 of file hpc3.h.

#define HPCDMA_EOXP   0x40000000 /* end of packet for tx */

Definition at line 24 of file hpc3.h.

#define HPCDMA_ETXD   0x00008000 /* set to one by HPC when packet tx'd */

Definition at line 29 of file hpc3.h.

#define HPCDMA_OWN   0x00004000 /* Denotes ring buffer ownership on rx */

Definition at line 30 of file hpc3.h.

#define HPCDMA_XIE   0x20000000 /* irq generated when at end of this desc */

Definition at line 26 of file hpc3.h.

#define HPCDMA_XIU   0x01000000 /* Tx buffer in use by CPU. */

Definition at line 27 of file hpc3.h.

Function Documentation

void sgihpc_init ( void  )

Definition at line 31 of file ip22-hpc.c.

Variable Documentation

struct hpc3_regs* hpc3c0

Definition at line 17 of file ip22-hpc.c.

struct hpc3_regs * hpc3c1

Definition at line 17 of file ip22-hpc.c.