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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Go to the source code of this file.
Data Structures | |
| struct | i2c_algo_iop3xx_data |
Macros | |
| #define | IOP3XX_ICR_FAST_MODE 0x8000 /* 1=400kBps, 0=100kBps */ |
| #define | IOP3XX_ICR_UNIT_RESET 0x4000 /* 1=RESET */ |
| #define | IOP3XX_ICR_SAD_IE 0x2000 /* 1=Slave Detect Interrupt Enable */ |
| #define | IOP3XX_ICR_ALD_IE 0x1000 /* 1=Arb Loss Detect Interrupt Enable */ |
| #define | IOP3XX_ICR_SSD_IE 0x0800 /* 1=Slave STOP Detect Interrupt Enable */ |
| #define | IOP3XX_ICR_BERR_IE 0x0400 /* 1=Bus Error Interrupt Enable */ |
| #define | IOP3XX_ICR_RXFULL_IE 0x0200 /* 1=Receive Full Interrupt Enable */ |
| #define | IOP3XX_ICR_TXEMPTY_IE 0x0100 /* 1=Transmit Empty Interrupt Enable */ |
| #define | IOP3XX_ICR_GCD 0x0080 /* 1=General Call Disable */ |
| #define | IOP3XX_ICR_UE 0x0040 /* 1=Unit Enable */ |
| #define | IOP3XX_ICR_SCLEN 0x0020 /* 1=SCL enable for master mode */ |
| #define | IOP3XX_ICR_MABORT |
| #define | IOP3XX_ICR_TBYTE 0x0008 /* 1=Send/Receive a byte. i2c clears */ |
| #define | IOP3XX_ICR_NACK 0x0004 /* 1=reply with NACK */ |
| #define | IOP3XX_ICR_MSTOP 0x0002 /* 1=send a STOP after next data byte */ |
| #define | IOP3XX_ICR_MSTART 0x0001 /* 1=initiate a START */ |
| #define | IOP3XX_ISR_BERRD 0x0400 /* 1=BUS ERROR Detected */ |
| #define | IOP3XX_ISR_SAD 0x0200 /* 1=Slave ADdress Detected */ |
| #define | IOP3XX_ISR_GCAD 0x0100 /* 1=General Call Address Detected */ |
| #define | IOP3XX_ISR_RXFULL 0x0080 /* 1=Receive Full */ |
| #define | IOP3XX_ISR_TXEMPTY 0x0040 /* 1=Transmit Empty */ |
| #define | IOP3XX_ISR_ALD 0x0020 /* 1=Arbitration Loss Detected */ |
| #define | IOP3XX_ISR_SSD 0x0010 /* 1=Slave STOP Detected */ |
| #define | IOP3XX_ISR_BBUSY 0x0008 /* 1=Bus BUSY */ |
| #define | IOP3XX_ISR_UNITBUSY 0x0004 /* 1=Unit Busy */ |
| #define | IOP3XX_ISR_NACK 0x0002 /* 1=Unit Rx or Tx a NACK */ |
| #define | IOP3XX_ISR_RXREAD 0x0001 /* 1=READ 0=WRITE (R/W bit of slave addr */ |
| #define | IOP3XX_ISR_CLEARBITS 0x07f0 |
| #define | IOP3XX_ISAR_SAMASK 0x007f |
| #define | IOP3XX_IDBR_MASK 0x00ff |
| #define | IOP3XX_IBMR_SCL 0x0002 |
| #define | IOP3XX_IBMR_SDA 0x0001 |
| #define | IOP3XX_GPOD_I2C0 0x00c0 /* clear these bits to enable ch0 */ |
| #define | IOP3XX_GPOD_I2C1 0x0030 /* clear these bits to enable ch1 */ |
| #define | MYSAR 0 /* default slave address */ |
| #define | I2C_ERR 321 |
| #define | I2C_ERR_BERR (I2C_ERR+0) |
| #define | I2C_ERR_ALD (I2C_ERR+1) |
| #define | CR_OFFSET 0 |
| #define | SR_OFFSET 0x4 |
| #define | SAR_OFFSET 0x8 |
| #define | DBR_OFFSET 0xc |
| #define | CCR_OFFSET 0x10 |
| #define | BMR_OFFSET 0x14 |
| #define | IOP3XX_I2C_IO_SIZE 0x18 |
| #define BMR_OFFSET 0x14 |
Definition at line 94 of file i2c-iop3xx.h.
| #define CCR_OFFSET 0x10 |
Definition at line 93 of file i2c-iop3xx.h.
| #define CR_OFFSET 0 |
Definition at line 89 of file i2c-iop3xx.h.
| #define DBR_OFFSET 0xc |
Definition at line 92 of file i2c-iop3xx.h.
| #define I2C_ERR 321 |
Definition at line 84 of file i2c-iop3xx.h.
| #define I2C_ERR_ALD (I2C_ERR+1) |
Definition at line 86 of file i2c-iop3xx.h.
| #define I2C_ERR_BERR (I2C_ERR+0) |
Definition at line 85 of file i2c-iop3xx.h.
| #define IOP3XX_GPOD_I2C0 0x00c0 /* clear these bits to enable ch0 */ |
Definition at line 79 of file i2c-iop3xx.h.
| #define IOP3XX_GPOD_I2C1 0x0030 /* clear these bits to enable ch1 */ |
Definition at line 80 of file i2c-iop3xx.h.
| #define IOP3XX_I2C_IO_SIZE 0x18 |
Definition at line 96 of file i2c-iop3xx.h.
| #define IOP3XX_IBMR_SCL 0x0002 |
Definition at line 76 of file i2c-iop3xx.h.
| #define IOP3XX_IBMR_SDA 0x0001 |
Definition at line 77 of file i2c-iop3xx.h.
| #define IOP3XX_ICR_ALD_IE 0x1000 /* 1=Arb Loss Detect Interrupt Enable */ |
Definition at line 31 of file i2c-iop3xx.h.
| #define IOP3XX_ICR_BERR_IE 0x0400 /* 1=Bus Error Interrupt Enable */ |
Definition at line 33 of file i2c-iop3xx.h.
| #define IOP3XX_ICR_FAST_MODE 0x8000 /* 1=400kBps, 0=100kBps */ |
Definition at line 28 of file i2c-iop3xx.h.
| #define IOP3XX_ICR_GCD 0x0080 /* 1=General Call Disable */ |
Definition at line 36 of file i2c-iop3xx.h.
| #define IOP3XX_ICR_MABORT |
Definition at line 51 of file i2c-iop3xx.h.
| #define IOP3XX_ICR_MSTART 0x0001 /* 1=initiate a START */ |
Definition at line 55 of file i2c-iop3xx.h.
| #define IOP3XX_ICR_MSTOP 0x0002 /* 1=send a STOP after next data byte */ |
Definition at line 54 of file i2c-iop3xx.h.
| #define IOP3XX_ICR_NACK 0x0004 /* 1=reply with NACK */ |
Definition at line 53 of file i2c-iop3xx.h.
| #define IOP3XX_ICR_RXFULL_IE 0x0200 /* 1=Receive Full Interrupt Enable */ |
Definition at line 34 of file i2c-iop3xx.h.
| #define IOP3XX_ICR_SAD_IE 0x2000 /* 1=Slave Detect Interrupt Enable */ |
Definition at line 30 of file i2c-iop3xx.h.
| #define IOP3XX_ICR_SCLEN 0x0020 /* 1=SCL enable for master mode */ |
Definition at line 50 of file i2c-iop3xx.h.
| #define IOP3XX_ICR_SSD_IE 0x0800 /* 1=Slave STOP Detect Interrupt Enable */ |
Definition at line 32 of file i2c-iop3xx.h.
| #define IOP3XX_ICR_TBYTE 0x0008 /* 1=Send/Receive a byte. i2c clears */ |
Definition at line 52 of file i2c-iop3xx.h.
| #define IOP3XX_ICR_TXEMPTY_IE 0x0100 /* 1=Transmit Empty Interrupt Enable */ |
Definition at line 35 of file i2c-iop3xx.h.
| #define IOP3XX_ICR_UE 0x0040 /* 1=Unit Enable */ |
Definition at line 41 of file i2c-iop3xx.h.
| #define IOP3XX_ICR_UNIT_RESET 0x4000 /* 1=RESET */ |
Definition at line 29 of file i2c-iop3xx.h.
| #define IOP3XX_IDBR_MASK 0x00ff |
Definition at line 74 of file i2c-iop3xx.h.
| #define IOP3XX_ISAR_SAMASK 0x007f |
Definition at line 72 of file i2c-iop3xx.h.
| #define IOP3XX_ISR_ALD 0x0020 /* 1=Arbitration Loss Detected */ |
Definition at line 63 of file i2c-iop3xx.h.
| #define IOP3XX_ISR_BBUSY 0x0008 /* 1=Bus BUSY */ |
Definition at line 65 of file i2c-iop3xx.h.
| #define IOP3XX_ISR_BERRD 0x0400 /* 1=BUS ERROR Detected */ |
Definition at line 58 of file i2c-iop3xx.h.
| #define IOP3XX_ISR_CLEARBITS 0x07f0 |
Definition at line 70 of file i2c-iop3xx.h.
| #define IOP3XX_ISR_GCAD 0x0100 /* 1=General Call Address Detected */ |
Definition at line 60 of file i2c-iop3xx.h.
| #define IOP3XX_ISR_NACK 0x0002 /* 1=Unit Rx or Tx a NACK */ |
Definition at line 67 of file i2c-iop3xx.h.
| #define IOP3XX_ISR_RXFULL 0x0080 /* 1=Receive Full */ |
Definition at line 61 of file i2c-iop3xx.h.
| #define IOP3XX_ISR_RXREAD 0x0001 /* 1=READ 0=WRITE (R/W bit of slave addr */ |
Definition at line 68 of file i2c-iop3xx.h.
| #define IOP3XX_ISR_SAD 0x0200 /* 1=Slave ADdress Detected */ |
Definition at line 59 of file i2c-iop3xx.h.
| #define IOP3XX_ISR_SSD 0x0010 /* 1=Slave STOP Detected */ |
Definition at line 64 of file i2c-iop3xx.h.
| #define IOP3XX_ISR_TXEMPTY 0x0040 /* 1=Transmit Empty */ |
Definition at line 62 of file i2c-iop3xx.h.
| #define IOP3XX_ISR_UNITBUSY 0x0004 /* 1=Unit Busy */ |
Definition at line 66 of file i2c-iop3xx.h.
Definition at line 82 of file i2c-iop3xx.h.
| #define SAR_OFFSET 0x8 |
Definition at line 91 of file i2c-iop3xx.h.
| #define SR_OFFSET 0x4 |
Definition at line 90 of file i2c-iop3xx.h.
1.8.2