#include <linux/slab.h>

Data Structures
struct	bufferDMA

Macros
#define	TRUE (1)

#define	FALSE (0)

#define	S626_SIZE 0x0200

#define	DMABUF_SIZE 4096 /* 4k pages */

#define	S626_ADC_CHANNELS 16

#define	S626_DAC_CHANNELS 4

#define	S626_ENCODER_CHANNELS 6

#define	S626_DIO_CHANNELS 48

#define	S626_DIO_BANKS 3 /* Number of DIO groups. */

#define	S626_DIO_EXTCHANS 40 /* Number of */

#define	NUM_TRIMDACS 12 /* Number of valid TrimDAC channels. */

#define	INTEL 1 /* Intel bus type. */

#define	MOTOROLA 2 /* Motorola bus type. */

#define	PLATFORM INTEL /* * SELECT PLATFORM TYPE * */

#define	RANGE_5V 0x10 /* +/-5V range */

#define	RANGE_10V 0x00 /* +/-10V range */

#define	EOPL 0x80 /* End of ADC poll list marker. */

#define	GSEL_BIPOLAR5V 0x00F0 /* LP_GSEL setting for 5V bipolar range. */

#define	GSEL_BIPOLAR10V 0x00A0 /* LP_GSEL setting for 10V bipolar range. */

#define	ERR_ILLEGAL_PARM 0x00010000 /* Illegal function parameter value was specified. */

#define	ERR_I2C 0x00020000 /* I2C error. */

#define	ERR_COUNTERSETUP 0x00200000 /* Illegal setup specified for counter channel. */

#define	ERR_DEBI_TIMEOUT 0x00400000 /* DEBI transfer timed out. */

#define	ADC_DMABUF_DWORDS 40 /* ADC DMA buffer must hold 16 samples, plus pre/post garbage samples. */

#define	DAC_WDMABUF_DWORDS 1 /* DAC output DMA buffer holds a single sample. */

#define	DAC_WDMABUF_OS ADC_DMABUF_DWORDS

#define	IRQ_GPIO3 0x00000040 /* IRQ enable for GPIO3. */

#define	IRQ_RPS1 0x10000000

#define	ISR_AFOU 0x00000800

#define	IRQ_COINT1A 0x0400 /* conter 1A overflow interrupt mask */

#define	IRQ_COINT1B 0x0800 /* conter 1B overflow interrupt mask */

#define	IRQ_COINT2A 0x1000 /* conter 2A overflow interrupt mask */

#define	IRQ_COINT2B 0x2000 /* conter 2B overflow interrupt mask */

#define	IRQ_COINT3A 0x4000 /* conter 3A overflow interrupt mask */

#define	IRQ_COINT3B 0x8000 /* conter 3B overflow interrupt mask */

#define	RPS_CLRSIGNAL 0x00000000 /* CLEAR SIGNAL */

#define	RPS_SETSIGNAL 0x10000000 /* SET SIGNAL */

#define	RPS_NOP 0x00000000 /* NOP */

#define	RPS_PAUSE 0x20000000 /* PAUSE */

#define	RPS_UPLOAD 0x40000000 /* UPLOAD */

#define	RPS_JUMP 0x80000000 /* JUMP */

#define	RPS_LDREG 0x90000100 /* LDREG (1 uint32_t only) */

#define	RPS_STREG 0xA0000100 /* STREG (1 uint32_t only) */

#define	RPS_STOP 0x50000000 /* STOP */

#define	RPS_IRQ 0x60000000 /* IRQ */

#define	RPS_LOGICAL_OR 0x08000000 /* Logical OR conditionals. */

#define	RPS_INVERT 0x04000000 /* Test for negated semaphores. */

#define	RPS_DEBI 0x00000002 /* DEBI done */

#define	RPS_SIG0 0x00200000 /* RPS semaphore 0 (used by ADC). */

#define	RPS_SIG1 0x00400000 /* RPS semaphore 1 (used by DAC). */

#define	RPS_SIG2 0x00800000 /* RPS semaphore 2 (not used). */

#define	RPS_GPIO2 0x00080000 /* RPS GPIO2 */

#define	RPS_GPIO3 0x00100000 /* RPS GPIO3 */

#define	RPS_SIGADC RPS_SIG0 /* Trigger/status for ADC's RPS program. */

#define	RPS_SIGDAC RPS_SIG1 /* Trigger/status for DAC's RPS program. */

#define	RPSCLK_SCALAR 8 /* This is apparent ratio of PCI/RPS clks (undocumented!!). */

#define	RPSCLK_PER_US (33 / RPSCLK_SCALAR) /* Number of RPS clocks in one microsecond. */

#define	SBA_RPS_A0 0x27 /* Time of RPS0 busy, in PCI clocks. */

#define	GPIO_BASE 0x10004000 /* GPIO 0,2,3 = inputs, GPIO3 = IRQ; GPIO1 = out. */

#define	GPIO1_LO 0x00000000 /* GPIO1 set to LOW. */

#define	GPIO1_HI 0x00001000 /* GPIO1 set to HIGH. */

#define	PSR_DEBI_E 0x00040000 /* DEBI event flag. */

#define	PSR_DEBI_S 0x00080000 /* DEBI status flag. */

#define	PSR_A2_IN 0x00008000 /* Audio output DMA2 protection address reached. */

#define	PSR_AFOU 0x00000800 /* Audio FIFO under/overflow detected. */

#define	PSR_GPIO2 0x00000020 /* GPIO2 input pin: 0=AdcBusy, 1=AdcIdle. */

#define	PSR_EC0S 0x00000001 /* Event counter 0 threshold reached. */

#define	SSR_AF2_OUT 0x00000200 /* Audio 2 output FIFO under/overflow detected. */

#define	MC1_SOFT_RESET 0x80000000 /* Invoke 7146 soft reset. */

#define	MC1_SHUTDOWN 0x3FFF0000 /* Shut down all MC1-controlled enables. */

#define	MC1_ERPS1 0x2000 /* enab/disable RPS task 1. */

#define	MC1_ERPS0 0x1000 /* enab/disable RPS task 0. */

#define	MC1_DEBI 0x0800 /* enab/disable DEBI pins. */

#define	MC1_AUDIO 0x0200 /* enab/disable audio port pins. */

#define	MC1_I2C 0x0100 /* enab/disable I2C interface. */

#define	MC1_A2OUT 0x0008 /* enab/disable transfer on A2 out. */

#define	MC1_A2IN 0x0004 /* enab/disable transfer on A2 in. */

#define	MC1_A1IN 0x0001 /* enab/disable transfer on A1 in. */

#define	MC2_UPLD_DEBIq 0x00020002 /* Upload DEBI registers. */

#define	MC2_UPLD_IICq 0x00010001 /* Upload I2C registers. */

#define	MC2_RPSSIG2_ONq 0x20002000 /* Assert RPS_SIG2. */

#define	MC2_RPSSIG1_ONq 0x10001000 /* Assert RPS_SIG1. */

#define	MC2_RPSSIG0_ONq 0x08000800 /* Assert RPS_SIG0. */

#define	MC2_UPLD_DEBI_MASKq 0x00000002 /* Upload DEBI mask. */

#define	MC2_UPLD_IIC_MASKq 0x00000001 /* Upload I2C mask. */

#define	MC2_RPSSIG2_MASKq 0x00002000 /* RPS_SIG2 bit mask. */

#define	MC2_RPSSIG1_MASKq 0x00001000 /* RPS_SIG1 bit mask. */

#define	MC2_RPSSIG0_MASKq 0x00000800 /* RPS_SIG0 bit mask. */

#define	MC2_DELAYTRIG_4USq MC2_RPSSIG1_ON

#define	MC2_DELAYBUSY_4USq MC2_RPSSIG1_MASK

#define	MC2_DELAYTRIG_6USq MC2_RPSSIG2_ON

#define	MC2_DELAYBUSY_6USq MC2_RPSSIG2_MASK

#define	MC2_UPLD_DEBI 0x0002 /* Upload DEBI. */

#define	MC2_UPLD_IIC 0x0001 /* Upload I2C. */

#define	MC2_RPSSIG2 0x2000 /* RPS signal 2 (not used). */

#define	MC2_RPSSIG1 0x1000 /* RPS signal 1 (DAC RPS busy). */

#define	MC2_RPSSIG0 0x0800 /* RPS signal 0 (ADC RPS busy). */

#define	MC2_ADC_RPS MC2_RPSSIG0 /* ADC RPS busy. */

#define	MC2_DAC_RPS MC2_RPSSIG1 /* DAC RPS busy. */

#define	MC2_UPLD_DEBIQ 0x00020002 /* Upload DEBI registers. */

#define	MC2_UPLD_IICQ 0x00010001 /* Upload I2C registers. */

#define	P_PCI_BT_A 0x004C /* Audio DMA burst/threshold control. */

#define	P_DEBICFG 0x007C /* DEBI configuration. */

#define	P_DEBICMD 0x0080 /* DEBI command. */

#define	P_DEBIPAGE 0x0084 /* DEBI page. */

#define	P_DEBIAD 0x0088 /* DEBI target address. */

#define	P_I2CCTRL 0x008C /* I2C control. */

#define	P_I2CSTAT 0x0090 /* I2C status. */

#define	P_BASEA2_IN

#define	P_PROTA2_IN

#define	P_PAGEA2_IN 0x00B4 /* Audio input 2 paging attributes. */

#define	P_BASEA2_OUT

#define	P_PROTA2_OUT

#define	P_PAGEA2_OUT 0x00C0 /* Audio output 2 paging attributes. */

#define	P_RPSPAGE0 0x00C4 /* RPS0 page. */

#define	P_RPSPAGE1 0x00C8 /* RPS1 page. */

#define	P_RPS0_TOUT 0x00D4 /* RPS0 time-out. */

#define	P_RPS1_TOUT 0x00D8 /* RPS1 time-out. */

#define	P_IER 0x00DC /* Interrupt enable. */

#define	P_GPIO 0x00E0 /* General-purpose I/O. */

#define	P_EC1SSR 0x00E4 /* Event counter set 1 source select. */

#define	P_ECT1R 0x00EC /* Event counter threshold set 1. */

#define	P_ACON1 0x00F4 /* Audio control 1. */

#define	P_ACON2 0x00F8 /* Audio control 2. */

#define	P_MC1 0x00FC /* Master control 1. */

#define	P_MC2 0x0100 /* Master control 2. */

#define	P_RPSADDR0 0x0104 /* RPS0 instruction pointer. */

#define	P_RPSADDR1 0x0108 /* RPS1 instruction pointer. */

#define	P_ISR 0x010C /* Interrupt status. */

#define	P_PSR 0x0110 /* Primary status. */

#define	P_SSR 0x0114 /* Secondary status. */

#define	P_EC1R 0x0118 /* Event counter set 1. */

#define	P_ADP4

#define	P_FB_BUFFER1 0x0144 /* Audio feedback buffer 1. */

#define	P_FB_BUFFER2 0x0148 /* Audio feedback buffer 2. */

#define	P_TSL1 0x0180 /* Audio time slot list 1. */

#define	P_TSL2 0x01C0 /* Audio time slot list 2. */

#define	LP_DACPOL 0x0082 /* Write DAC polarity. */

#define	LP_GSEL 0x0084 /* Write ADC gain. */

#define	LP_ISEL 0x0086 /* Write ADC channel select. */

#define	LP_WRINTSELA 0x0042 /* Write A interrupt enable. */

#define	LP_WREDGSELA 0x0044 /* Write A edge selection. */

#define	LP_WRCAPSELA 0x0046 /* Write A capture enable. */

#define	LP_WRDOUTA 0x0048 /* Write A digital output. */

#define	LP_WRINTSELB 0x0052 /* Write B interrupt enable. */

#define	LP_WREDGSELB 0x0054 /* Write B edge selection. */

#define	LP_WRCAPSELB 0x0056 /* Write B capture enable. */

#define	LP_WRDOUTB 0x0058 /* Write B digital output. */

#define	LP_WRINTSELC 0x0062 /* Write C interrupt enable. */

#define	LP_WREDGSELC 0x0064 /* Write C edge selection. */

#define	LP_WRCAPSELC 0x0066 /* Write C capture enable. */

#define	LP_WRDOUTC 0x0068 /* Write C digital output. */

#define	LP_RDDINA 0x0040 /* Read digital input. */

#define	LP_RDCAPFLGA 0x0048 /* Read edges captured. */

#define	LP_RDINTSELA 0x004A /* Read interrupt enable register. */

#define	LP_RDEDGSELA 0x004C /* Read edge selection register. */

#define	LP_RDCAPSELA 0x004E /* Read capture enable register. */

#define	LP_RDDINB 0x0050 /* Read digital input. */

#define	LP_RDCAPFLGB 0x0058 /* Read edges captured. */

#define	LP_RDINTSELB 0x005A /* Read interrupt enable register. */

#define	LP_RDEDGSELB 0x005C /* Read edge selection register. */

#define	LP_RDCAPSELB 0x005E /* Read capture enable register. */

#define	LP_RDDINC 0x0060 /* Read digital input. */

#define	LP_RDCAPFLGC 0x0068 /* Read edges captured. */

#define	LP_RDINTSELC 0x006A /* Read interrupt enable register. */

#define	LP_RDEDGSELC 0x006C /* Read edge selection register. */

#define	LP_RDCAPSELC 0x006E /* Read capture enable register. */

#define	LP_CR0A 0x0000 /* 0A setup register. */

#define	LP_CR0B 0x0002 /* 0B setup register. */

#define	LP_CR1A 0x0004 /* 1A setup register. */

#define	LP_CR1B 0x0006 /* 1B setup register. */

#define	LP_CR2A 0x0008 /* 2A setup register. */

#define	LP_CR2B 0x000A /* 2B setup register. */

#define	LP_CNTR0ALSW 0x000C /* 0A lsw. */

#define	LP_CNTR0AMSW 0x000E /* 0A msw. */

#define	LP_CNTR0BLSW 0x0010 /* 0B lsw. */

#define	LP_CNTR0BMSW 0x0012 /* 0B msw. */

#define	LP_CNTR1ALSW 0x0014 /* 1A lsw. */

#define	LP_CNTR1AMSW 0x0016 /* 1A msw. */

#define	LP_CNTR1BLSW 0x0018 /* 1B lsw. */

#define	LP_CNTR1BMSW 0x001A /* 1B msw. */

#define	LP_CNTR2ALSW 0x001C /* 2A lsw. */

#define	LP_CNTR2AMSW 0x001E /* 2A msw. */

#define	LP_CNTR2BLSW 0x0020 /* 2B lsw. */

#define	LP_CNTR2BMSW 0x0022 /* 2B msw. */

#define	LP_MISC1 0x0088 /* Read/write Misc1. */

#define	LP_WRMISC2 0x0090 /* Write Misc2. */

#define	LP_RDMISC2 0x0082 /* Read Misc2. */

#define	MISC1_WENABLE

#define	MISC1_WDISABLE 0x0000 /* Disable writes to MISC2. */

#define	MISC1_EDCAP

#define	MISC1_NOEDCAP

#define	RDMISC1_WDTIMEOUT 0x4000 /* Watchdog timer timed out. */

#define	WRMISC2_WDCLEAR 0x8000 /* Reset watchdog timer to zero. */

#define	WRMISC2_CHARGE_ENABLE 0x4000 /* enab battery trickle charging. */

#define	MISC2_BATT_ENABLE 0x0008 /* Backup battery enable. */

#define	MISC2_WDENABLE 0x0004 /* Watchdog timer enable. */

#define	MISC2_WDPERIOD_MASK 0x0003 /* Watchdog interval */

#define	A2_RUN 0x40000000 /* Run A2 based on TSL2. */

#define	A1_RUN 0x20000000 /* Run A1 based on TSL1. */

#define	A1_SWAP 0x00200000 /* Use big-endian for A1. */

#define	A2_SWAP 0x00100000 /* Use big-endian for A2. */

#define	WS_MODES 0x00019999 /* WS0 = TSL1 trigger */

#define	ACON1_BASE (WS_MODES \| A1_RUN)

#define	ACON1_ADCSTART

#define	ACON1_DACSTART (ACON1_BASE \| A2_RUN)

#define	ACON1_DACSTOP ACON1_BASE /* Halt A2. */

#define	A1_CLKSRC_BCLK1 0x00000000 /* A1 bit rate = BCLK1 (ADC). */

#define	A2_CLKSRC_X1 0x00800000 /* A2 bit rate = ACLK/1 (DACs). */

#define	A2_CLKSRC_X2 0x00C00000 /* A2 bit rate = ACLK/2 (DACs). */

#define	A2_CLKSRC_X4 0x01400000 /* A2 bit rate = ACLK/4 (DACs). */

#define	INVERT_BCLK2 0x00100000 /* Invert BCLK2 (DACs). */

#define	BCLK2_OE 0x00040000 /* enab BCLK2 (DACs). */

#define	ACON2_XORMASK 0x000C0000 /* XOR mask for ACON2 */

#define	ACON2_INIT (ACON2_XORMASK ^ (A1_CLKSRC_BCLK1 \| A2_CLKSRC_X2 \| INVERT_BCLK2 \| BCLK2_OE))

#define	WS1 0x40000000 /* WS output to assert. */

#define	WS2 0x20000000

#define	WS3 0x10000000

#define	WS4 0x08000000

#define	RSD1 0x01000000 /* Shift A1 data in on SD1. */

#define	SDW_A1

#define	SIB_A1

#define	SF_A1

#define	XFIFO_0 0x00000000 /* Data fifo byte 0. */

#define	XFIFO_1 0x00000010 /* Data fifo byte 1. */

#define	XFIFO_2 0x00000020 /* Data fifo byte 2. */

#define	XFIFO_3 0x00000030 /* Data fifo byte 3. */

#define	XFB0 0x00000040 /* FB_BUFFER byte 0. */

#define	XFB1 0x00000050 /* FB_BUFFER byte 1. */

#define	XFB2 0x00000060 /* FB_BUFFER byte 2. */

#define	XFB3 0x00000070 /* FB_BUFFER byte 3. */

#define	SIB_A2

#define	SF_A2

#define	LF_A2

#define	XSD2 0x00000008 /* Shift data out on SD2. */

#define	RSD3 0x00001800 /* Shift data in on SD3. */

#define	RSD2 0x00001000 /* Shift data in on SD2. */

#define	LOW_A2 0x00000002 /* Drive last SD low */

#define	EOS 0x00000001 /* End of superframe. */

#define	I2C_CLKSEL 0x0400

#define	I2C_BITRATE 68.75

#define	I2C_WRTIME 15.0

#define	I2C_RETRIES (I2C_WRTIME * I2C_BITRATE / 9.0)

#define	I2C_ERR 0x0002 /* I2C control/status */

#define	I2C_BUSY 0x0001 /* I2C control/status */

#define	I2C_ABORT 0x0080 /* I2C status flag ABORT. */

#define	I2C_ATTRSTART 0x3 /* I2C attribute START. */

#define	I2C_ATTRCONT 0x2 /* I2C attribute CONT. */

#define	I2C_ATTRSTOP 0x1 /* I2C attribute STOP. */

#define	I2C_ATTRNOP 0x0 /* I2C attribute NOP. */

#define	I2CR (devpriv->I2CAdrs \| 1)

#define	I2CW (devpriv->I2CAdrs)

#define	I2C_B2(ATTR, VAL) (((ATTR) << 6) \| ((VAL) << 24))

#define	I2C_B1(ATTR, VAL) (((ATTR) << 4) \| ((VAL) << 16))

#define	I2C_B0(ATTR, VAL) (((ATTR) << 2) \| ((VAL) << 8))

#define	P_DEBICFGq 0x007C /* DEBI configuration. */

#define	P_DEBICMDq 0x0080 /* DEBI command. */

#define	P_DEBIPAGEq 0x0084 /* DEBI page. */

#define	P_DEBIADq 0x0088 /* DEBI target address. */

#define	DEBI_CFG_TOQ 0x03C00000 /* timeout (15 PCI cycles) */

#define	DEBI_CFG_FASTQ 0x10000000 /* fast mode enable */

#define	DEBI_CFG_16Q 0x00080000 /* 16-bit access enable */

#define	DEBI_CFG_INCQ 0x00040000 /* enable address increment */

#define	DEBI_CFG_TIMEROFFQ 0x00010000 /* disable timer */

#define	DEBI_CMD_RDQ 0x00050000 /* read immediate 2 bytes */

#define	DEBI_CMD_WRQ 0x00040000 /* write immediate 2 bytes */

#define	DEBI_PAGE_DISABLEQ 0x00000000 /* paging disable */

#define	DEBI_CMD_SIZE16 (2 << 17) /* Transfer size is */

#define	DEBI_CMD_READ 0x00010000 /* Read operation. */

#define	DEBI_CMD_WRITE 0x00000000 /* Write operation. */

#define	DEBI_CMD_RDWORD (DEBI_CMD_READ \| DEBI_CMD_SIZE16)

#define	DEBI_CMD_WRWORD (DEBI_CMD_WRITE \| DEBI_CMD_SIZE16)

#define	DEBI_CFG_XIRQ_EN 0x80000000 /* enab external */

#define	DEBI_CFG_XRESUME 0x40000000 /* Resume block */

#define	DEBI_CFG_FAST 0x10000000 /* Fast mode enable. */

#define	DEBI_CFG_TOUT_BIT 22 /* Finish DEBI cycle after */

#define	DEBI_CFG_SWAP_NONE 0x00000000 /* Straight - don't */

#define	DEBI_CFG_SWAP_2 0x00100000 /* 2-byte swap (Motorola). */

#define	DEBI_CFG_SWAP_4 0x00200000 /* 4-byte swap. */

#define	DEBI_CFG_16 0x00080000 /* Slave is able to */

#define	DEBI_CFG_SLAVE16 0x00080000 /* Slave is able to */

#define	DEBI_CFG_INC 0x00040000 /* enab address */

#define	DEBI_CFG_INTEL 0x00020000 /* Intel style local bus. */

#define	DEBI_CFG_TIMEROFF 0x00010000 /* Disable timer. */

#define	DEBI_TOUT 7 /* Wait 7 PCI clocks */

#define	DEBI_SWAP DEBI_CFG_SWAP_NONE

#define	DEBI_PAGE_DISABLE 0x00000000 /* Paging disable. */

#define	LOADSRC_INDX 0 /* Preload core in response to */

#define	LOADSRC_OVER 1 /* Preload core in response to */

#define	LOADSRCB_OVERA 2 /* Preload B core in response */

#define	LOADSRC_NONE 3 /* Never preload core. */

#define	INTSRC_NONE 0 /* Interrupts disabled. */

#define	INTSRC_OVER 1 /* Interrupt on Overflow. */

#define	INTSRC_INDX 2 /* Interrupt on Index. */

#define	INTSRC_BOTH 3 /* Interrupt on Index or Overflow. */

#define	LATCHSRC_AB_READ 0 /* Latch on read. */

#define	LATCHSRC_A_INDXA 1 /* Latch A on A Index. */

#define	LATCHSRC_B_INDXB 2 /* Latch B on B Index. */

#define	LATCHSRC_B_OVERA 3 /* Latch B on A Overflow. */

#define	INDXSRC_HARD 0 /* Hardware or software index. */

#define	INDXSRC_SOFT 1 /* Software index only. */

#define	INDXPOL_POS 0 /* Index input is active high. */

#define	INDXPOL_NEG 1 /* Index input is active low. */

#define	CLKSRC_COUNTER 0 /* Counter mode. */

#define	CLKSRC_TIMER 2 /* Timer mode. */

#define	CLKSRC_EXTENDER 3 /* Extender mode. */

#define	CLKPOL_POS 0 /* Counter/Extender clock is */

#define	CLKPOL_NEG 1 /* Counter/Extender clock is */

#define	CNTDIR_UP 0 /* Timer counts up. */

#define	CNTDIR_DOWN 1 /* Timer counts down. */

#define	CLKENAB_ALWAYS 0 /* Clock always enabled. */

#define	CLKENAB_INDEX 1 /* Clock is enabled by index. */

#define	CLKMULT_4X 0 /* 4x clock multiplier. */

#define	CLKMULT_2X 1 /* 2x clock multiplier. */

#define	CLKMULT_1X 2 /* 1x clock multiplier. */

#define	BF_LOADSRC 9 /* Preload trigger. */

#define	BF_INDXSRC 7 /* Index source. */

#define	BF_INDXPOL 6 /* Index polarity. */

#define	BF_CLKSRC 4 /* Clock source. */

#define	BF_CLKPOL 3 /* Clock polarity/count direction. */

#define	BF_CLKMULT 1 /* Clock multiplier. */

#define	BF_CLKENAB 0 /* Clock enable. */

#define	CLKSRC_COUNTER 0 /* Counter: ENC_C clock, ENC_D */

#define	CLKSRC_TIMER 2 /* Timer: SYS_C clock, */

#define	CLKSRC_EXTENDER 3 /* Extender: OVR_A clock, */

#define	MULT_X0 0x0003 /* Supports no multipliers; */

#define	MULT_X1 0x0002 /* Supports multiplier x1; */

#define	MULT_X2 0x0001 /* Supports multipliers x1, */

#define	MULT_X4 0x0000 /* Supports multipliers x1, */

#define	NUM_COUNTERS 6 /* Maximum valid counter */

#define	NUM_INTSOURCES 4

#define	NUM_LATCHSOURCES 4

#define	NUM_CLKMULTS 4

#define	NUM_CLKSOURCES 4

#define	NUM_CLKPOLS 2

#define	NUM_INDEXPOLS 2

#define	NUM_INDEXSOURCES 2

#define	NUM_LOADTRIGS 4

#define	CRABIT_INDXSRC_B 14 /* B index source. */

#define	CRABIT_CLKSRC_B 12 /* B clock source. */

#define	CRABIT_INDXPOL_A 11 /* A index polarity. */

#define	CRABIT_LOADSRC_A 9 /* A preload trigger. */

#define	CRABIT_CLKMULT_A 7 /* A clock multiplier. */

#define	CRABIT_INTSRC_A 5 /* A interrupt source. */

#define	CRABIT_CLKPOL_A 4 /* A clock polarity. */

#define	CRABIT_INDXSRC_A 2 /* A index source. */

#define	CRABIT_CLKSRC_A 0 /* A clock source. */

#define	CRBBIT_INTRESETCMD 15 /* Interrupt reset command. */

#define	CRBBIT_INTRESET_B 14 /* B interrupt reset enable. */

#define	CRBBIT_INTRESET_A 13 /* A interrupt reset enable. */

#define	CRBBIT_CLKENAB_A 12 /* A clock enable. */

#define	CRBBIT_INTSRC_B 10 /* B interrupt source. */

#define	CRBBIT_LATCHSRC 8 /* A/B latch source. */

#define	CRBBIT_LOADSRC_B 6 /* B preload trigger. */

#define	CRBBIT_CLKMULT_B 3 /* B clock multiplier. */

#define	CRBBIT_CLKENAB_B 2 /* B clock enable. */

#define	CRBBIT_INDXPOL_B 1 /* B index polarity. */

#define	CRBBIT_CLKPOL_B 0 /* B clock polarity. */

#define	CRAMSK_INDXSRC_B ((uint16_t)(3 << CRABIT_INDXSRC_B))

#define	CRAMSK_CLKSRC_B ((uint16_t)(3 << CRABIT_CLKSRC_B))

#define	CRAMSK_INDXPOL_A ((uint16_t)(1 << CRABIT_INDXPOL_A))

#define	CRAMSK_LOADSRC_A ((uint16_t)(3 << CRABIT_LOADSRC_A))

#define	CRAMSK_CLKMULT_A ((uint16_t)(3 << CRABIT_CLKMULT_A))

#define	CRAMSK_INTSRC_A ((uint16_t)(3 << CRABIT_INTSRC_A))

#define	CRAMSK_CLKPOL_A ((uint16_t)(3 << CRABIT_CLKPOL_A))

#define	CRAMSK_INDXSRC_A ((uint16_t)(3 << CRABIT_INDXSRC_A))

#define	CRAMSK_CLKSRC_A ((uint16_t)(3 << CRABIT_CLKSRC_A))

#define	CRBMSK_INTRESETCMD ((uint16_t)(1 << CRBBIT_INTRESETCMD))

#define	CRBMSK_INTRESET_B ((uint16_t)(1 << CRBBIT_INTRESET_B))

#define	CRBMSK_INTRESET_A ((uint16_t)(1 << CRBBIT_INTRESET_A))

#define	CRBMSK_CLKENAB_A ((uint16_t)(1 << CRBBIT_CLKENAB_A))

#define	CRBMSK_INTSRC_B ((uint16_t)(3 << CRBBIT_INTSRC_B))

#define	CRBMSK_LATCHSRC ((uint16_t)(3 << CRBBIT_LATCHSRC))

#define	CRBMSK_LOADSRC_B ((uint16_t)(3 << CRBBIT_LOADSRC_B))

#define	CRBMSK_CLKMULT_B ((uint16_t)(3 << CRBBIT_CLKMULT_B))

#define	CRBMSK_CLKENAB_B ((uint16_t)(1 << CRBBIT_CLKENAB_B))

#define	CRBMSK_INDXPOL_B ((uint16_t)(1 << CRBBIT_INDXPOL_B))

#define	CRBMSK_CLKPOL_B ((uint16_t)(1 << CRBBIT_CLKPOL_B))

#define	CRBMSK_INTCTRL (CRBMSK_INTRESETCMD \| CRBMSK_INTRESET_A \| CRBMSK_INTRESET_B) /* Interrupt reset control bits. */

#define	STDBIT_INTSRC 13

#define	STDBIT_LATCHSRC 11

#define	STDBIT_LOADSRC 9

#define	STDBIT_INDXSRC 7

#define	STDBIT_INDXPOL 6

#define	STDBIT_CLKSRC 4

#define	STDBIT_CLKPOL 3

#define	STDBIT_CLKMULT 1

#define	STDBIT_CLKENAB 0

#define	STDMSK_INTSRC ((uint16_t)(3 << STDBIT_INTSRC))

#define	STDMSK_LATCHSRC ((uint16_t)(3 << STDBIT_LATCHSRC))

#define	STDMSK_LOADSRC ((uint16_t)(3 << STDBIT_LOADSRC))

#define	STDMSK_INDXSRC ((uint16_t)(1 << STDBIT_INDXSRC))

#define	STDMSK_INDXPOL ((uint16_t)(1 << STDBIT_INDXPOL))

#define	STDMSK_CLKSRC ((uint16_t)(3 << STDBIT_CLKSRC))

#define	STDMSK_CLKPOL ((uint16_t)(1 << STDBIT_CLKPOL))

#define	STDMSK_CLKMULT ((uint16_t)(3 << STDBIT_CLKMULT))

#define	STDMSK_CLKENAB ((uint16_t)(1 << STDBIT_CLKENAB))

Macro Definition Documentation

#define A1_CLKSRC_BCLK1 0x00000000 /* A1 bit rate = BCLK1 (ADC). */

Definition at line 364 of file s626.h.

#define A1_RUN 0x20000000 /* Run A1 based on TSL1. */

Definition at line 344 of file s626.h.

#define A1_SWAP 0x00200000 /* Use big-endian for A1. */

Definition at line 345 of file s626.h.

#define A2_CLKSRC_X1 0x00800000 /* A2 bit rate = ACLK/1 (DACs). */

Definition at line 365 of file s626.h.

#define A2_CLKSRC_X2 0x00C00000 /* A2 bit rate = ACLK/2 (DACs). */

Definition at line 366 of file s626.h.

#define A2_CLKSRC_X4 0x01400000 /* A2 bit rate = ACLK/4 (DACs). */

Definition at line 367 of file s626.h.

#define A2_RUN 0x40000000 /* Run A2 based on TSL2. */

Definition at line 343 of file s626.h.

#define A2_SWAP 0x00100000 /* Use big-endian for A2. */

Definition at line 346 of file s626.h.

#define ACON1_ADCSTART

Value:

ACON1_BASE /* Start ADC: run A1

* based on TSL1. */

Definition at line 358 of file s626.h.

#define ACON1_BASE (WS_MODES | A1_RUN)

Definition at line 353 of file s626.h.

#define ACON1_DACSTART (ACON1_BASE | A2_RUN)

Definition at line 359 of file s626.h.

#define ACON1_DACSTOP ACON1_BASE /* Halt A2. */

Definition at line 361 of file s626.h.

#define ACON2_INIT (ACON2_XORMASK ^ (A1_CLKSRC_BCLK1 | A2_CLKSRC_X2 | INVERT_BCLK2 | BCLK2_OE))

Definition at line 373 of file s626.h.

#define ACON2_XORMASK 0x000C0000 /* XOR mask for ACON2 */

Definition at line 370 of file s626.h.

#define ADC_DMABUF_DWORDS 40 /* ADC DMA buffer must hold 16 samples, plus pre/post garbage samples. */

Definition at line 109 of file s626.h.

#define BCLK2_OE 0x00040000 /* enab BCLK2 (DACs). */

Definition at line 369 of file s626.h.

#define BF_CLKENAB 0 /* Clock enable. */

Definition at line 578 of file s626.h.

#define BF_CLKMULT 1 /* Clock multiplier. */

Definition at line 577 of file s626.h.

#define BF_CLKPOL 3 /* Clock polarity/count direction. */

Definition at line 576 of file s626.h.

#define BF_CLKSRC 4 /* Clock source. */

Definition at line 575 of file s626.h.

#define BF_INDXPOL 6 /* Index polarity. */

Definition at line 574 of file s626.h.

#define BF_INDXSRC 7 /* Index source. */

Definition at line 573 of file s626.h.

#define BF_LOADSRC 9 /* Preload trigger. */

Definition at line 572 of file s626.h.

#define CLKENAB_ALWAYS 0 /* Clock always enabled. */

Definition at line 563 of file s626.h.

#define CLKENAB_INDEX 1 /* Clock is enabled by index. */

Definition at line 564 of file s626.h.

#define CLKMULT_1X 2 /* 1x clock multiplier. */

Definition at line 569 of file s626.h.

#define CLKMULT_2X 1 /* 2x clock multiplier. */

Definition at line 568 of file s626.h.

#define CLKMULT_4X 0 /* 4x clock multiplier. */

Definition at line 567 of file s626.h.

#define CLKPOL_NEG 1 /* Counter/Extender clock is */

Definition at line 557 of file s626.h.

#define CLKPOL_POS 0 /* Counter/Extender clock is */

Definition at line 555 of file s626.h.

#define CLKSRC_COUNTER 0 /* Counter mode. */

Definition at line 583 of file s626.h.

#define CLKSRC_COUNTER 0 /* Counter: ENC_C clock, ENC_D */

Definition at line 583 of file s626.h.

#define CLKSRC_EXTENDER 3 /* Extender mode. */

Definition at line 588 of file s626.h.

#define CLKSRC_EXTENDER 3 /* Extender: OVR_A clock, */

Definition at line 588 of file s626.h.

#define CLKSRC_TIMER 2 /* Timer mode. */

Definition at line 585 of file s626.h.

#define CLKSRC_TIMER 2 /* Timer: SYS_C clock, */

Definition at line 585 of file s626.h.

#define CNTDIR_DOWN 1 /* Timer counts down. */

Definition at line 560 of file s626.h.

#define CNTDIR_UP 0 /* Timer counts up. */

Definition at line 559 of file s626.h.

#define CRABIT_CLKMULT_A 7 /* A clock multiplier. */

Definition at line 626 of file s626.h.

#define CRABIT_CLKPOL_A 4 /* A clock polarity. */

Definition at line 628 of file s626.h.

#define CRABIT_CLKSRC_A 0 /* A clock source. */

Definition at line 630 of file s626.h.

#define CRABIT_CLKSRC_B 12 /* B clock source. */

Definition at line 623 of file s626.h.

#define CRABIT_INDXPOL_A 11 /* A index polarity. */

Definition at line 624 of file s626.h.

#define CRABIT_INDXSRC_A 2 /* A index source. */

Definition at line 629 of file s626.h.

#define CRABIT_INDXSRC_B 14 /* B index source. */

Definition at line 622 of file s626.h.

#define CRABIT_INTSRC_A 5 /* A interrupt source. */

Definition at line 627 of file s626.h.

#define CRABIT_LOADSRC_A 9 /* A preload trigger. */

Definition at line 625 of file s626.h.

#define CRAMSK_CLKMULT_A ((uint16_t)(3 << CRABIT_CLKMULT_A))

Definition at line 651 of file s626.h.

#define CRAMSK_CLKPOL_A ((uint16_t)(3 << CRABIT_CLKPOL_A))

Definition at line 653 of file s626.h.

#define CRAMSK_CLKSRC_A ((uint16_t)(3 << CRABIT_CLKSRC_A))

Definition at line 655 of file s626.h.

#define CRAMSK_CLKSRC_B ((uint16_t)(3 << CRABIT_CLKSRC_B))

Definition at line 648 of file s626.h.

#define CRAMSK_INDXPOL_A ((uint16_t)(1 << CRABIT_INDXPOL_A))

Definition at line 649 of file s626.h.

#define CRAMSK_INDXSRC_A ((uint16_t)(3 << CRABIT_INDXSRC_A))

Definition at line 654 of file s626.h.

#define CRAMSK_INDXSRC_B ((uint16_t)(3 << CRABIT_INDXSRC_B))

Definition at line 647 of file s626.h.

#define CRAMSK_INTSRC_A ((uint16_t)(3 << CRABIT_INTSRC_A))

Definition at line 652 of file s626.h.

#define CRAMSK_LOADSRC_A ((uint16_t)(3 << CRABIT_LOADSRC_A))

Definition at line 650 of file s626.h.

#define CRBBIT_CLKENAB_A 12 /* A clock enable. */

Definition at line 636 of file s626.h.

#define CRBBIT_CLKENAB_B 2 /* B clock enable. */

Definition at line 641 of file s626.h.

#define CRBBIT_CLKMULT_B 3 /* B clock multiplier. */

Definition at line 640 of file s626.h.

#define CRBBIT_CLKPOL_B 0 /* B clock polarity. */

Definition at line 643 of file s626.h.

#define CRBBIT_INDXPOL_B 1 /* B index polarity. */

Definition at line 642 of file s626.h.

#define CRBBIT_INTRESET_A 13 /* A interrupt reset enable. */

Definition at line 635 of file s626.h.

#define CRBBIT_INTRESET_B 14 /* B interrupt reset enable. */

Definition at line 634 of file s626.h.

#define CRBBIT_INTRESETCMD 15 /* Interrupt reset command. */

Definition at line 633 of file s626.h.

#define CRBBIT_INTSRC_B 10 /* B interrupt source. */

Definition at line 637 of file s626.h.

#define CRBBIT_LATCHSRC 8 /* A/B latch source. */

Definition at line 638 of file s626.h.

#define CRBBIT_LOADSRC_B 6 /* B preload trigger. */

Definition at line 639 of file s626.h.

#define CRBMSK_CLKENAB_A ((uint16_t)(1 << CRBBIT_CLKENAB_A))

Definition at line 660 of file s626.h.

#define CRBMSK_CLKENAB_B ((uint16_t)(1 << CRBBIT_CLKENAB_B))

Definition at line 665 of file s626.h.

#define CRBMSK_CLKMULT_B ((uint16_t)(3 << CRBBIT_CLKMULT_B))

Definition at line 664 of file s626.h.

#define CRBMSK_CLKPOL_B ((uint16_t)(1 << CRBBIT_CLKPOL_B))

Definition at line 667 of file s626.h.

#define CRBMSK_INDXPOL_B ((uint16_t)(1 << CRBBIT_INDXPOL_B))

Definition at line 666 of file s626.h.

#define CRBMSK_INTCTRL (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A | CRBMSK_INTRESET_B) /* Interrupt reset control bits. */

Definition at line 669 of file s626.h.

#define CRBMSK_INTRESET_A ((uint16_t)(1 << CRBBIT_INTRESET_A))

Definition at line 659 of file s626.h.

#define CRBMSK_INTRESET_B ((uint16_t)(1 << CRBBIT_INTRESET_B))

Definition at line 658 of file s626.h.

#define CRBMSK_INTRESETCMD ((uint16_t)(1 << CRBBIT_INTRESETCMD))

Definition at line 657 of file s626.h.

#define CRBMSK_INTSRC_B ((uint16_t)(3 << CRBBIT_INTSRC_B))

Definition at line 661 of file s626.h.

#define CRBMSK_LATCHSRC ((uint16_t)(3 << CRBBIT_LATCHSRC))

Definition at line 662 of file s626.h.

#define CRBMSK_LOADSRC_B ((uint16_t)(3 << CRBBIT_LOADSRC_B))

Definition at line 663 of file s626.h.

#define DAC_WDMABUF_DWORDS 1 /* DAC output DMA buffer holds a single sample. */

Definition at line 110 of file s626.h.

#define DAC_WDMABUF_OS ADC_DMABUF_DWORDS

Definition at line 115 of file s626.h.

#define DEBI_CFG_16 0x00080000 /* Slave is able to */

Definition at line 485 of file s626.h.

#define DEBI_CFG_16Q 0x00080000 /* 16-bit access enable */

Definition at line 448 of file s626.h.

#define DEBI_CFG_FAST 0x10000000 /* Fast mode enable. */

Definition at line 473 of file s626.h.

#define DEBI_CFG_FASTQ 0x10000000 /* fast mode enable */

Definition at line 447 of file s626.h.

#define DEBI_CFG_INC 0x00040000 /* enab address */

Definition at line 492 of file s626.h.

#define DEBI_CFG_INCQ 0x00040000 /* enable address increment */

Definition at line 449 of file s626.h.

#define DEBI_CFG_INTEL 0x00020000 /* Intel style local bus. */

Definition at line 495 of file s626.h.

#define DEBI_CFG_SLAVE16 0x00080000 /* Slave is able to */

Definition at line 489 of file s626.h.

#define DEBI_CFG_SWAP_2 0x00100000 /* 2-byte swap (Motorola). */

Definition at line 483 of file s626.h.

#define DEBI_CFG_SWAP_4 0x00200000 /* 4-byte swap. */

Definition at line 484 of file s626.h.

#define DEBI_CFG_SWAP_NONE 0x00000000 /* Straight - don't */

Definition at line 480 of file s626.h.

#define DEBI_CFG_TIMEROFF 0x00010000 /* Disable timer. */

Definition at line 496 of file s626.h.

#define DEBI_CFG_TIMEROFFQ 0x00010000 /* disable timer */

Definition at line 450 of file s626.h.

#define DEBI_CFG_TOQ 0x03C00000 /* timeout (15 PCI cycles) */

Definition at line 446 of file s626.h.

#define DEBI_CFG_TOUT_BIT 22 /* Finish DEBI cycle after */

Definition at line 476 of file s626.h.

#define DEBI_CFG_XIRQ_EN 0x80000000 /* enab external */

Definition at line 468 of file s626.h.

#define DEBI_CFG_XRESUME 0x40000000 /* Resume block */

Definition at line 470 of file s626.h.

#define DEBI_CMD_RDQ 0x00050000 /* read immediate 2 bytes */

Definition at line 451 of file s626.h.

#define DEBI_CMD_RDWORD (DEBI_CMD_READ | DEBI_CMD_SIZE16)

Definition at line 462 of file s626.h.

#define DEBI_CMD_READ 0x00010000 /* Read operation. */

Definition at line 458 of file s626.h.

#define DEBI_CMD_SIZE16 (2 << 17) /* Transfer size is */

Definition at line 456 of file s626.h.

#define DEBI_CMD_WRITE 0x00000000 /* Write operation. */

Definition at line 459 of file s626.h.

#define DEBI_CMD_WRQ 0x00040000 /* write immediate 2 bytes */

Definition at line 452 of file s626.h.

#define DEBI_CMD_WRWORD (DEBI_CMD_WRITE | DEBI_CMD_SIZE16)

Definition at line 465 of file s626.h.

#define DEBI_PAGE_DISABLE 0x00000000 /* Paging disable. */

Definition at line 516 of file s626.h.

#define DEBI_PAGE_DISABLEQ 0x00000000 /* paging disable */

Definition at line 453 of file s626.h.

#define DEBI_SWAP DEBI_CFG_SWAP_NONE

Definition at line 505 of file s626.h.

#define DEBI_TOUT 7 /* Wait 7 PCI clocks */

Definition at line 500 of file s626.h.

#define DMABUF_SIZE 4096 /* 4k pages */

Definition at line 76 of file s626.h.

#define EOPL 0x80 /* End of ADC poll list marker. */

Definition at line 98 of file s626.h.

#define EOS 0x00000001 /* End of superframe. */

Definition at line 403 of file s626.h.

#define ERR_COUNTERSETUP 0x00200000 /* Illegal setup specified for counter channel. */

Definition at line 105 of file s626.h.

#define ERR_DEBI_TIMEOUT 0x00400000 /* DEBI transfer timed out. */

Definition at line 106 of file s626.h.

#define ERR_I2C 0x00020000 /* I2C error. */

Definition at line 104 of file s626.h.

#define ERR_ILLEGAL_PARM 0x00010000 /* Illegal function parameter value was specified. */

Definition at line 103 of file s626.h.

#define FALSE (0)

Definition at line 70 of file s626.h.

#define GPIO1_HI 0x00001000 /* GPIO1 set to HIGH. */

Definition at line 165 of file s626.h.

#define GPIO1_LO 0x00000000 /* GPIO1 set to LOW. */

Definition at line 164 of file s626.h.

#define GPIO_BASE 0x10004000 /* GPIO 0,2,3 = inputs, GPIO3 = IRQ; GPIO1 = out. */

Definition at line 163 of file s626.h.

#define GSEL_BIPOLAR10V 0x00A0 /* LP_GSEL setting for 10V bipolar range. */

Definition at line 100 of file s626.h.

#define GSEL_BIPOLAR5V 0x00F0 /* LP_GSEL setting for 5V bipolar range. */

Definition at line 99 of file s626.h.

#define I2C_ABORT 0x0080 /* I2C status flag ABORT. */

Definition at line 423 of file s626.h.

#define I2C_ATTRCONT 0x2 /* I2C attribute CONT. */

Definition at line 425 of file s626.h.

#define I2C_ATTRNOP 0x0 /* I2C attribute NOP. */

Definition at line 427 of file s626.h.

#define I2C_ATTRSTART 0x3 /* I2C attribute START. */

Definition at line 424 of file s626.h.

#define I2C_ATTRSTOP 0x1 /* I2C attribute STOP. */

Definition at line 426 of file s626.h.

#define I2C_B0	(	ATTR,
		VAL
	)	(((ATTR) << 2) \| ((VAL) << 8))

Definition at line 438 of file s626.h.

#define I2C_B1	(	ATTR,
		VAL
	)	(((ATTR) << 4) \| ((VAL) << 16))

Definition at line 437 of file s626.h.

#define I2C_B2	(	ATTR,
		VAL
	)	(((ATTR) << 6) \| ((VAL) << 24))

Definition at line 436 of file s626.h.

#define I2C_BITRATE 68.75

Definition at line 409 of file s626.h.

#define I2C_BUSY 0x0001 /* I2C control/status */

Definition at line 421 of file s626.h.

#define I2C_CLKSEL 0x0400

Definition at line 406 of file s626.h.

#define I2C_ERR 0x0002 /* I2C control/status */

Definition at line 419 of file s626.h.

#define I2C_RETRIES (I2C_WRTIME * I2C_BITRATE / 9.0)

Definition at line 418 of file s626.h.

#define I2C_WRTIME 15.0

Definition at line 412 of file s626.h.

#define I2CR (devpriv->I2CAdrs | 1)

Definition at line 430 of file s626.h.

#define I2CW (devpriv->I2CAdrs)

Definition at line 433 of file s626.h.

#define INDXPOL_NEG 1 /* Index input is active low. */

Definition at line 547 of file s626.h.

#define INDXPOL_POS 0 /* Index input is active high. */

Definition at line 546 of file s626.h.

#define INDXSRC_HARD 0 /* Hardware or software index. */

Definition at line 542 of file s626.h.

#define INDXSRC_SOFT 1 /* Software index only. */

Definition at line 543 of file s626.h.

#define INTEL 1 /* Intel bus type. */

Definition at line 90 of file s626.h.

#define INTSRC_BOTH 3 /* Interrupt on Index or Overflow. */

Definition at line 533 of file s626.h.

#define INTSRC_INDX 2 /* Interrupt on Index. */

Definition at line 532 of file s626.h.

#define INTSRC_NONE 0 /* Interrupts disabled. */

Definition at line 530 of file s626.h.

#define INTSRC_OVER 1 /* Interrupt on Overflow. */

Definition at line 531 of file s626.h.

#define INVERT_BCLK2 0x00100000 /* Invert BCLK2 (DACs). */

Definition at line 368 of file s626.h.

#define IRQ_COINT1A 0x0400 /* conter 1A overflow interrupt mask */

Definition at line 123 of file s626.h.

#define IRQ_COINT1B 0x0800 /* conter 1B overflow interrupt mask */

Definition at line 124 of file s626.h.

#define IRQ_COINT2A 0x1000 /* conter 2A overflow interrupt mask */

Definition at line 125 of file s626.h.

#define IRQ_COINT2B 0x2000 /* conter 2B overflow interrupt mask */

Definition at line 126 of file s626.h.

#define IRQ_COINT3A 0x4000 /* conter 3A overflow interrupt mask */

Definition at line 127 of file s626.h.

#define IRQ_COINT3B 0x8000 /* conter 3B overflow interrupt mask */

Definition at line 128 of file s626.h.

#define IRQ_GPIO3 0x00000040 /* IRQ enable for GPIO3. */

Definition at line 118 of file s626.h.

#define IRQ_RPS1 0x10000000

Definition at line 119 of file s626.h.

#define ISR_AFOU 0x00000800

Definition at line 120 of file s626.h.

#define LATCHSRC_A_INDXA 1 /* Latch A on A Index. */

Definition at line 537 of file s626.h.

#define LATCHSRC_AB_READ 0 /* Latch on read. */

Definition at line 536 of file s626.h.

#define LATCHSRC_B_INDXB 2 /* Latch B on B Index. */

Definition at line 538 of file s626.h.

#define LATCHSRC_B_OVERA 3 /* Latch B on A Overflow. */

Definition at line 539 of file s626.h.

#define LF_A2

Value:

0x00000080  /* Load next dword from A2's
                         * output fifo into its
                         * output dword buffer. */

Definition at line 396 of file s626.h.

#define LOADSRC_INDX 0 /* Preload core in response to */

Definition at line 521 of file s626.h.

#define LOADSRC_NONE 3 /* Never preload core. */

Definition at line 527 of file s626.h.

#define LOADSRC_OVER 1 /* Preload core in response to */

Definition at line 523 of file s626.h.

#define LOADSRCB_OVERA 2 /* Preload B core in response */

Definition at line 525 of file s626.h.

#define LOW_A2 0x00000002 /* Drive last SD low */

Definition at line 400 of file s626.h.

#define LP_CNTR0ALSW 0x000C /* 0A lsw. */

Definition at line 305 of file s626.h.

#define LP_CNTR0AMSW 0x000E /* 0A msw. */

Definition at line 306 of file s626.h.

#define LP_CNTR0BLSW 0x0010 /* 0B lsw. */

Definition at line 307 of file s626.h.

#define LP_CNTR0BMSW 0x0012 /* 0B msw. */

Definition at line 308 of file s626.h.

#define LP_CNTR1ALSW 0x0014 /* 1A lsw. */

Definition at line 309 of file s626.h.

#define LP_CNTR1AMSW 0x0016 /* 1A msw. */

Definition at line 310 of file s626.h.

#define LP_CNTR1BLSW 0x0018 /* 1B lsw. */

Definition at line 311 of file s626.h.

#define LP_CNTR1BMSW 0x001A /* 1B msw. */

Definition at line 312 of file s626.h.

#define LP_CNTR2ALSW 0x001C /* 2A lsw. */

Definition at line 313 of file s626.h.

#define LP_CNTR2AMSW 0x001E /* 2A msw. */

Definition at line 314 of file s626.h.

#define LP_CNTR2BLSW 0x0020 /* 2B lsw. */

Definition at line 315 of file s626.h.

#define LP_CNTR2BMSW 0x0022 /* 2B msw. */

Definition at line 316 of file s626.h.

#define LP_CR0A 0x0000 /* 0A setup register. */

Definition at line 297 of file s626.h.

#define LP_CR0B 0x0002 /* 0B setup register. */

Definition at line 298 of file s626.h.

#define LP_CR1A 0x0004 /* 1A setup register. */

Definition at line 299 of file s626.h.

#define LP_CR1B 0x0006 /* 1B setup register. */

Definition at line 300 of file s626.h.

#define LP_CR2A 0x0008 /* 2A setup register. */

Definition at line 301 of file s626.h.

#define LP_CR2B 0x000A /* 2B setup register. */

Definition at line 302 of file s626.h.

#define LP_DACPOL 0x0082 /* Write DAC polarity. */

Definition at line 262 of file s626.h.

#define LP_GSEL 0x0084 /* Write ADC gain. */

Definition at line 263 of file s626.h.

#define LP_ISEL 0x0086 /* Write ADC channel select. */

Definition at line 264 of file s626.h.

#define LP_MISC1 0x0088 /* Read/write Misc1. */

Definition at line 319 of file s626.h.

#define LP_RDCAPFLGA 0x0048 /* Read edges captured. */

Definition at line 281 of file s626.h.

#define LP_RDCAPFLGB 0x0058 /* Read edges captured. */

Definition at line 286 of file s626.h.

#define LP_RDCAPFLGC 0x0068 /* Read edges captured. */

Definition at line 291 of file s626.h.

#define LP_RDCAPSELA 0x004E /* Read capture enable register. */

Definition at line 284 of file s626.h.

#define LP_RDCAPSELB 0x005E /* Read capture enable register. */

Definition at line 289 of file s626.h.

#define LP_RDCAPSELC 0x006E /* Read capture enable register. */

Definition at line 294 of file s626.h.

#define LP_RDDINA 0x0040 /* Read digital input. */

Definition at line 280 of file s626.h.

#define LP_RDDINB 0x0050 /* Read digital input. */

Definition at line 285 of file s626.h.

#define LP_RDDINC 0x0060 /* Read digital input. */

Definition at line 290 of file s626.h.

#define LP_RDEDGSELA 0x004C /* Read edge selection register. */

Definition at line 283 of file s626.h.

#define LP_RDEDGSELB 0x005C /* Read edge selection register. */

Definition at line 288 of file s626.h.

#define LP_RDEDGSELC 0x006C /* Read edge selection register. */

Definition at line 293 of file s626.h.

#define LP_RDINTSELA 0x004A /* Read interrupt enable register. */

Definition at line 282 of file s626.h.

#define LP_RDINTSELB 0x005A /* Read interrupt enable register. */

Definition at line 287 of file s626.h.

#define LP_RDINTSELC 0x006A /* Read interrupt enable register. */

Definition at line 292 of file s626.h.

#define LP_RDMISC2 0x0082 /* Read Misc2. */

Definition at line 321 of file s626.h.

#define LP_WRCAPSELA 0x0046 /* Write A capture enable. */

Definition at line 268 of file s626.h.

#define LP_WRCAPSELB 0x0056 /* Write B capture enable. */

Definition at line 272 of file s626.h.

#define LP_WRCAPSELC 0x0066 /* Write C capture enable. */

Definition at line 276 of file s626.h.

#define LP_WRDOUTA 0x0048 /* Write A digital output. */

Definition at line 269 of file s626.h.

#define LP_WRDOUTB 0x0058 /* Write B digital output. */

Definition at line 273 of file s626.h.

#define LP_WRDOUTC 0x0068 /* Write C digital output. */

Definition at line 277 of file s626.h.

#define LP_WREDGSELA 0x0044 /* Write A edge selection. */

Definition at line 267 of file s626.h.

#define LP_WREDGSELB 0x0054 /* Write B edge selection. */

Definition at line 271 of file s626.h.

#define LP_WREDGSELC 0x0064 /* Write C edge selection. */

Definition at line 275 of file s626.h.

#define LP_WRINTSELA 0x0042 /* Write A interrupt enable. */

Definition at line 266 of file s626.h.

#define LP_WRINTSELB 0x0052 /* Write B interrupt enable. */

Definition at line 270 of file s626.h.

#define LP_WRINTSELC 0x0062 /* Write C interrupt enable. */

Definition at line 274 of file s626.h.

#define LP_WRMISC2 0x0090 /* Write Misc2. */

Definition at line 320 of file s626.h.

#define MC1_A1IN 0x0001 /* enab/disable transfer on A1 in. */

Definition at line 189 of file s626.h.

#define MC1_A2IN 0x0004 /* enab/disable transfer on A2 in. */

Definition at line 188 of file s626.h.

#define MC1_A2OUT 0x0008 /* enab/disable transfer on A2 out. */

Definition at line 187 of file s626.h.

#define MC1_AUDIO 0x0200 /* enab/disable audio port pins. */

Definition at line 185 of file s626.h.

#define MC1_DEBI 0x0800 /* enab/disable DEBI pins. */

Definition at line 184 of file s626.h.

#define MC1_ERPS0 0x1000 /* enab/disable RPS task 0. */

Definition at line 183 of file s626.h.

#define MC1_ERPS1 0x2000 /* enab/disable RPS task 1. */

Definition at line 182 of file s626.h.

#define MC1_I2C 0x0100 /* enab/disable I2C interface. */

Definition at line 186 of file s626.h.

#define MC1_SHUTDOWN 0x3FFF0000 /* Shut down all MC1-controlled enables. */

Definition at line 180 of file s626.h.

#define MC1_SOFT_RESET 0x80000000 /* Invoke 7146 soft reset. */

Definition at line 179 of file s626.h.

#define MC2_ADC_RPS MC2_RPSSIG0 /* ADC RPS busy. */

Definition at line 215 of file s626.h.

#define MC2_DAC_RPS MC2_RPSSIG1 /* DAC RPS busy. */

Definition at line 216 of file s626.h.

#define MC2_DELAYBUSY_4USq MC2_RPSSIG1_MASK

Definition at line 204 of file s626.h.

#define MC2_DELAYBUSY_6USq MC2_RPSSIG2_MASK

Definition at line 207 of file s626.h.

#define MC2_DELAYTRIG_4USq MC2_RPSSIG1_ON

Definition at line 203 of file s626.h.

#define MC2_DELAYTRIG_6USq MC2_RPSSIG2_ON

Definition at line 206 of file s626.h.

#define MC2_RPSSIG0 0x0800 /* RPS signal 0 (ADC RPS busy). */

Definition at line 213 of file s626.h.

#define MC2_RPSSIG0_MASKq 0x00000800 /* RPS_SIG0 bit mask. */

Definition at line 201 of file s626.h.

#define MC2_RPSSIG0_ONq 0x08000800 /* Assert RPS_SIG0. */

Definition at line 196 of file s626.h.

#define MC2_RPSSIG1 0x1000 /* RPS signal 1 (DAC RPS busy). */

Definition at line 212 of file s626.h.

#define MC2_RPSSIG1_MASKq 0x00001000 /* RPS_SIG1 bit mask. */

Definition at line 200 of file s626.h.

#define MC2_RPSSIG1_ONq 0x10001000 /* Assert RPS_SIG1. */

Definition at line 195 of file s626.h.

#define MC2_RPSSIG2 0x2000 /* RPS signal 2 (not used). */

Definition at line 211 of file s626.h.

#define MC2_RPSSIG2_MASKq 0x00002000 /* RPS_SIG2 bit mask. */

Definition at line 199 of file s626.h.

#define MC2_RPSSIG2_ONq 0x20002000 /* Assert RPS_SIG2. */

Definition at line 194 of file s626.h.

#define MC2_UPLD_DEBI 0x0002 /* Upload DEBI. */

Definition at line 209 of file s626.h.

#define MC2_UPLD_DEBI_MASKq 0x00000002 /* Upload DEBI mask. */

Definition at line 197 of file s626.h.

#define MC2_UPLD_DEBIq 0x00020002 /* Upload DEBI registers. */

Definition at line 192 of file s626.h.

#define MC2_UPLD_DEBIQ 0x00020002 /* Upload DEBI registers. */

Definition at line 219 of file s626.h.

#define MC2_UPLD_IIC 0x0001 /* Upload I2C. */

Definition at line 210 of file s626.h.

#define MC2_UPLD_IIC_MASKq 0x00000001 /* Upload I2C mask. */

Definition at line 198 of file s626.h.

#define MC2_UPLD_IICq 0x00010001 /* Upload I2C registers. */

Definition at line 193 of file s626.h.

#define MC2_UPLD_IICQ 0x00010001 /* Upload I2C registers. */

Definition at line 220 of file s626.h.

#define MISC1_EDCAP

Value:

0x1000 /* enab edge capture on DIO chans

* specified by LP_WRCAPSELx. */

Definition at line 326 of file s626.h.

#define MISC1_NOEDCAP

Value:

0x0000 /* Disable edge capture on specified

* DIO chans. */

Definition at line 327 of file s626.h.

#define MISC1_WDISABLE 0x0000 /* Disable writes to MISC2. */

Definition at line 325 of file s626.h.

#define MISC1_WENABLE

Value:

0x8000 /* enab writes to MISC2 (except Clear

* Watchdog bit). */

Definition at line 324 of file s626.h.

#define MISC2_BATT_ENABLE 0x0008 /* Backup battery enable. */

Definition at line 337 of file s626.h.

#define MISC2_WDENABLE 0x0004 /* Watchdog timer enable. */

Definition at line 338 of file s626.h.

#define MISC2_WDPERIOD_MASK 0x0003 /* Watchdog interval */

Definition at line 339 of file s626.h.

#define MOTOROLA 2 /* Motorola bus type. */

Definition at line 91 of file s626.h.

#define MULT_X0 0x0003 /* Supports no multipliers; */

Definition at line 593 of file s626.h.

#define MULT_X1 0x0002 /* Supports multiplier x1; */

Definition at line 596 of file s626.h.

#define MULT_X2 0x0001 /* Supports multipliers x1, */

Definition at line 599 of file s626.h.

#define MULT_X4 0x0000 /* Supports multipliers x1, */

Definition at line 602 of file s626.h.

#define NUM_CLKMULTS 4

Definition at line 612 of file s626.h.

#define NUM_CLKPOLS 2

Definition at line 614 of file s626.h.

#define NUM_CLKSOURCES 4

Definition at line 613 of file s626.h.

#define NUM_COUNTERS 6 /* Maximum valid counter */

Definition at line 608 of file s626.h.

#define NUM_INDEXPOLS 2

Definition at line 615 of file s626.h.

#define NUM_INDEXSOURCES 2

Definition at line 616 of file s626.h.

#define NUM_INTSOURCES 4

Definition at line 610 of file s626.h.

#define NUM_LATCHSOURCES 4

Definition at line 611 of file s626.h.

#define NUM_LOADTRIGS 4

Definition at line 617 of file s626.h.

#define NUM_TRIMDACS 12 /* Number of valid TrimDAC channels. */

Definition at line 87 of file s626.h.

#define P_ACON1 0x00F4 /* Audio control 1. */

Definition at line 244 of file s626.h.

#define P_ACON2 0x00F8 /* Audio control 2. */

Definition at line 245 of file s626.h.

#define P_ADP4

Value:

0x0138 /* Logical audio DMA pointer of audio

* input FIFO A2_IN. */

Definition at line 254 of file s626.h.

#define P_BASEA2_IN

Value:

0x00AC /* Audio input 2 base physical DMAbuf

* address. */

Definition at line 230 of file s626.h.

#define P_BASEA2_OUT

Value:

0x00B8 /* Audio output 2 base physical DMAbuf

* address. */

Definition at line 233 of file s626.h.

#define P_DEBIAD 0x0088 /* DEBI target address. */

Definition at line 227 of file s626.h.

#define P_DEBIADq 0x0088 /* DEBI target address. */

Definition at line 444 of file s626.h.

#define P_DEBICFG 0x007C /* DEBI configuration. */

Definition at line 224 of file s626.h.

#define P_DEBICFGq 0x007C /* DEBI configuration. */

Definition at line 441 of file s626.h.

#define P_DEBICMD 0x0080 /* DEBI command. */

Definition at line 225 of file s626.h.

#define P_DEBICMDq 0x0080 /* DEBI command. */

Definition at line 442 of file s626.h.

#define P_DEBIPAGE 0x0084 /* DEBI page. */

Definition at line 226 of file s626.h.

#define P_DEBIPAGEq 0x0084 /* DEBI page. */

Definition at line 443 of file s626.h.

#define P_EC1R 0x0118 /* Event counter set 1. */

Definition at line 253 of file s626.h.

#define P_EC1SSR 0x00E4 /* Event counter set 1 source select. */

Definition at line 242 of file s626.h.

#define P_ECT1R 0x00EC /* Event counter threshold set 1. */

Definition at line 243 of file s626.h.

#define P_FB_BUFFER1 0x0144 /* Audio feedback buffer 1. */

Definition at line 255 of file s626.h.

#define P_FB_BUFFER2 0x0148 /* Audio feedback buffer 2. */

Definition at line 256 of file s626.h.

#define P_GPIO 0x00E0 /* General-purpose I/O. */

Definition at line 241 of file s626.h.

#define P_I2CCTRL 0x008C /* I2C control. */

Definition at line 228 of file s626.h.

#define P_I2CSTAT 0x0090 /* I2C status. */

Definition at line 229 of file s626.h.

#define P_IER 0x00DC /* Interrupt enable. */

Definition at line 240 of file s626.h.

#define P_ISR 0x010C /* Interrupt status. */

Definition at line 250 of file s626.h.

#define P_MC1 0x00FC /* Master control 1. */

Definition at line 246 of file s626.h.

#define P_MC2 0x0100 /* Master control 2. */

Definition at line 247 of file s626.h.

#define P_PAGEA2_IN 0x00B4 /* Audio input 2 paging attributes. */

Definition at line 232 of file s626.h.

#define P_PAGEA2_OUT 0x00C0 /* Audio output 2 paging attributes. */

Definition at line 235 of file s626.h.

#define P_PCI_BT_A 0x004C /* Audio DMA burst/threshold control. */

Definition at line 223 of file s626.h.

#define P_PROTA2_IN

Value:

0x00B0 /* Audio input 2 physical DMAbuf

* protection address. */

Definition at line 231 of file s626.h.

#define P_PROTA2_OUT

Value:

0x00BC /* Audio output 2 physical DMAbuf

* protection address. */

Definition at line 234 of file s626.h.

#define P_PSR 0x0110 /* Primary status. */

Definition at line 251 of file s626.h.

#define P_RPS0_TOUT 0x00D4 /* RPS0 time-out. */

Definition at line 238 of file s626.h.

#define P_RPS1_TOUT 0x00D8 /* RPS1 time-out. */

Definition at line 239 of file s626.h.

#define P_RPSADDR0 0x0104 /* RPS0 instruction pointer. */

Definition at line 248 of file s626.h.

#define P_RPSADDR1 0x0108 /* RPS1 instruction pointer. */

Definition at line 249 of file s626.h.

#define P_RPSPAGE0 0x00C4 /* RPS0 page. */

Definition at line 236 of file s626.h.

#define P_RPSPAGE1 0x00C8 /* RPS1 page. */

Definition at line 237 of file s626.h.

#define P_SSR 0x0114 /* Secondary status. */

Definition at line 252 of file s626.h.

#define P_TSL1 0x0180 /* Audio time slot list 1. */

Definition at line 257 of file s626.h.

#define P_TSL2 0x01C0 /* Audio time slot list 2. */

Definition at line 258 of file s626.h.

#define PLATFORM INTEL /* *** SELECT PLATFORM TYPE *** */

Definition at line 93 of file s626.h.

#define PSR_A2_IN 0x00008000 /* Audio output DMA2 protection address reached. */

Definition at line 170 of file s626.h.

#define PSR_AFOU 0x00000800 /* Audio FIFO under/overflow detected. */

Definition at line 171 of file s626.h.

#define PSR_DEBI_E 0x00040000 /* DEBI event flag. */

Definition at line 168 of file s626.h.

#define PSR_DEBI_S 0x00080000 /* DEBI status flag. */

Definition at line 169 of file s626.h.

#define PSR_EC0S 0x00000001 /* Event counter 0 threshold reached. */

Definition at line 173 of file s626.h.

#define PSR_GPIO2 0x00000020 /* GPIO2 input pin: 0=AdcBusy, 1=AdcIdle. */

Definition at line 172 of file s626.h.

#define RANGE_10V 0x00 /* +/-10V range */

Definition at line 96 of file s626.h.

#define RANGE_5V 0x10 /* +/-5V range */

Definition at line 95 of file s626.h.

#define RDMISC1_WDTIMEOUT 0x4000 /* Watchdog timer timed out. */

Definition at line 330 of file s626.h.

#define RPS_CLRSIGNAL 0x00000000 /* CLEAR SIGNAL */

Definition at line 131 of file s626.h.

#define RPS_DEBI 0x00000002 /* DEBI done */

Definition at line 144 of file s626.h.

#define RPS_GPIO2 0x00080000 /* RPS GPIO2 */

Definition at line 149 of file s626.h.

#define RPS_GPIO3 0x00100000 /* RPS GPIO3 */

Definition at line 150 of file s626.h.

#define RPS_INVERT 0x04000000 /* Test for negated semaphores. */

Definition at line 143 of file s626.h.

#define RPS_IRQ 0x60000000 /* IRQ */

Definition at line 140 of file s626.h.

#define RPS_JUMP 0x80000000 /* JUMP */

Definition at line 136 of file s626.h.

#define RPS_LDREG 0x90000100 /* LDREG (1 uint32_t only) */

Definition at line 137 of file s626.h.

#define RPS_LOGICAL_OR 0x08000000 /* Logical OR conditionals. */

Definition at line 142 of file s626.h.

#define RPS_NOP 0x00000000 /* NOP */

Definition at line 133 of file s626.h.

#define RPS_PAUSE 0x20000000 /* PAUSE */

Definition at line 134 of file s626.h.

#define RPS_SETSIGNAL 0x10000000 /* SET SIGNAL */

Definition at line 132 of file s626.h.

#define RPS_SIG0 0x00200000 /* RPS semaphore 0 (used by ADC). */

Definition at line 146 of file s626.h.

#define RPS_SIG1 0x00400000 /* RPS semaphore 1 (used by DAC). */

Definition at line 147 of file s626.h.

#define RPS_SIG2 0x00800000 /* RPS semaphore 2 (not used). */

Definition at line 148 of file s626.h.

#define RPS_SIGADC RPS_SIG0 /* Trigger/status for ADC's RPS program. */

Definition at line 152 of file s626.h.

#define RPS_SIGDAC RPS_SIG1 /* Trigger/status for DAC's RPS program. */

Definition at line 153 of file s626.h.

#define RPS_STOP 0x50000000 /* STOP */

Definition at line 139 of file s626.h.

#define RPS_STREG 0xA0000100 /* STREG (1 uint32_t only) */

Definition at line 138 of file s626.h.

#define RPS_UPLOAD 0x40000000 /* UPLOAD */

Definition at line 135 of file s626.h.

#define RPSCLK_PER_US (33 / RPSCLK_SCALAR) /* Number of RPS clocks in one microsecond. */

Definition at line 157 of file s626.h.

#define RPSCLK_SCALAR 8 /* This is apparent ratio of PCI/RPS clks (undocumented!!). */

Definition at line 156 of file s626.h.

#define RSD1 0x01000000 /* Shift A1 data in on SD1. */

Definition at line 380 of file s626.h.

#define RSD2 0x00001000 /* Shift data in on SD2. */

Definition at line 399 of file s626.h.

#define RSD3 0x00001800 /* Shift data in on SD3. */

Definition at line 398 of file s626.h.

#define S626_ADC_CHANNELS 16

Definition at line 78 of file s626.h.

#define S626_DAC_CHANNELS 4

Definition at line 79 of file s626.h.

#define S626_DIO_BANKS 3 /* Number of DIO groups. */

Definition at line 82 of file s626.h.

#define S626_DIO_CHANNELS 48

Definition at line 81 of file s626.h.

#define S626_DIO_EXTCHANS 40 /* Number of */

Definition at line 83 of file s626.h.

#define S626_ENCODER_CHANNELS 6

Definition at line 80 of file s626.h.

#define S626_SIZE 0x0200

Definition at line 75 of file s626.h.

#define SBA_RPS_A0 0x27 /* Time of RPS0 busy, in PCI clocks. */

Definition at line 160 of file s626.h.

#define SDW_A1

Value:

0x00800000 /* Store rcv'd char at next

* char slot of DWORD1 buffer. */

Definition at line 381 of file s626.h.

#define SF_A1

Value:

0x00200000 /* Write unsigned long

* buffer to input FIFO. */

Definition at line 383 of file s626.h.

#define SF_A2

Value:

0x00000100  /* Store next dword from A2's
                         * input shifter to its input
                         * fifo. */

Definition at line 395 of file s626.h.

#define SIB_A1

Value:

0x00400000 /* Store rcv'd char at next

* char slot of FB1 buffer. */

Definition at line 382 of file s626.h.

#define SIB_A2

Value:

0x00000200 /* Store next dword from A2's

* input shifter to FB2 buffer. */

Definition at line 394 of file s626.h.

#define SSR_AF2_OUT 0x00000200 /* Audio 2 output FIFO under/overflow detected. */

Definition at line 176 of file s626.h.

#define STDBIT_CLKENAB 0

Definition at line 681 of file s626.h.

#define STDBIT_CLKMULT 1

Definition at line 680 of file s626.h.

#define STDBIT_CLKPOL 3

Definition at line 679 of file s626.h.

#define STDBIT_CLKSRC 4

Definition at line 678 of file s626.h.

#define STDBIT_INDXPOL 6

Definition at line 677 of file s626.h.

#define STDBIT_INDXSRC 7

Definition at line 676 of file s626.h.

#define STDBIT_INTSRC 13

Definition at line 673 of file s626.h.

#define STDBIT_LATCHSRC 11

Definition at line 674 of file s626.h.

#define STDBIT_LOADSRC 9

Definition at line 675 of file s626.h.

#define STDMSK_CLKENAB ((uint16_t)(1 << STDBIT_CLKENAB))

Definition at line 693 of file s626.h.

#define STDMSK_CLKMULT ((uint16_t)(3 << STDBIT_CLKMULT))

Definition at line 692 of file s626.h.

#define STDMSK_CLKPOL ((uint16_t)(1 << STDBIT_CLKPOL))

Definition at line 691 of file s626.h.

#define STDMSK_CLKSRC ((uint16_t)(3 << STDBIT_CLKSRC))

Definition at line 690 of file s626.h.

#define STDMSK_INDXPOL ((uint16_t)(1 << STDBIT_INDXPOL))

Definition at line 689 of file s626.h.

#define STDMSK_INDXSRC ((uint16_t)(1 << STDBIT_INDXSRC))

Definition at line 688 of file s626.h.

#define STDMSK_INTSRC ((uint16_t)(3 << STDBIT_INTSRC))

Definition at line 685 of file s626.h.

#define STDMSK_LATCHSRC ((uint16_t)(3 << STDBIT_LATCHSRC))

Definition at line 686 of file s626.h.

#define STDMSK_LOADSRC ((uint16_t)(3 << STDBIT_LOADSRC))

Definition at line 687 of file s626.h.

#define TRUE (1)

Definition at line 66 of file s626.h.

#define WRMISC2_CHARGE_ENABLE 0x4000 /* enab battery trickle charging. */

Definition at line 334 of file s626.h.

#define WRMISC2_WDCLEAR 0x8000 /* Reset watchdog timer to zero. */

Definition at line 333 of file s626.h.

#define WS1 0x40000000 /* WS output to assert. */

Definition at line 376 of file s626.h.

#define WS2 0x20000000

Definition at line 377 of file s626.h.

#define WS3 0x10000000

Definition at line 378 of file s626.h.

#define WS4 0x08000000

Definition at line 379 of file s626.h.

#define WS_MODES 0x00019999 /* WS0 = TSL1 trigger */

Definition at line 347 of file s626.h.

#define XFB0 0x00000040 /* FB_BUFFER byte 0. */

Definition at line 390 of file s626.h.

#define XFB1 0x00000050 /* FB_BUFFER byte 1. */

Definition at line 391 of file s626.h.

#define XFB2 0x00000060 /* FB_BUFFER byte 2. */

Definition at line 392 of file s626.h.

#define XFB3 0x00000070 /* FB_BUFFER byte 3. */

Definition at line 393 of file s626.h.

#define XFIFO_0 0x00000000 /* Data fifo byte 0. */

Definition at line 386 of file s626.h.

#define XFIFO_1 0x00000010 /* Data fifo byte 1. */

Definition at line 387 of file s626.h.

#define XFIFO_2 0x00000020 /* Data fifo byte 2. */

Definition at line 388 of file s626.h.

#define XFIFO_3 0x00000030 /* Data fifo byte 3. */

Definition at line 389 of file s626.h.

#define XSD2 0x00000008 /* Shift data out on SD2. */

Definition at line 397 of file s626.h.

Data Structures

Macros

Macro Definition Documentation