#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/edac.h>
#include <linux/delay.h>
#include <linux/mmzone.h>
#include "edac_core.h"

Data Structures
struct	i5100_priv

Macros
#define	I5100_MC 0x40 /* Memory Control Register */

#define	I5100_MC_SCRBEN_MASK (1 << 7)

#define	I5100_MC_SCRBDONE_MASK (1 << 4)

#define	I5100_MS 0x44 /* Memory Status Register */

#define	I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */

#define	I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */

#define	I5100_TOLM 0x6c /* Top of Low Memory */

#define	I5100_MIR0 0x80 /* Memory Interleave Range 0 */

#define	I5100_MIR1 0x84 /* Memory Interleave Range 1 */

#define	I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */

#define	I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */

#define	I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */

#define	I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16)

#define	I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15)

#define	I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14)

#define	I5100_FERR_NF_MEM_M12ERR_MASK (1 << 12)

#define	I5100_FERR_NF_MEM_M11ERR_MASK (1 << 11)

#define	I5100_FERR_NF_MEM_M10ERR_MASK (1 << 10)

#define	I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6)

#define	I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5)

#define	I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4)

#define	I5100_FERR_NF_MEM_M1ERR_MASK (1 << 1)

#define	I5100_FERR_NF_MEM_ANY_MASK

#define	I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */

#define	I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */

#define	I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */

#define	I5100_DMIR 0x15c /* DIMM Interleave Range */

#define	I5100_VALIDLOG 0x18c /* Valid Log Markers */

#define	I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */

#define	I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */

#define	I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */

#define	I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */

#define	I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */

#define	I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */

#define	I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */

#define	I5100_MAX_RANKS_PER_CHAN 6

#define	I5100_CHANNELS 2

#define	I5100_MAX_RANKS_PER_DIMM 4

#define	I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */

#define	I5100_MAX_DIMM_SLOTS_PER_CHAN 4

#define	I5100_MAX_RANK_INTERLEAVE 4

#define	I5100_MAX_DMIRS 5

#define	I5100_SCRUB_REFRESH_RATE (5 * 60 * HZ)

Functions
	MODULE_DEVICE_TABLE (pci, i5100_pci_tbl)

	module_init (i5100_init)

	module_exit (i5100_exit)

	MODULE_LICENSE ("GPL")

	MODULE_AUTHOR ("Arthur Jones <[email protected]>")

	MODULE_DESCRIPTION ("MC Driver for Intel I5100 memory controllers")

Macro Definition Documentation

#define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */

Definition at line 45 of file i5100_edac.c.

#define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */

Definition at line 46 of file i5100_edac.c.

#define I5100_CHANNELS 2

Definition at line 290 of file i5100_edac.c.

#define I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */

Definition at line 292 of file i5100_edac.c.

#define I5100_DMIR 0x15c /* DIMM Interleave Range */

Definition at line 74 of file i5100_edac.c.

#define I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */

Definition at line 70 of file i5100_edac.c.

#define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */

Definition at line 47 of file i5100_edac.c.

#define I5100_FERR_NF_MEM_ANY_MASK

Value:

(I5100_FERR_NF_MEM_M16ERR_MASK | \
            I5100_FERR_NF_MEM_M15ERR_MASK | \
            I5100_FERR_NF_MEM_M14ERR_MASK | \
            I5100_FERR_NF_MEM_M12ERR_MASK | \
            I5100_FERR_NF_MEM_M11ERR_MASK | \
            I5100_FERR_NF_MEM_M10ERR_MASK | \
            I5100_FERR_NF_MEM_M6ERR_MASK | \
            I5100_FERR_NF_MEM_M5ERR_MASK | \
            I5100_FERR_NF_MEM_M4ERR_MASK | \
            I5100_FERR_NF_MEM_M1ERR_MASK)

Definition at line 58 of file i5100_edac.c.

#define I5100_FERR_NF_MEM_M10ERR_MASK (1 << 10)

Definition at line 53 of file i5100_edac.c.

#define I5100_FERR_NF_MEM_M11ERR_MASK (1 << 11)

Definition at line 52 of file i5100_edac.c.

#define I5100_FERR_NF_MEM_M12ERR_MASK (1 << 12)

Definition at line 51 of file i5100_edac.c.

#define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14)

Definition at line 50 of file i5100_edac.c.

#define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15)

Definition at line 49 of file i5100_edac.c.

#define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16)

Definition at line 48 of file i5100_edac.c.

#define I5100_FERR_NF_MEM_M1ERR_MASK (1 << 1)

Definition at line 57 of file i5100_edac.c.

#define I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4)

Definition at line 56 of file i5100_edac.c.

#define I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5)

Definition at line 55 of file i5100_edac.c.

#define I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6)

Definition at line 54 of file i5100_edac.c.

#define I5100_MAX_DIMM_SLOTS_PER_CHAN 4

Definition at line 293 of file i5100_edac.c.

#define I5100_MAX_DMIRS 5

Definition at line 295 of file i5100_edac.c.

#define I5100_MAX_RANK_INTERLEAVE 4

Definition at line 294 of file i5100_edac.c.

#define I5100_MAX_RANKS_PER_CHAN 6

Definition at line 289 of file i5100_edac.c.

#define I5100_MAX_RANKS_PER_DIMM 4

Definition at line 291 of file i5100_edac.c.

#define I5100_MC 0x40 /* Memory Control Register */

Definition at line 36 of file i5100_edac.c.

#define I5100_MC_SCRBDONE_MASK (1 << 4)

Definition at line 38 of file i5100_edac.c.

#define I5100_MC_SCRBEN_MASK (1 << 7)

Definition at line 37 of file i5100_edac.c.

#define I5100_MIR0 0x80 /* Memory Interleave Range 0 */

Definition at line 43 of file i5100_edac.c.

#define I5100_MIR1 0x84 /* Memory Interleave Range 1 */

Definition at line 44 of file i5100_edac.c.

#define I5100_MS 0x44 /* Memory Status Register */

Definition at line 39 of file i5100_edac.c.

#define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */

Definition at line 73 of file i5100_edac.c.

#define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */

Definition at line 82 of file i5100_edac.c.

#define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */

Definition at line 69 of file i5100_edac.c.

#define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */

Definition at line 76 of file i5100_edac.c.

#define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */

Definition at line 77 of file i5100_edac.c.

#define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */

Definition at line 80 of file i5100_edac.c.

#define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */

Definition at line 81 of file i5100_edac.c.

#define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */

Definition at line 78 of file i5100_edac.c.

#define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */

Definition at line 79 of file i5100_edac.c.

#define I5100_SCRUB_REFRESH_RATE (5 * 60 * HZ)

Definition at line 296 of file i5100_edac.c.

#define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */

Definition at line 41 of file i5100_edac.c.

#define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */

Definition at line 40 of file i5100_edac.c.

#define I5100_TOLM 0x6c /* Top of Low Memory */

Definition at line 42 of file i5100_edac.c.

#define I5100_VALIDLOG 0x18c /* Valid Log Markers */

Definition at line 75 of file i5100_edac.c.

Function Documentation

MODULE_AUTHOR ( "Arthur Jones <[email protected]>" )

MODULE_DESCRIPTION ( "MC Driver for Intel I5100 memory controllers" )

MODULE_DEVICE_TABLE	(	pci	,
		i5100_pci_tbl
	)

module_exit ( i5100_exit )

module_init ( i5100_init )

MODULE_LICENSE ( "GPL" )

Data Structures

Macros

Functions

Macro Definition Documentation

Function Documentation