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#define | MY_NAME "ibmphpd" |
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#define | debug(fmt, arg...) do { if (ibmphp_debug == 1) printk(KERN_DEBUG "%s: " fmt , MY_NAME , ## arg); } while (0) |
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#define | debug_pci(fmt, arg...) do { if (ibmphp_debug) printk(KERN_DEBUG "%s: " fmt , MY_NAME , ## arg); } while (0) |
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#define | err(format, arg...) printk(KERN_ERR "%s: " format , MY_NAME , ## arg) |
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#define | info(format, arg...) printk(KERN_INFO "%s: " format , MY_NAME , ## arg) |
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#define | warn(format, arg...) printk(KERN_WARNING "%s: " format , MY_NAME , ## arg) |
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#define | EBDA_SLOT_133_MAX 0x20 |
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#define | EBDA_SLOT_100_MAX 0x10 |
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#define | EBDA_SLOT_66_MAX 0x02 |
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#define | EBDA_SLOT_PCIX_CAP 0x08 |
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#define | EBDA_RSRC_TYPE_MASK 0x03 |
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#define | EBDA_IO_RSRC_TYPE 0x00 |
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#define | EBDA_MEM_RSRC_TYPE 0x01 |
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#define | EBDA_PFM_RSRC_TYPE 0x03 |
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#define | EBDA_RES_RSRC_TYPE 0x02 |
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#define | EBDA_IO_RESTRI_MASK 0x0c |
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#define | EBDA_NO_RESTRI 0x00 |
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#define | EBDA_AVO_VGA_ADDR 0x04 |
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#define | EBDA_AVO_VGA_ADDR_AND_ALIA 0x08 |
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#define | EBDA_AVO_ISA_ADDR 0x0c |
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#define | EBDA_DEV_TYPE_MASK 0x10 |
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#define | EBDA_PCI_DEV 0x10 |
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#define | EBDA_NON_PCI_DEV 0x00 |
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#define | EBDA_PRI_DEF_MASK 0x20 |
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#define | EBDA_PRI_PCI_BUS_INFO 0x20 |
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#define | EBDA_NORM_DEV_RSRC_INFO 0x00 |
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#define | HPC_DEVICE_ID 0x0246 |
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#define | HPC_SUBSYSTEM_ID 0x0247 |
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#define | HPC_PCI_OFFSET 0x40 |
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#define | MEM 0 |
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#define | IO 1 |
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#define | PFMEM 2 |
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#define | RESTYPE 0x03 |
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#define | IOMASK 0x00 /* will need to take its complement */ |
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#define | MMASK 0x01 |
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#define | PFMASK 0x03 |
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#define | PCIDEVMASK 0x10 /* we should always have PCI devices */ |
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#define | PRIMARYBUSMASK 0x20 |
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#define | PCI_VENDOR_ID_NOTVALID 0xFFFF |
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#define | PCI_HEADER_TYPE_MULTIDEVICE 0x80 |
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#define | PCI_HEADER_TYPE_MULTIBRIDGE 0x81 |
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#define | LATENCY 0x64 |
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#define | CACHE 64 |
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#define | DEVICEENABLE 0x015F /* CPQ has 0x0157 */ |
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#define | IOBRIDGE 0x1000 /* 4k */ |
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#define | MEMBRIDGE 0x100000 /* 1M */ |
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#define | SCSI_IRQ 0x09 |
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#define | LAN_IRQ 0x0A |
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#define | OTHER_IRQ 0x0B |
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#define | HPC_ERROR 0xFF |
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#define | BUS_SPEED 0x30 |
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#define | BUS_MODE 0x40 |
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#define | BUS_MODE_PCIX 0x01 |
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#define | BUS_MODE_PCI 0x00 |
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#define | BUS_SPEED_2 0x20 |
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#define | BUS_SPEED_1 0x10 |
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#define | BUS_SPEED_33 0x00 |
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#define | BUS_SPEED_66 0x01 |
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#define | BUS_SPEED_100 0x02 |
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#define | BUS_SPEED_133 0x03 |
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#define | BUS_SPEED_66PCIX 0x04 |
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#define | BUS_SPEED_66UNKNOWN 0x05 |
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#define | BUS_STATUS_AVAILABLE 0x01 |
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#define | BUS_CONTROL_AVAILABLE 0x02 |
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#define | SLOT_LATCH_REGS_SUPPORTED 0x10 |
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#define | PRGM_MODEL_REV_LEVEL 0xF0 |
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#define | MAX_ADAPTER_NONE 0x09 |
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#define | HPC_CTLR_ENABLEIRQ 0x00 |
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#define | HPC_CTLR_DISABLEIRQ 0x01 |
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#define | HPC_SLOT_OFF 0x02 |
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#define | HPC_SLOT_ON 0x03 |
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#define | HPC_SLOT_ATTNOFF 0x04 |
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#define | HPC_SLOT_ATTNON 0x05 |
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#define | HPC_CTLR_CLEARIRQ 0x06 |
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#define | HPC_CTLR_RESET 0x07 |
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#define | HPC_CTLR_IRQSTEER 0x08 |
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#define | HPC_BUS_33CONVMODE 0x09 |
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#define | HPC_BUS_66CONVMODE 0x0A |
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#define | HPC_BUS_66PCIXMODE 0x0B |
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#define | HPC_BUS_100PCIXMODE 0x0C |
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#define | HPC_BUS_133PCIXMODE 0x0D |
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#define | HPC_ALLSLOT_OFF 0x11 |
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#define | HPC_ALLSLOT_ON 0x12 |
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#define | HPC_SLOT_BLINKLED 0x13 |
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#define | READ_SLOTSTATUS 0x01 |
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#define | READ_EXTSLOTSTATUS 0x02 |
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#define | READ_BUSSTATUS 0x03 |
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#define | READ_CTLRSTATUS 0x04 |
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#define | READ_ALLSTAT 0x05 |
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#define | READ_ALLSLOT 0x06 |
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#define | READ_SLOTLATCHLOWREG 0x07 |
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#define | READ_REVLEVEL 0x08 |
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#define | READ_HPCOPTIONS 0x09 |
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#define | HPC_SLOT_POWER 0x01 |
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#define | HPC_SLOT_CONNECT 0x02 |
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#define | HPC_SLOT_ATTN 0x04 |
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#define | HPC_SLOT_PRSNT2 0x08 |
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#define | HPC_SLOT_PRSNT1 0x10 |
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#define | HPC_SLOT_PWRGD 0x20 |
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#define | HPC_SLOT_BUS_SPEED 0x40 |
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#define | HPC_SLOT_LATCH 0x80 |
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#define | HPC_SLOT_POWER_OFF 0x00 |
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#define | HPC_SLOT_POWER_ON 0x01 |
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#define | HPC_SLOT_CONNECTED 0x00 |
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#define | HPC_SLOT_DISCONNECTED 0x01 |
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#define | HPC_SLOT_ATTN_OFF 0x00 |
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#define | HPC_SLOT_ATTN_ON 0x01 |
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#define | HPC_SLOT_ATTN_BLINK 0x02 |
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#define | HPC_SLOT_EMPTY 0x00 |
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#define | HPC_SLOT_PRSNT_7 0x01 |
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#define | HPC_SLOT_PRSNT_15 0x02 |
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#define | HPC_SLOT_PRSNT_25 0x03 |
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#define | HPC_SLOT_PWRGD_FAULT_NONE 0x00 |
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#define | HPC_SLOT_PWRGD_GOOD 0x01 |
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#define | HPC_SLOT_BUS_SPEED_OK 0x00 |
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#define | HPC_SLOT_BUS_SPEED_MISM 0x01 |
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#define | HPC_SLOT_LATCH_OPEN 0x01 |
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#define | HPC_SLOT_LATCH_CLOSED 0x00 |
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#define | HPC_SLOT_PCIX 0x01 |
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#define | HPC_SLOT_SPEED1 0x02 |
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#define | HPC_SLOT_SPEED2 0x04 |
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#define | HPC_SLOT_BLINK_ATTN 0x08 |
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#define | HPC_SLOT_RSRVD1 0x10 |
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#define | HPC_SLOT_RSRVD2 0x20 |
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#define | HPC_SLOT_BUS_MODE 0x40 |
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#define | HPC_SLOT_RSRVD3 0x80 |
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#define | HPC_SLOT_PCIX_NO 0x00 |
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#define | HPC_SLOT_PCIX_YES 0x01 |
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#define | HPC_SLOT_SPEED_33 0x00 |
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#define | HPC_SLOT_SPEED_66 0x01 |
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#define | HPC_SLOT_SPEED_133 0x02 |
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#define | HPC_SLOT_ATTN_BLINK_OFF 0x00 |
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#define | HPC_SLOT_ATTN_BLINK_ON 0x01 |
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#define | HPC_SLOT_BUS_MODE_OK 0x00 |
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#define | HPC_SLOT_BUS_MODE_MISM 0x01 |
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#define | HPC_CTLR_WORKING 0x01 |
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#define | HPC_CTLR_FINISHED 0x02 |
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#define | HPC_CTLR_RESULT0 0x04 |
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#define | HPC_CTLR_RESULT1 0x08 |
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#define | HPC_CTLR_RESULE2 0x10 |
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#define | HPC_CTLR_RESULT3 0x20 |
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#define | HPC_CTLR_IRQ_ROUTG 0x40 |
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#define | HPC_CTLR_IRQ_PENDG 0x80 |
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#define | HPC_CTLR_WORKING_NO 0x00 |
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#define | HPC_CTLR_WORKING_YES 0x01 |
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#define | HPC_CTLR_FINISHED_NO 0x00 |
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#define | HPC_CTLR_FINISHED_YES 0x01 |
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#define | HPC_CTLR_RESULT_SUCCESS 0x00 |
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#define | HPC_CTLR_RESULT_FAILED 0x01 |
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#define | HPC_CTLR_RESULT_RSVD 0x02 |
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#define | HPC_CTLR_RESULT_NORESP 0x03 |
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#define | SLOT_POWER(s) |
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#define | SLOT_CONNECT(s) |
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#define | SLOT_ATTN(s, es) |
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#define | SLOT_PRESENT(s) |
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#define | SLOT_PWRGD(s) |
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#define | SLOT_BUS_SPEED(s) |
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#define | SLOT_LATCH(s) |
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#define | SLOT_PCIX(es) |
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#define | SLOT_SPEED(es) |
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#define | SLOT_BUS_MODE(es) |
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#define | CURRENT_BUS_SPEED(s) |
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#define | CURRENT_BUS_MODE(s) ((u8) (s & BUS_MODE) ? BUS_MODE_PCIX : BUS_MODE_PCI) |
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#define | READ_BUS_STATUS(s) ((u8) (s->options & BUS_STATUS_AVAILABLE)) |
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#define | READ_BUS_MODE(s) ((s->revision & PRGM_MODEL_REV_LEVEL) >= 0x20) |
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#define | SET_BUS_STATUS(s) ((u8) (s->options & BUS_CONTROL_AVAILABLE)) |
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#define | READ_SLOT_LATCH(s) ((u8) (s->options & SLOT_LATCH_REGS_SUPPORTED)) |
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#define | CTLR_WORKING(c) |
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#define | CTLR_FINISHED(c) |
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#define | CTLR_RESULT(c) |
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#define | NEEDTOCHECK_CMDSTATUS(c) |
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#define | ENABLE 1 |
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#define | DISABLE 0 |
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#define | CARD_INFO 0x07 |
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#define | PCIX133 0x07 |
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#define | PCIX66 0x05 |
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#define | PCI66 0x04 |
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