1 #ifndef __SOUND_ICE1712_H
2 #define __SOUND_ICE1712_H
40 #define ICEREG(ice, x) ((ice)->port + ICE1712_REG_##x)
42 #define ICE1712_REG_CONTROL 0x00
43 #define ICE1712_RESET 0x80
44 #define ICE1712_SERR_LEVEL 0x04
45 #define ICE1712_NATIVE 0x01
46 #define ICE1712_REG_IRQMASK 0x01
47 #define ICE1712_IRQ_MPU1 0x80
48 #define ICE1712_IRQ_TIMER 0x40
49 #define ICE1712_IRQ_MPU2 0x20
50 #define ICE1712_IRQ_PROPCM 0x10
51 #define ICE1712_IRQ_FM 0x08
52 #define ICE1712_IRQ_PBKDS 0x04
53 #define ICE1712_IRQ_CONCAP 0x02
54 #define ICE1712_IRQ_CONPBK 0x01
55 #define ICE1712_REG_IRQSTAT 0x02
57 #define ICE1712_REG_INDEX 0x03
58 #define ICE1712_REG_DATA 0x04
59 #define ICE1712_REG_NMI_STAT1 0x05
60 #define ICE1712_REG_NMI_DATA 0x06
61 #define ICE1712_REG_NMI_INDEX 0x07
62 #define ICE1712_REG_AC97_INDEX 0x08
63 #define ICE1712_REG_AC97_CMD 0x09
64 #define ICE1712_AC97_COLD 0x80
65 #define ICE1712_AC97_WARM 0x40
66 #define ICE1712_AC97_WRITE 0x20
67 #define ICE1712_AC97_READ 0x10
68 #define ICE1712_AC97_READY 0x08
69 #define ICE1712_AC97_PBK_VSR 0x02
70 #define ICE1712_AC97_CAP_VSR 0x01
71 #define ICE1712_REG_AC97_DATA 0x0a
72 #define ICE1712_REG_MPU1_CTRL 0x0c
73 #define ICE1712_REG_MPU1_DATA 0x0d
74 #define ICE1712_REG_I2C_DEV_ADDR 0x10
75 #define ICE1712_I2C_WRITE 0x01
76 #define ICE1712_REG_I2C_BYTE_ADDR 0x11
77 #define ICE1712_REG_I2C_DATA 0x12
78 #define ICE1712_REG_I2C_CTRL 0x13
79 #define ICE1712_I2C_EEPROM 0x80
80 #define ICE1712_I2C_BUSY 0x01
81 #define ICE1712_REG_CONCAP_ADDR 0x14
82 #define ICE1712_REG_CONCAP_COUNT 0x18
83 #define ICE1712_REG_SERR_SHADOW 0x1b
84 #define ICE1712_REG_MPU2_CTRL 0x1c
85 #define ICE1712_REG_MPU2_DATA 0x1d
86 #define ICE1712_REG_TIMER 0x1e
92 #define ICE1712_IREG_PBK_COUNT_LO 0x00
93 #define ICE1712_IREG_PBK_COUNT_HI 0x01
94 #define ICE1712_IREG_PBK_CTRL 0x02
95 #define ICE1712_IREG_PBK_LEFT 0x03
96 #define ICE1712_IREG_PBK_RIGHT 0x04
97 #define ICE1712_IREG_PBK_SOFT 0x05
98 #define ICE1712_IREG_PBK_RATE_LO 0x06
99 #define ICE1712_IREG_PBK_RATE_MID 0x07
100 #define ICE1712_IREG_PBK_RATE_HI 0x08
101 #define ICE1712_IREG_CAP_COUNT_LO 0x10
102 #define ICE1712_IREG_CAP_COUNT_HI 0x11
103 #define ICE1712_IREG_CAP_CTRL 0x12
104 #define ICE1712_IREG_GPIO_DATA 0x20
105 #define ICE1712_IREG_GPIO_WRITE_MASK 0x21
106 #define ICE1712_IREG_GPIO_DIRECTION 0x22
107 #define ICE1712_IREG_CONSUMER_POWERDOWN 0x30
108 #define ICE1712_IREG_PRO_POWERDOWN 0x31
114 #define ICEDS(ice, x) ((ice)->dmapath_port + ICE1712_DS_##x)
116 #define ICE1712_DS_INTMASK 0x00
117 #define ICE1712_DS_INTSTAT 0x02
118 #define ICE1712_DS_DATA 0x04
119 #define ICE1712_DS_INDEX 0x08
125 #define ICE1712_DSC_ADDR0 0x00
126 #define ICE1712_DSC_COUNT0 0x01
127 #define ICE1712_DSC_ADDR1 0x02
128 #define ICE1712_DSC_COUNT1 0x03
129 #define ICE1712_DSC_CONTROL 0x04
130 #define ICE1712_BUFFER1 0x80
131 #define ICE1712_BUFFER1_AUTO 0x40
132 #define ICE1712_BUFFER0_AUTO 0x20
133 #define ICE1712_FLUSH 0x10
134 #define ICE1712_STEREO 0x08
135 #define ICE1712_16BIT 0x04
136 #define ICE1712_PAUSE 0x02
137 #define ICE1712_START 0x01
138 #define ICE1712_DSC_RATE 0x05
139 #define ICE1712_DSC_VOLUME 0x06
145 #define ICEMT(ice, x) ((ice)->profi_port + ICE1712_MT_##x)
147 #define ICE1712_MT_IRQ 0x00
148 #define ICE1712_MULTI_CAPTURE 0x80
149 #define ICE1712_MULTI_PLAYBACK 0x40
150 #define ICE1712_MULTI_CAPSTATUS 0x02
151 #define ICE1712_MULTI_PBKSTATUS 0x01
152 #define ICE1712_MT_RATE 0x01
153 #define ICE1712_SPDIF_MASTER 0x10
154 #define ICE1712_MT_I2S_FORMAT 0x02
155 #define ICE1712_MT_AC97_INDEX 0x04
156 #define ICE1712_MT_AC97_CMD 0x05
158 #define ICE1712_MT_AC97_DATA 0x06
159 #define ICE1712_MT_PLAYBACK_ADDR 0x10
160 #define ICE1712_MT_PLAYBACK_SIZE 0x14
161 #define ICE1712_MT_PLAYBACK_COUNT 0x16
162 #define ICE1712_MT_PLAYBACK_CONTROL 0x18
163 #define ICE1712_CAPTURE_START_SHADOW 0x04
164 #define ICE1712_PLAYBACK_PAUSE 0x02
165 #define ICE1712_PLAYBACK_START 0x01
166 #define ICE1712_MT_CAPTURE_ADDR 0x20
167 #define ICE1712_MT_CAPTURE_SIZE 0x24
168 #define ICE1712_MT_CAPTURE_COUNT 0x26
169 #define ICE1712_MT_CAPTURE_CONTROL 0x28
170 #define ICE1712_CAPTURE_START 0x01
171 #define ICE1712_MT_ROUTE_PSDOUT03 0x30
172 #define ICE1712_MT_ROUTE_SPDOUT 0x32
173 #define ICE1712_MT_ROUTE_CAPTURE 0x34
174 #define ICE1712_MT_MONITOR_VOLUME 0x38
175 #define ICE1712_MT_MONITOR_INDEX 0x3a
176 #define ICE1712_MT_MONITOR_RATE 0x3b
177 #define ICE1712_MT_MONITOR_ROUTECTRL 0x3c
178 #define ICE1712_ROUTE_AC97 0x01
179 #define ICE1712_MT_MONITOR_PEAKINDEX 0x3e
180 #define ICE1712_MT_MONITOR_PEAKDATA 0x3f
187 #define ICE1712_CFG_CLOCK 0xc0
188 #define ICE1712_CFG_CLOCK512 0x00
189 #define ICE1712_CFG_CLOCK384 0x40
190 #define ICE1712_CFG_EXT 0x80
191 #define ICE1712_CFG_2xMPU401 0x20
192 #define ICE1712_CFG_NO_CON_AC97 0x10
193 #define ICE1712_CFG_ADC_MASK 0x0c
194 #define ICE1712_CFG_DAC_MASK 0x03
196 #define ICE1712_CFG_PRO_I2S 0x80
197 #define ICE1712_CFG_AC97_PACKED 0x01
199 #define ICE1712_CFG_I2S_VOLUME 0x80
200 #define ICE1712_CFG_I2S_96KHZ 0x40
201 #define ICE1712_CFG_I2S_RESMASK 0x30
202 #define ICE1712_CFG_I2S_OTHER 0x0f
204 #define ICE1712_CFG_I2S_CHIPID 0xfc
205 #define ICE1712_CFG_SPDIF_IN 0x02
206 #define ICE1712_CFG_SPDIF_OUT 0x01
212 #define ICE1712_DMA_MODE_WRITE 0x48
213 #define ICE1712_DMA_AUTOINIT 0x10
257 #define ice_has_con_ac97(ice) (!((ice)->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97))
387 #ifdef CONFIG_PM_SLEEP
390 unsigned int pm_suspend_enabled:1;
391 unsigned int pm_saved_is_spdif_master:1;
392 unsigned int pm_saved_spdif_ctrl;
393 unsigned char pm_saved_spdif_cfg;
394 unsigned int pm_saved_route;
402 static inline void snd_ice1712_gpio_set_dir(
struct snd_ice1712 *ice,
unsigned int bits)
404 ice->
gpio.set_dir(ice, bits);
407 static inline unsigned int snd_ice1712_gpio_get_dir(
struct snd_ice1712 *ice)
409 return ice->
gpio.get_dir(ice);
412 static inline void snd_ice1712_gpio_set_mask(
struct snd_ice1712 *ice,
unsigned int bits)
414 ice->
gpio.set_mask(ice, bits);
417 static inline void snd_ice1712_gpio_write(
struct snd_ice1712 *ice,
unsigned int val)
419 ice->
gpio.set_data(ice, val);
422 static inline unsigned int snd_ice1712_gpio_read(
struct snd_ice1712 *ice)
424 return ice->
gpio.get_data(ice);
432 static inline void snd_ice1712_save_gpio_status(
struct snd_ice1712 *ice)
435 ice->
gpio.saved[0] = ice->
gpio.direction;
436 ice->
gpio.saved[1] = ice->
gpio.write_mask;
439 static inline void snd_ice1712_restore_gpio_status(
struct snd_ice1712 *ice)
441 ice->
gpio.set_dir(ice, ice->
gpio.saved[0]);
442 ice->
gpio.set_mask(ice, ice->
gpio.saved[1]);
443 ice->
gpio.direction = ice->
gpio.saved[0];
444 ice->
gpio.write_mask = ice->
gpio.saved[1];
449 #define ICE1712_GPIO(xiface, xname, xindex, mask, invert, xaccess) \
450 { .iface = xiface, .name = xname, .access = xaccess, .info = snd_ctl_boolean_mono_info, \
451 .get = snd_ice1712_gpio_get, .put = snd_ice1712_gpio_put, \
452 .private_value = mask | (invert << 24) }
460 static inline void snd_ice1712_gpio_write_bits(
struct snd_ice1712 *ice,
461 unsigned int mask,
unsigned int bits)
466 snd_ice1712_gpio_set_dir(ice, ice->
gpio.direction);
467 val = snd_ice1712_gpio_read(ice);
470 snd_ice1712_gpio_write(ice, val);
473 static inline int snd_ice1712_gpio_read_bits(
struct snd_ice1712 *ice,
476 ice->
gpio.direction &= ~mask;
477 snd_ice1712_gpio_set_dir(ice, ice->
gpio.direction);
478 return snd_ice1712_gpio_read(ice) &
mask;