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ide-timings.c
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1 /*
2  * Copyright (c) 1999-2001 Vojtech Pavlik
3  * Copyright (c) 2007-2008 Bartlomiej Zolnierkiewicz
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18  *
19  * Should you need to contact me, the author, you can do so either by
20  * e-mail - mail your message to <[email protected]>, or by paper mail:
21  * Vojtech Pavlik, Simunkova 1594, Prague 8, 182 00 Czech Republic
22  */
23 
24 #include <linux/kernel.h>
25 #include <linux/ide.h>
26 #include <linux/module.h>
27 
28 /*
29  * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
30  * These were taken from ATA/ATAPI-6 standard, rev 0a, except
31  * for PIO 5, which is a nonstandard extension and UDMA6, which
32  * is currently supported only by Maxtor drives.
33  */
34 
35 static struct ide_timing ide_timing[] = {
36 
37  { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
38  { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
39  { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
40  { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
41 
42  { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
43  { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
44  { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
45 
46  { XFER_MW_DMA_4, 25, 0, 0, 0, 55, 20, 80, 0 },
47  { XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 100, 0 },
48  { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
49  { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
50  { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
51 
52  { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
53  { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
54  { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
55 
56  { XFER_PIO_6, 10, 55, 20, 80, 55, 20, 80, 0 },
57  { XFER_PIO_5, 15, 65, 25, 100, 65, 25, 100, 0 },
58  { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
59  { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
60 
61  { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
62  { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
63  { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
64 
65  { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 },
66 
67  { 0xff }
68 };
69 
70 struct ide_timing *ide_timing_find_mode(u8 speed)
71 {
72  struct ide_timing *t;
73 
74  for (t = ide_timing; t->mode != speed; t++)
75  if (t->mode == 0xff)
76  return NULL;
77  return t;
78 }
79 EXPORT_SYMBOL_GPL(ide_timing_find_mode);
80 
81 u16 ide_pio_cycle_time(ide_drive_t *drive, u8 pio)
82 {
83  u16 *id = drive->id;
84  struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
85  u16 cycle = 0;
86 
87  if (id[ATA_ID_FIELD_VALID] & 2) {
88  if (ata_id_has_iordy(drive->id))
89  cycle = id[ATA_ID_EIDE_PIO_IORDY];
90  else
91  cycle = id[ATA_ID_EIDE_PIO];
92 
93  /* conservative "downgrade" for all pre-ATA2 drives */
94  if (pio < 3 && cycle < t->cycle)
95  cycle = 0; /* use standard timing */
96 
97  /* Use the standard timing for the CF specific modes too */
98  if (pio > 4 && ata_id_is_cfa(id))
99  cycle = 0;
100  }
101 
102  return cycle ? cycle : t->cycle;
103 }
104 EXPORT_SYMBOL_GPL(ide_pio_cycle_time);
105 
106 #define ENOUGH(v, unit) (((v) - 1) / (unit) + 1)
107 #define EZ(v, unit) ((v) ? ENOUGH(v, unit) : 0)
108 
109 static void ide_timing_quantize(struct ide_timing *t, struct ide_timing *q,
110  int T, int UT)
111 {
112  q->setup = EZ(t->setup * 1000, T);
113  q->act8b = EZ(t->act8b * 1000, T);
114  q->rec8b = EZ(t->rec8b * 1000, T);
115  q->cyc8b = EZ(t->cyc8b * 1000, T);
116  q->active = EZ(t->active * 1000, T);
117  q->recover = EZ(t->recover * 1000, T);
118  q->cycle = EZ(t->cycle * 1000, T);
119  q->udma = EZ(t->udma * 1000, UT);
120 }
121 
122 void ide_timing_merge(struct ide_timing *a, struct ide_timing *b,
123  struct ide_timing *m, unsigned int what)
124 {
125  if (what & IDE_TIMING_SETUP)
126  m->setup = max(a->setup, b->setup);
127  if (what & IDE_TIMING_ACT8B)
128  m->act8b = max(a->act8b, b->act8b);
129  if (what & IDE_TIMING_REC8B)
130  m->rec8b = max(a->rec8b, b->rec8b);
131  if (what & IDE_TIMING_CYC8B)
132  m->cyc8b = max(a->cyc8b, b->cyc8b);
133  if (what & IDE_TIMING_ACTIVE)
134  m->active = max(a->active, b->active);
135  if (what & IDE_TIMING_RECOVER)
136  m->recover = max(a->recover, b->recover);
137  if (what & IDE_TIMING_CYCLE)
138  m->cycle = max(a->cycle, b->cycle);
139  if (what & IDE_TIMING_UDMA)
140  m->udma = max(a->udma, b->udma);
141 }
142 EXPORT_SYMBOL_GPL(ide_timing_merge);
143 
144 int ide_timing_compute(ide_drive_t *drive, u8 speed,
145  struct ide_timing *t, int T, int UT)
146 {
147  u16 *id = drive->id;
148  struct ide_timing *s, p;
149 
150  /*
151  * Find the mode.
152  */
153  s = ide_timing_find_mode(speed);
154  if (s == NULL)
155  return -EINVAL;
156 
157  /*
158  * Copy the timing from the table.
159  */
160  *t = *s;
161 
162  /*
163  * If the drive is an EIDE drive, it can tell us it needs extended
164  * PIO/MWDMA cycle timing.
165  */
166  if (id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
167  memset(&p, 0, sizeof(p));
168 
169  if (speed >= XFER_PIO_0 && speed < XFER_SW_DMA_0) {
170  if (speed <= XFER_PIO_2)
171  p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO];
172  else if ((speed <= XFER_PIO_4) ||
173  (speed == XFER_PIO_5 && !ata_id_is_cfa(id)))
174  p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY];
175  } else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
176  p.cycle = id[ATA_ID_EIDE_DMA_MIN];
177 
178  ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B);
179  }
180 
181  /*
182  * Convert the timing to bus clock counts.
183  */
184  ide_timing_quantize(t, t, T, UT);
185 
186  /*
187  * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
188  * S.M.A.R.T and some other commands. We have to ensure that the
189  * DMA cycle timing is slower/equal than the current PIO timing.
190  */
191  if (speed >= XFER_SW_DMA_0) {
192  ide_timing_compute(drive, drive->pio_mode, &p, T, UT);
193  ide_timing_merge(&p, t, t, IDE_TIMING_ALL);
194  }
195 
196  /*
197  * Lengthen active & recovery time so that cycle time is correct.
198  */
199  if (t->act8b + t->rec8b < t->cyc8b) {
200  t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
201  t->rec8b = t->cyc8b - t->act8b;
202  }
203 
204  if (t->active + t->recover < t->cycle) {
205  t->active += (t->cycle - (t->active + t->recover)) / 2;
206  t->recover = t->cycle - t->active;
207  }
208 
209  return 0;
210 }
211 EXPORT_SYMBOL_GPL(ide_timing_compute);
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