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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/init.h>#include <linux/types.h>#include <linux/mm.h>#include <linux/interrupt.h>#include <linux/spinlock.h>#include <linux/device.h>#include <linux/dma-mapping.h>#include <linux/slab.h>#include <linux/platform_device.h>#include <linux/clk.h>#include <linux/dmaengine.h>#include <linux/module.h>#include <asm/irq.h>#include <linux/platform_data/dma-imx.h>#include <mach/hardware.h>#include "dmaengine.h"Go to the source code of this file.
Data Structures | |
| struct | imx_dma_2d_config |
| struct | imxdma_desc |
| struct | imxdma_channel |
| struct | imxdma_engine |
Macros | |
| #define | IMXDMA_MAX_CHAN_DESCRIPTORS 16 |
| #define | IMX_DMA_CHANNELS 16 |
| #define | IMX_DMA_2D_SLOTS 2 |
| #define | IMX_DMA_2D_SLOT_A 0 |
| #define | IMX_DMA_2D_SLOT_B 1 |
| #define | IMX_DMA_LENGTH_LOOP ((unsigned int)-1) |
| #define | IMX_DMA_MEMSIZE_32 (0 << 4) |
| #define | IMX_DMA_MEMSIZE_8 (1 << 4) |
| #define | IMX_DMA_MEMSIZE_16 (2 << 4) |
| #define | IMX_DMA_TYPE_LINEAR (0 << 10) |
| #define | IMX_DMA_TYPE_2D (1 << 10) |
| #define | IMX_DMA_TYPE_FIFO (2 << 10) |
| #define | IMX_DMA_ERR_BURST (1 << 0) |
| #define | IMX_DMA_ERR_REQUEST (1 << 1) |
| #define | IMX_DMA_ERR_TRANSFER (1 << 2) |
| #define | IMX_DMA_ERR_BUFFER (1 << 3) |
| #define | IMX_DMA_ERR_TIMEOUT (1 << 4) |
| #define | DMA_DCR 0x00 /* Control Register */ |
| #define | DMA_DISR 0x04 /* Interrupt status Register */ |
| #define | DMA_DIMR 0x08 /* Interrupt mask Register */ |
| #define | DMA_DBTOSR 0x0c /* Burst timeout status Register */ |
| #define | DMA_DRTOSR 0x10 /* Request timeout Register */ |
| #define | DMA_DSESR 0x14 /* Transfer Error Status Register */ |
| #define | DMA_DBOSR 0x18 /* Buffer overflow status Register */ |
| #define | DMA_DBTOCR 0x1c /* Burst timeout control Register */ |
| #define | DMA_WSRA 0x40 /* W-Size Register A */ |
| #define | DMA_XSRA 0x44 /* X-Size Register A */ |
| #define | DMA_YSRA 0x48 /* Y-Size Register A */ |
| #define | DMA_WSRB 0x4c /* W-Size Register B */ |
| #define | DMA_XSRB 0x50 /* X-Size Register B */ |
| #define | DMA_YSRB 0x54 /* Y-Size Register B */ |
| #define | DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */ |
| #define | DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */ |
| #define | DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */ |
| #define | DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ |
| #define | DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */ |
| #define | DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */ |
| #define | DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */ |
| #define | DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */ |
| #define | DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */ |
| #define | DCR_DRST (1<<1) |
| #define | DCR_DEN (1<<0) |
| #define | DBTOCR_EN (1<<15) |
| #define | DBTOCR_CNT(x) ((x) & 0x7fff) |
| #define | CNTR_CNT(x) ((x) & 0xffffff) |
| #define | CCR_ACRPT (1<<14) |
| #define | CCR_DMOD_LINEAR (0x0 << 12) |
| #define | CCR_DMOD_2D (0x1 << 12) |
| #define | CCR_DMOD_FIFO (0x2 << 12) |
| #define | CCR_DMOD_EOBFIFO (0x3 << 12) |
| #define | CCR_SMOD_LINEAR (0x0 << 10) |
| #define | CCR_SMOD_2D (0x1 << 10) |
| #define | CCR_SMOD_FIFO (0x2 << 10) |
| #define | CCR_SMOD_EOBFIFO (0x3 << 10) |
| #define | CCR_MDIR_DEC (1<<9) |
| #define | CCR_MSEL_B (1<<8) |
| #define | CCR_DSIZ_32 (0x0 << 6) |
| #define | CCR_DSIZ_8 (0x1 << 6) |
| #define | CCR_DSIZ_16 (0x2 << 6) |
| #define | CCR_SSIZ_32 (0x0 << 4) |
| #define | CCR_SSIZ_8 (0x1 << 4) |
| #define | CCR_SSIZ_16 (0x2 << 4) |
| #define | CCR_REN (1<<3) |
| #define | CCR_RPT (1<<2) |
| #define | CCR_FRC (1<<1) |
| #define | CCR_CEN (1<<0) |
| #define | RTOR_EN (1<<15) |
| #define | RTOR_CLK (1<<14) |
| #define | RTOR_PSC (1<<13) |
Enumerations | |
| enum | imxdma_prep_type { IMXDMA_DESC_MEMCPY, IMXDMA_DESC_INTERLEAVED, IMXDMA_DESC_SLAVE_SG, IMXDMA_DESC_CYCLIC } |
Functions | |
| subsys_initcall (imxdma_module_init) | |
| MODULE_AUTHOR ("Sascha Hauer, Pengutronix <[email protected]>") | |
| MODULE_DESCRIPTION ("i.MX dma driver") | |
| MODULE_LICENSE ("GPL") | |
| #define DMA_BLR | ( | x | ) | (0x94 + ((x) << 6)) /* Burst length Registers */ |
| #define DMA_BUCR | ( | x | ) | (0x98 + ((x) << 6)) /* Bus Utilization Registers */ |
| #define DMA_CCNR | ( | x | ) | (0x9C + ((x) << 6)) /* Channel counter Registers */ |
| #define DMA_CCR | ( | x | ) | (0x8c + ((x) << 6)) /* Control Registers */ |
| #define DMA_CNTR | ( | x | ) | (0x88 + ((x) << 6)) /* Count Registers */ |
| #define DMA_DAR | ( | x | ) | (0x84 + ((x) << 6)) /* Destination Address Registers */ |
| #define DMA_DBOSR 0x18 /* Buffer overflow status Register */ |
| #define DMA_DBTOCR 0x1c /* Burst timeout control Register */ |
| #define DMA_DBTOSR 0x0c /* Burst timeout status Register */ |
| #define DMA_DSESR 0x14 /* Transfer Error Status Register */ |
| #define DMA_RSSR | ( | x | ) | (0x90 + ((x) << 6)) /* Request source select Registers */ |
| #define DMA_RTOR | ( | x | ) | (0x98 + ((x) << 6)) /* Request timeout Registers */ |
| #define DMA_SAR | ( | x | ) | (0x80 + ((x) << 6)) /* Source Address Registers */ |
| enum imxdma_prep_type |
| MODULE_AUTHOR | ( | "Sascha | Hauer, |
| Pengutronix< s.hauer @pengutronix.de >" | |||
| ) |
| MODULE_LICENSE | ( | "GPL" | ) |
| subsys_initcall | ( | imxdma_module_init | ) |
1.8.2