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#define DMA_AXI_BLEN_128 (1 << 6) |
#define DMA_AXI_BLEN_16 (1 << 3) |
#define DMA_AXI_BLEN_256 (1 << 7) |
#define DMA_AXI_BLEN_32 (1 << 4) |
#define DMA_AXI_BLEN_4 (1 << 1) |
#define DMA_AXI_BLEN_64 (1 << 5) |
#define DMA_AXI_BLEN_8 (1 << 2) |
#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */ |
#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ |
#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */ |
#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ |
#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ |
#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */ |
#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */ |
#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */ |
#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */ |
#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */ |
#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */ |
#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */ |
#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */ |
#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */ |
#define STMMAC_RX_COE_NONE 0 |
#define STMMAC_RX_COE_TYPE1 1 |
#define STMMAC_RX_COE_TYPE2 2 |