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stmmac.h
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1 /*******************************************************************************
2 
3  Header file for stmmac platform data
4 
5  Copyright (C) 2009 STMicroelectronics Ltd
6 
7  This program is free software; you can redistribute it and/or modify it
8  under the terms and conditions of the GNU General Public License,
9  version 2, as published by the Free Software Foundation.
10 
11  This program is distributed in the hope it will be useful, but WITHOUT
12  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14  more details.
15 
16  You should have received a copy of the GNU General Public License along with
17  this program; if not, write to the Free Software Foundation, Inc.,
18  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 
20  The full GNU General Public License is included in this distribution in
21  the file called "COPYING".
22 
23  Author: Giuseppe Cavallaro <[email protected]>
24 *******************************************************************************/
25 
26 #ifndef __STMMAC_PLATFORM_DATA
27 #define __STMMAC_PLATFORM_DATA
28 
29 #include <linux/platform_device.h>
30 
31 #define STMMAC_RX_COE_NONE 0
32 #define STMMAC_RX_COE_TYPE1 1
33 #define STMMAC_RX_COE_TYPE2 2
34 
35 /* Define the macros for CSR clock range parameters to be passed by
36  * platform code.
37  * This could also be configured at run time using CPU freq framework. */
38 
39 /* MDC Clock Selection define*/
40 #define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
41 #define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
42 #define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
43 #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
44 #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
45 #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
46 
47 /* The MDC clock could be set higher than the IEEE 802.3
48  * specified frequency limit 0f 2.5 MHz, by programming a clock divider
49  * of value different than the above defined values. The resultant MDIO
50  * clock frequency of 12.5 MHz is applicable for the interfacing chips
51  * supporting higher MDC clocks.
52  * The MDC clock selection macros need to be defined for MDC clock rate
53  * of 12.5 MHz, corresponding to the following selection.
54  */
55 #define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
56 #define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */
57 #define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */
58 #define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */
59 #define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */
60 #define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */
61 #define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */
62 #define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
63 
64 /* AXI DMA Burst length suported */
65 #define DMA_AXI_BLEN_4 (1 << 1)
66 #define DMA_AXI_BLEN_8 (1 << 2)
67 #define DMA_AXI_BLEN_16 (1 << 3)
68 #define DMA_AXI_BLEN_32 (1 << 4)
69 #define DMA_AXI_BLEN_64 (1 << 5)
70 #define DMA_AXI_BLEN_128 (1 << 6)
71 #define DMA_AXI_BLEN_256 (1 << 7)
72 #define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
73  | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
74  | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
75 
76 /* Platfrom data for platform device structure's platform_data field */
77 
79  int (*phy_reset)(void *priv);
80  unsigned int phy_mask;
81  int *irqs;
83 };
84 
86  int pbl;
89  int burst_len;
90 };
91 
93  char *phy_bus_name;
94  int bus_id;
95  int phy_addr;
96  int interface;
99  int clk_csr;
100  int has_gmac;
101  int enh_desc;
102  int tx_coe;
103  int rx_coe;
105  int pmt;
107  void (*fix_mac_speed)(void *priv, unsigned int speed);
108  void (*bus_setup)(void __iomem *ioaddr);
111  void *custom_cfg;
112  void *custom_data;
113  void *bsp_priv;
114 };
115 #endif