#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/info.h>
#include <sound/initval.h>

Data Structures
struct	ichdev

struct	intel8x0m

struct	ich_pcm_table

struct	ich_reg_info

struct	shortname_table

Macros
#define	ICHREG(x) ICH_REG_##x

#define	DEFINE_REGSET(name, base)

#define	ICH_REG_LVI_MASK 0x1f

#define	ICH_FIFOE 0x10 /* FIFO error */

#define	ICH_BCIS 0x08 /* buffer completion interrupt status */

#define	ICH_LVBCI 0x04 /* last valid buffer completion interrupt */

#define	ICH_CELV 0x02 /* current equals last valid */

#define	ICH_DCH 0x01 /* DMA controller halted */

#define	ICH_REG_PIV_MASK 0x1f /* mask */

#define	ICH_IOCE 0x10 /* interrupt on completion enable */

#define	ICH_FEIE 0x08 /* fifo error interrupt enable */

#define	ICH_LVBIE 0x04 /* last valid buffer interrupt enable */

#define	ICH_RESETREGS 0x02 /* reset busmaster registers */

#define	ICH_STARTBM 0x01 /* start busmaster operation */

#define	ICH_REG_GLOB_CNT 0x3c /* dword - global control */

#define	ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */

#define	ICH_SRIE 0x00000020 /* secondary resume interrupt enable */

#define	ICH_PRIE 0x00000010 /* primary resume interrupt enable */

#define	ICH_ACLINK 0x00000008 /* AClink shut off */

#define	ICH_AC97WARM 0x00000004 /* AC'97 warm reset */

#define	ICH_AC97COLD 0x00000002 /* AC'97 cold reset */

#define	ICH_GIE 0x00000001 /* GPI interrupt enable */

#define	ICH_REG_GLOB_STA 0x40 /* dword - global status */

#define	ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */

#define	ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */

#define	ICH_BCS 0x08000000 /* ICH4: bit clock stopped */

#define	ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */

#define	ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */

#define	ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */

#define	ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */

#define	ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */

#define	ICH_MD3 0x00020000 /* modem power down semaphore */

#define	ICH_AD3 0x00010000 /* audio power down semaphore */

#define	ICH_RCS 0x00008000 /* read completion status */

#define	ICH_BIT3 0x00004000 /* bit 3 slot 12 */

#define	ICH_BIT2 0x00002000 /* bit 2 slot 12 */

#define	ICH_BIT1 0x00001000 /* bit 1 slot 12 */

#define	ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */

#define	ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */

#define	ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */

#define	ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */

#define	ICH_MCINT 0x00000080 /* MIC capture interrupt */

#define	ICH_POINT 0x00000040 /* playback interrupt */

#define	ICH_PIINT 0x00000020 /* capture interrupt */

#define	ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */

#define	ICH_MOINT 0x00000004 /* modem playback interrupt */

#define	ICH_MIINT 0x00000002 /* modem capture interrupt */

#define	ICH_GSCI 0x00000001 /* GPI status change interrupt */

#define	ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */

#define	ICH_CAS 0x01 /* codec access semaphore */

#define	ICH_MAX_FRAGS 32 /* max hw frags */

#define	get_ichdev(substream) (substream->runtime->private_data)

#define	INTEL8X0M_PM_OPS NULL

#define	snd_intel8x0m_proc_init(chip)

Enumerations
enum	{ DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }

enum	{ ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT }

enum	{ ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT }

Functions
	MODULE_AUTHOR ("Jaroslav Kysela <[email protected]>")

	MODULE_DESCRIPTION ("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; ""SiS 7013; NVidia MCP/2/2S/3 modems")

	MODULE_LICENSE ("GPL")

	MODULE_SUPPORTED_DEVICE ("{{Intel,82801AA-ICH},""{Intel,82901AB-ICH0},""{Intel,82801BA-ICH2},""{Intel,82801CA-ICH3},""{Intel,82801DB-ICH4},""{Intel,ICH5},""{Intel,ICH6},""{Intel,ICH7},""{Intel,MX440},""{SiS,7013},""{NVidia,NForce Modem},""{NVidia,NForce2 Modem},""{NVidia,NForce2s Modem},""{NVidia,NForce3 Modem},""{AMD,AMD768}}")

	module_param (index, int, 0444)

	MODULE_PARM_DESC (index,"Index value for Intel i8x0 modemcard.")

	module_param (id, charp, 0444)

	MODULE_PARM_DESC (id,"ID string for Intel i8x0 modemcard.")

	module_param (ac97_clock, int, 0444)

	MODULE_PARM_DESC (ac97_clock,"AC'97 codec clock (0 = auto-detect).")

	module_param (enable, bool, 0444)

	DEFINE_REGSET (OFF, 0)

	MODULE_DEVICE_TABLE (pci, snd_intel8x0m_ids)

	module_pci_driver (intel8x0m_driver)

Macro Definition Documentation

#define DEFINE_REGSET	(	name,
		base
	)

Value:

enum { \
    ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
    ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
    ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
    ICH_REG_##name##_SR = base + 0x06,  /* byte - status register */ \
    ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
    ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
    ICH_REG_##name##_CR = base + 0x0b,  /* byte - control register */ \
};

Definition at line 81 of file intel8x0m.c.

#define get_ichdev ( substream ) (substream->runtime->private_data)

Definition at line 166 of file intel8x0m.c.

#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */

Definition at line 125 of file intel8x0m.c.

#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */

Definition at line 124 of file intel8x0m.c.

#define ICH_ACLINK 0x00000008 /* AClink shut off */

Definition at line 123 of file intel8x0m.c.

#define ICH_AD3 0x00010000 /* audio power down semaphore */

Definition at line 137 of file intel8x0m.c.

#define ICH_BCIS 0x08 /* buffer completion interrupt status */

Definition at line 102 of file intel8x0m.c.

#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */

Definition at line 130 of file intel8x0m.c.

#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */

Definition at line 141 of file intel8x0m.c.

#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */

Definition at line 140 of file intel8x0m.c.

#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */

Definition at line 139 of file intel8x0m.c.

#define ICH_CAS 0x01 /* codec access semaphore */

Definition at line 154 of file intel8x0m.c.

#define ICH_CELV 0x02 /* current equals last valid */

Definition at line 104 of file intel8x0m.c.

#define ICH_DCH 0x01 /* DMA controller halted */

Definition at line 105 of file intel8x0m.c.

#define ICH_FEIE 0x08 /* fifo error interrupt enable */

Definition at line 112 of file intel8x0m.c.

#define ICH_FIFOE 0x10 /* FIFO error */

Definition at line 101 of file intel8x0m.c.

#define ICH_GIE 0x00000001 /* GPI interrupt enable */

Definition at line 126 of file intel8x0m.c.

#define ICH_GSCI 0x00000001 /* GPI status change interrupt */

Definition at line 152 of file intel8x0m.c.

#define ICH_IOCE 0x10 /* interrupt on completion enable */

Definition at line 111 of file intel8x0m.c.

#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */

Definition at line 103 of file intel8x0m.c.

#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */

Definition at line 113 of file intel8x0m.c.

#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */

Definition at line 133 of file intel8x0m.c.

#define ICH_MAX_FRAGS 32 /* max hw frags */

Definition at line 156 of file intel8x0m.c.

#define ICH_MCINT 0x00000080 /* MIC capture interrupt */

Definition at line 146 of file intel8x0m.c.

#define ICH_MD3 0x00020000 /* modem power down semaphore */

Definition at line 136 of file intel8x0m.c.

#define ICH_MIINT 0x00000002 /* modem capture interrupt */

Definition at line 151 of file intel8x0m.c.

#define ICH_MOINT 0x00000004 /* modem playback interrupt */

Definition at line 150 of file intel8x0m.c.

#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */

Definition at line 135 of file intel8x0m.c.

#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */

Definition at line 149 of file intel8x0m.c.

#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */

Definition at line 132 of file intel8x0m.c.

#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */

Definition at line 145 of file intel8x0m.c.

#define ICH_PIINT 0x00000020 /* capture interrupt */

Definition at line 148 of file intel8x0m.c.

#define ICH_POINT 0x00000040 /* playback interrupt */

Definition at line 147 of file intel8x0m.c.

#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */

Definition at line 143 of file intel8x0m.c.

#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */

Definition at line 122 of file intel8x0m.c.

#define ICH_RCS 0x00008000 /* read completion status */

Definition at line 138 of file intel8x0m.c.

#define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */

Definition at line 153 of file intel8x0m.c.

#define ICH_REG_GLOB_CNT 0x3c /* dword - global control */

Definition at line 119 of file intel8x0m.c.

#define ICH_REG_GLOB_STA 0x40 /* dword - global status */

Definition at line 127 of file intel8x0m.c.

#define ICH_REG_LVI_MASK 0x1f

Definition at line 98 of file intel8x0m.c.

#define ICH_REG_PIV_MASK 0x1f /* mask */

Definition at line 108 of file intel8x0m.c.

#define ICH_RESETREGS 0x02 /* reset busmaster registers */

Definition at line 114 of file intel8x0m.c.

#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */

Definition at line 134 of file intel8x0m.c.

#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */

Definition at line 144 of file intel8x0m.c.

#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */

Definition at line 131 of file intel8x0m.c.

#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */

Definition at line 142 of file intel8x0m.c.

#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */

Definition at line 121 of file intel8x0m.c.

#define ICH_STARTBM 0x01 /* start busmaster operation */

Definition at line 115 of file intel8x0m.c.

#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */

Definition at line 129 of file intel8x0m.c.

#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */

Definition at line 128 of file intel8x0m.c.

#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */

Definition at line 120 of file intel8x0m.c.

#define ICHREG ( x ) ICH_REG_##x

Definition at line 79 of file intel8x0m.c.

#define INTEL8X0M_PM_OPS NULL

Definition at line 1069 of file intel8x0m.c.

#define snd_intel8x0m_proc_init ( chip )

Definition at line 1101 of file intel8x0m.c.

Enumeration Type Documentation

anonymous enum

Enumerator:

DEVICE_INTEL
DEVICE_SIS
DEVICE_ALI
DEVICE_NFORCE

Definition at line 77 of file intel8x0m.c.

anonymous enum

Enumerator:

ICHD_MDMIN
ICHD_MDMOUT
ICHD_MDMLAST

Definition at line 163 of file intel8x0m.c.

anonymous enum

Enumerator:

ALID_MDMIN
ALID_MDMOUT
ALID_MDMLAST

Definition at line 164 of file intel8x0m.c.

Function Documentation

DEFINE_REGSET	(	OFF	,
		0
	)

MODULE_AUTHOR ( "Jaroslav Kysela <[email protected]>" )

MODULE_DESCRIPTION	(	"Intel	82801AA,
		82901AB	,
		i810	,
		i820	,
		i830	,
		i840	,
		i845	,
		MX440;""SiS 7013;NVidia MCP/2/2S/3 modems"
	)

MODULE_DEVICE_TABLE	(	pci	,
		snd_intel8x0m_ids
	)

MODULE_LICENSE ( "GPL" )

module_param	(	index	,
		int	,
		0444
	)

module_param	(	id	,
		charp	,
		0444
	)

module_param	(	ac97_clock	,
		int	,
		0444
	)

module_param	(	enable	,
		bool	,
		0444
	)

MODULE_PARM_DESC	(	index	,
		"Index value for Intel i8x0 modemcard."
	)

MODULE_PARM_DESC	(	id	,
		"ID string for Intel i8x0 modemcard."
	)

MODULE_PARM_DESC	(	ac97_clock	,
		"AC'97 codec clock (0 = auto-detect)."
	)

module_pci_driver ( intel8x0m_driver )

MODULE_SUPPORTED_DEVICE ( "{{Intel,82801AA-ICH},""{Intel,82901AB-ICH0},""{Intel,82801BA-ICH2},""{Intel,82801CA-ICH3},""{Intel,82801DB-ICH4},""{Intel,ICH5},""{Intel,ICH6},""{Intel,ICH7},""{Intel,MX440},""{SiS,7013},""{NVidia,NForce Modem},""{NVidia,NForce2 Modem},""{NVidia,NForce2s Modem},""{NVidia,NForce3 Modem},""{AMD,AMD768}}" )

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation