Data Structures
struct	intel_msic_gpio_pdata

struct	intel_msic_ocd_pdata

struct	intel_msic_platform_data

Macros
#define	INTEL_MSIC_ID0 0x000 /* RO */

#define	INTEL_MSIC_ID1 0x001 /* RO */

#define	INTEL_MSIC_IRQLVL1 0x002

#define	INTEL_MSIC_ADC1INT 0x003

#define	INTEL_MSIC_CCINT 0x004

#define	INTEL_MSIC_PWRSRCINT 0x005

#define	INTEL_MSIC_PWRSRCINT1 0x006

#define	INTEL_MSIC_CHRINT 0x007

#define	INTEL_MSIC_CHRINT1 0x008

#define	INTEL_MSIC_RTCIRQ 0x009

#define	INTEL_MSIC_GPIO0LVIRQ 0x00a

#define	INTEL_MSIC_GPIO1LVIRQ 0x00b

#define	INTEL_MSIC_GPIOHVIRQ 0x00c

#define	INTEL_MSIC_VRINT 0x00d

#define	INTEL_MSIC_OCAUDIO 0x00e

#define	INTEL_MSIC_ACCDET 0x00f

#define	INTEL_MSIC_RESETIRQ1 0x010

#define	INTEL_MSIC_RESETIRQ2 0x011

#define	INTEL_MSIC_MADC1INT 0x012

#define	INTEL_MSIC_MCCINT 0x013

#define	INTEL_MSIC_MPWRSRCINT 0x014

#define	INTEL_MSIC_MPWRSRCINT1 0x015

#define	INTEL_MSIC_MCHRINT 0x016

#define	INTEL_MSIC_MCHRINT1 0x017

#define	INTEL_MSIC_RTCIRQMASK 0x018

#define	INTEL_MSIC_GPIO0LVIRQMASK 0x019

#define	INTEL_MSIC_GPIO1LVIRQMASK 0x01a

#define	INTEL_MSIC_GPIOHVIRQMASK 0x01b

#define	INTEL_MSIC_VRINTMASK 0x01c

#define	INTEL_MSIC_OCAUDIOMASK 0x01d

#define	INTEL_MSIC_ACCDETMASK 0x01e

#define	INTEL_MSIC_RESETIRQ1MASK 0x01f

#define	INTEL_MSIC_RESETIRQ2MASK 0x020

#define	INTEL_MSIC_IRQLVL1MSK 0x021

#define	INTEL_MSIC_PBCONFIG 0x03e

#define	INTEL_MSIC_PBSTATUS 0x03f /* RO */

#define	INTEL_MSIC_GPIO0LV7CTLO 0x040

#define	INTEL_MSIC_GPIO0LV6CTLO 0x041

#define	INTEL_MSIC_GPIO0LV5CTLO 0x042

#define	INTEL_MSIC_GPIO0LV4CTLO 0x043

#define	INTEL_MSIC_GPIO0LV3CTLO 0x044

#define	INTEL_MSIC_GPIO0LV2CTLO 0x045

#define	INTEL_MSIC_GPIO0LV1CTLO 0x046

#define	INTEL_MSIC_GPIO0LV0CTLO 0x047

#define	INTEL_MSIC_GPIO1LV7CTLOS 0x048

#define	INTEL_MSIC_GPIO1LV6CTLO 0x049

#define	INTEL_MSIC_GPIO1LV5CTLO 0x04a

#define	INTEL_MSIC_GPIO1LV4CTLO 0x04b

#define	INTEL_MSIC_GPIO1LV3CTLO 0x04c

#define	INTEL_MSIC_GPIO1LV2CTLO 0x04d

#define	INTEL_MSIC_GPIO1LV1CTLO 0x04e

#define	INTEL_MSIC_GPIO1LV0CTLO 0x04f

#define	INTEL_MSIC_GPIO0LV7CTLI 0x050

#define	INTEL_MSIC_GPIO0LV6CTLI 0x051

#define	INTEL_MSIC_GPIO0LV5CTLI 0x052

#define	INTEL_MSIC_GPIO0LV4CTLI 0x053

#define	INTEL_MSIC_GPIO0LV3CTLI 0x054

#define	INTEL_MSIC_GPIO0LV2CTLI 0x055

#define	INTEL_MSIC_GPIO0LV1CTLI 0x056

#define	INTEL_MSIC_GPIO0LV0CTLI 0x057

#define	INTEL_MSIC_GPIO1LV7CTLIS 0x058

#define	INTEL_MSIC_GPIO1LV6CTLI 0x059

#define	INTEL_MSIC_GPIO1LV5CTLI 0x05a

#define	INTEL_MSIC_GPIO1LV4CTLI 0x05b

#define	INTEL_MSIC_GPIO1LV3CTLI 0x05c

#define	INTEL_MSIC_GPIO1LV2CTLI 0x05d

#define	INTEL_MSIC_GPIO1LV1CTLI 0x05e

#define	INTEL_MSIC_GPIO1LV0CTLI 0x05f

#define	INTEL_MSIC_PWM0CLKDIV1 0x061

#define	INTEL_MSIC_PWM0CLKDIV0 0x062

#define	INTEL_MSIC_PWM1CLKDIV1 0x063

#define	INTEL_MSIC_PWM1CLKDIV0 0x064

#define	INTEL_MSIC_PWM2CLKDIV1 0x065

#define	INTEL_MSIC_PWM2CLKDIV0 0x066

#define	INTEL_MSIC_PWM0DUTYCYCLE 0x067

#define	INTEL_MSIC_PWM1DUTYCYCLE 0x068

#define	INTEL_MSIC_PWM2DUTYCYCLE 0x069

#define	INTEL_MSIC_GPIO0HV3CTLO 0x06d

#define	INTEL_MSIC_GPIO0HV2CTLO 0x06e

#define	INTEL_MSIC_GPIO0HV1CTLO 0x06f

#define	INTEL_MSIC_GPIO0HV0CTLO 0x070

#define	INTEL_MSIC_GPIO1HV3CTLO 0x071

#define	INTEL_MSIC_GPIO1HV2CTLO 0x072

#define	INTEL_MSIC_GPIO1HV1CTLO 0x073

#define	INTEL_MSIC_GPIO1HV0CTLO 0x074

#define	INTEL_MSIC_GPIO0HV3CTLI 0x075

#define	INTEL_MSIC_GPIO0HV2CTLI 0x076

#define	INTEL_MSIC_GPIO0HV1CTLI 0x077

#define	INTEL_MSIC_GPIO0HV0CTLI 0x078

#define	INTEL_MSIC_GPIO1HV3CTLI 0x079

#define	INTEL_MSIC_GPIO1HV2CTLI 0x07a

#define	INTEL_MSIC_GPIO1HV1CTLI 0x07b

#define	INTEL_MSIC_GPIO1HV0CTLI 0x07c

#define	INTEL_MSIC_SVIDCTRL0 0x080

#define	INTEL_MSIC_SVIDCTRL1 0x081

#define	INTEL_MSIC_SVIDCTRL2 0x082

#define	INTEL_MSIC_SVIDTXLASTPKT3 0x083 /* RO */

#define	INTEL_MSIC_SVIDTXLASTPKT2 0x084 /* RO */

#define	INTEL_MSIC_SVIDTXLASTPKT1 0x085 /* RO */

#define	INTEL_MSIC_SVIDTXLASTPKT0 0x086 /* RO */

#define	INTEL_MSIC_SVIDPKTOUTBYTE3 0x087

#define	INTEL_MSIC_SVIDPKTOUTBYTE2 0x088

#define	INTEL_MSIC_SVIDPKTOUTBYTE1 0x089

#define	INTEL_MSIC_SVIDPKTOUTBYTE0 0x08a

#define	INTEL_MSIC_SVIDRXVPDEBUG1 0x08b

#define	INTEL_MSIC_SVIDRXVPDEBUG0 0x08c

#define	INTEL_MSIC_SVIDRXLASTPKT3 0x08d /* RO */

#define	INTEL_MSIC_SVIDRXLASTPKT2 0x08e /* RO */

#define	INTEL_MSIC_SVIDRXLASTPKT1 0x08f /* RO */

#define	INTEL_MSIC_SVIDRXLASTPKT0 0x090 /* RO */

#define	INTEL_MSIC_SVIDRXCHKSTATUS3 0x091 /* RO */

#define	INTEL_MSIC_SVIDRXCHKSTATUS2 0x092 /* RO */

#define	INTEL_MSIC_SVIDRXCHKSTATUS1 0x093 /* RO */

#define	INTEL_MSIC_SVIDRXCHKSTATUS0 0x094 /* RO */

#define	INTEL_MSIC_VCCLATCH 0x0c0

#define	INTEL_MSIC_VNNLATCH 0x0c1

#define	INTEL_MSIC_VCCCNT 0x0c2

#define	INTEL_MSIC_SMPSRAMP 0x0c3

#define	INTEL_MSIC_VNNCNT 0x0c4

#define	INTEL_MSIC_VNNAONCNT 0x0c5

#define	INTEL_MSIC_VCC122AONCNT 0x0c6

#define	INTEL_MSIC_V180AONCNT 0x0c7

#define	INTEL_MSIC_V500CNT 0x0c8

#define	INTEL_MSIC_VIHFCNT 0x0c9

#define	INTEL_MSIC_LDORAMP1 0x0ca

#define	INTEL_MSIC_LDORAMP2 0x0cb

#define	INTEL_MSIC_VCC108AONCNT 0x0cc

#define	INTEL_MSIC_VCC108ASCNT 0x0cd

#define	INTEL_MSIC_VCC108CNT 0x0ce

#define	INTEL_MSIC_VCCA100ASCNT 0x0cf

#define	INTEL_MSIC_VCCA100CNT 0x0d0

#define	INTEL_MSIC_VCC180AONCNT 0x0d1

#define	INTEL_MSIC_VCC180CNT 0x0d2

#define	INTEL_MSIC_VCC330CNT 0x0d3

#define	INTEL_MSIC_VUSB330CNT 0x0d4

#define	INTEL_MSIC_VCCSDIOCNT 0x0d5

#define	INTEL_MSIC_VPROG1CNT 0x0d6

#define	INTEL_MSIC_VPROG2CNT 0x0d7

#define	INTEL_MSIC_VEMMCSCNT 0x0d8

#define	INTEL_MSIC_VEMMC1CNT 0x0d9

#define	INTEL_MSIC_VEMMC2CNT 0x0da

#define	INTEL_MSIC_VAUDACNT 0x0db

#define	INTEL_MSIC_VHSPCNT 0x0dc

#define	INTEL_MSIC_VHSNCNT 0x0dd

#define	INTEL_MSIC_VHDMICNT 0x0de

#define	INTEL_MSIC_VOTGCNT 0x0df

#define	INTEL_MSIC_V1P35CNT 0x0e0

#define	INTEL_MSIC_V330AONCNT 0x0e1

#define	INTEL_MSIC_CHIPCNTRL 0x100 /* WO */

#define	INTEL_MSIC_ERCONFIG 0x101

#define	INTEL_MSIC_BATCURRENTLIMIT12 0x102

#define	INTEL_MSIC_BATTIMELIMIT12 0x103

#define	INTEL_MSIC_BATTIMELIMIT3 0x104

#define	INTEL_MSIC_BATTIMEDB 0x105

#define	INTEL_MSIC_BRSTCONFIGOUTPUTS 0x106

#define	INTEL_MSIC_BRSTCONFIGACTIONS 0x107

#define	INTEL_MSIC_BURSTCONTROLSTATUS 0x108

#define	INTEL_MSIC_RTCB1 0x140 /* RO */

#define	INTEL_MSIC_RTCB2 0x141 /* RO */

#define	INTEL_MSIC_RTCB3 0x142 /* RO */

#define	INTEL_MSIC_RTCB4 0x143 /* RO */

#define	INTEL_MSIC_RTCOB1 0x144

#define	INTEL_MSIC_RTCOB2 0x145

#define	INTEL_MSIC_RTCOB3 0x146

#define	INTEL_MSIC_RTCOB4 0x147

#define	INTEL_MSIC_RTCAB1 0x148

#define	INTEL_MSIC_RTCAB2 0x149

#define	INTEL_MSIC_RTCAB3 0x14a

#define	INTEL_MSIC_RTCAB4 0x14b

#define	INTEL_MSIC_RTCWAB1 0x14c

#define	INTEL_MSIC_RTCWAB2 0x14d

#define	INTEL_MSIC_RTCWAB3 0x14e

#define	INTEL_MSIC_RTCWAB4 0x14f

#define	INTEL_MSIC_RTCSC1 0x150

#define	INTEL_MSIC_RTCSC2 0x151

#define	INTEL_MSIC_RTCSC3 0x152

#define	INTEL_MSIC_RTCSC4 0x153

#define	INTEL_MSIC_RTCSTATUS 0x154 /* RO */

#define	INTEL_MSIC_RTCCONFIG1 0x155

#define	INTEL_MSIC_RTCCONFIG2 0x156

#define	INTEL_MSIC_BDTIMER 0x180

#define	INTEL_MSIC_BATTRMV 0x181

#define	INTEL_MSIC_VBUSDET 0x182

#define	INTEL_MSIC_VBUSDET1 0x183

#define	INTEL_MSIC_ADPHVDET 0x184

#define	INTEL_MSIC_ADPLVDET 0x185

#define	INTEL_MSIC_ADPDETDBDM 0x186

#define	INTEL_MSIC_LOWBATTDET 0x187

#define	INTEL_MSIC_CHRCTRL 0x188

#define	INTEL_MSIC_CHRCVOLTAGE 0x189

#define	INTEL_MSIC_CHRCCURRENT 0x18a

#define	INTEL_MSIC_SPCHARGER 0x18b

#define	INTEL_MSIC_CHRTTIME 0x18c

#define	INTEL_MSIC_CHRCTRL1 0x18d

#define	INTEL_MSIC_PWRSRCLMT 0x18e

#define	INTEL_MSIC_CHRSTWDT 0x18f

#define	INTEL_MSIC_WDTWRITE 0x190 /* WO */

#define	INTEL_MSIC_CHRSAFELMT 0x191

#define	INTEL_MSIC_SPWRSRCINT 0x192 /* RO */

#define	INTEL_MSIC_SPWRSRCINT1 0x193 /* RO */

#define	INTEL_MSIC_CHRLEDPWM 0x194

#define	INTEL_MSIC_CHRLEDCTRL 0x195

#define	INTEL_MSIC_ADC1CNTL1 0x1c0

#define	INTEL_MSIC_ADC1CNTL2 0x1c1

#define	INTEL_MSIC_ADC1CNTL3 0x1c2

#define	INTEL_MSIC_ADC1OFFSETH 0x1c3 /* RO */

#define	INTEL_MSIC_ADC1OFFSETL 0x1c4 /* RO */

#define	INTEL_MSIC_ADC1ADDR0 0x1c5

#define	INTEL_MSIC_ADC1ADDR1 0x1c6

#define	INTEL_MSIC_ADC1ADDR2 0x1c7

#define	INTEL_MSIC_ADC1ADDR3 0x1c8

#define	INTEL_MSIC_ADC1ADDR4 0x1c9

#define	INTEL_MSIC_ADC1ADDR5 0x1ca

#define	INTEL_MSIC_ADC1ADDR6 0x1cb

#define	INTEL_MSIC_ADC1ADDR7 0x1cc

#define	INTEL_MSIC_ADC1ADDR8 0x1cd

#define	INTEL_MSIC_ADC1ADDR9 0x1ce

#define	INTEL_MSIC_ADC1ADDR10 0x1cf

#define	INTEL_MSIC_ADC1ADDR11 0x1d0

#define	INTEL_MSIC_ADC1ADDR12 0x1d1

#define	INTEL_MSIC_ADC1ADDR13 0x1d2

#define	INTEL_MSIC_ADC1ADDR14 0x1d3

#define	INTEL_MSIC_ADC1SNS0H 0x1d4 /* RO */

#define	INTEL_MSIC_ADC1SNS0L 0x1d5 /* RO */

#define	INTEL_MSIC_ADC1SNS1H 0x1d6 /* RO */

#define	INTEL_MSIC_ADC1SNS1L 0x1d7 /* RO */

#define	INTEL_MSIC_ADC1SNS2H 0x1d8 /* RO */

#define	INTEL_MSIC_ADC1SNS2L 0x1d9 /* RO */

#define	INTEL_MSIC_ADC1SNS3H 0x1da /* RO */

#define	INTEL_MSIC_ADC1SNS3L 0x1db /* RO */

#define	INTEL_MSIC_ADC1SNS4H 0x1dc /* RO */

#define	INTEL_MSIC_ADC1SNS4L 0x1dd /* RO */

#define	INTEL_MSIC_ADC1SNS5H 0x1de /* RO */

#define	INTEL_MSIC_ADC1SNS5L 0x1df /* RO */

#define	INTEL_MSIC_ADC1SNS6H 0x1e0 /* RO */

#define	INTEL_MSIC_ADC1SNS6L 0x1e1 /* RO */

#define	INTEL_MSIC_ADC1SNS7H 0x1e2 /* RO */

#define	INTEL_MSIC_ADC1SNS7L 0x1e3 /* RO */

#define	INTEL_MSIC_ADC1SNS8H 0x1e4 /* RO */

#define	INTEL_MSIC_ADC1SNS8L 0x1e5 /* RO */

#define	INTEL_MSIC_ADC1SNS9H 0x1e6 /* RO */

#define	INTEL_MSIC_ADC1SNS9L 0x1e7 /* RO */

#define	INTEL_MSIC_ADC1SNS10H 0x1e8 /* RO */

#define	INTEL_MSIC_ADC1SNS10L 0x1e9 /* RO */

#define	INTEL_MSIC_ADC1SNS11H 0x1ea /* RO */

#define	INTEL_MSIC_ADC1SNS11L 0x1eb /* RO */

#define	INTEL_MSIC_ADC1SNS12H 0x1ec /* RO */

#define	INTEL_MSIC_ADC1SNS12L 0x1ed /* RO */

#define	INTEL_MSIC_ADC1SNS13H 0x1ee /* RO */

#define	INTEL_MSIC_ADC1SNS13L 0x1ef /* RO */

#define	INTEL_MSIC_ADC1SNS14H 0x1f0 /* RO */

#define	INTEL_MSIC_ADC1SNS14L 0x1f1 /* RO */

#define	INTEL_MSIC_ADC1BV0H 0x1f2 /* RO */

#define	INTEL_MSIC_ADC1BV0L 0x1f3 /* RO */

#define	INTEL_MSIC_ADC1BV1H 0x1f4 /* RO */

#define	INTEL_MSIC_ADC1BV1L 0x1f5 /* RO */

#define	INTEL_MSIC_ADC1BV2H 0x1f6 /* RO */

#define	INTEL_MSIC_ADC1BV2L 0x1f7 /* RO */

#define	INTEL_MSIC_ADC1BV3H 0x1f8 /* RO */

#define	INTEL_MSIC_ADC1BV3L 0x1f9 /* RO */

#define	INTEL_MSIC_ADC1BI0H 0x1fa /* RO */

#define	INTEL_MSIC_ADC1BI0L 0x1fb /* RO */

#define	INTEL_MSIC_ADC1BI1H 0x1fc /* RO */

#define	INTEL_MSIC_ADC1BI1L 0x1fd /* RO */

#define	INTEL_MSIC_ADC1BI2H 0x1fe /* RO */

#define	INTEL_MSIC_ADC1BI2L 0x1ff /* RO */

#define	INTEL_MSIC_ADC1BI3H 0x200 /* RO */

#define	INTEL_MSIC_ADC1BI3L 0x201 /* RO */

#define	INTEL_MSIC_CCCNTL 0x202

#define	INTEL_MSIC_CCOFFSETH 0x203 /* RO */

#define	INTEL_MSIC_CCOFFSETL 0x204 /* RO */

#define	INTEL_MSIC_CCADCHA 0x205 /* RO */

#define	INTEL_MSIC_CCADCLA 0x206 /* RO */

#define	INTEL_MSIC_AUDPLLCTRL 0x240

#define	INTEL_MSIC_DMICBUF0123 0x241

#define	INTEL_MSIC_DMICBUF45 0x242

#define	INTEL_MSIC_DMICGPO 0x244

#define	INTEL_MSIC_DMICMUX 0x245

#define	INTEL_MSIC_DMICCLK 0x246

#define	INTEL_MSIC_MICBIAS 0x247

#define	INTEL_MSIC_ADCCONFIG 0x248

#define	INTEL_MSIC_MICAMP1 0x249

#define	INTEL_MSIC_MICAMP2 0x24a

#define	INTEL_MSIC_NOISEMUX 0x24b

#define	INTEL_MSIC_AUDIOMUX12 0x24c

#define	INTEL_MSIC_AUDIOMUX34 0x24d

#define	INTEL_MSIC_AUDIOSINC 0x24e

#define	INTEL_MSIC_AUDIOTXEN 0x24f

#define	INTEL_MSIC_HSEPRXCTRL 0x250

#define	INTEL_MSIC_IHFRXCTRL 0x251

#define	INTEL_MSIC_VOICETXVOL 0x252

#define	INTEL_MSIC_SIDETONEVOL 0x253

#define	INTEL_MSIC_MUSICSHARVOL 0x254

#define	INTEL_MSIC_VOICETXCTRL 0x255

#define	INTEL_MSIC_HSMIXER 0x256

#define	INTEL_MSIC_DACCONFIG 0x257

#define	INTEL_MSIC_SOFTMUTE 0x258

#define	INTEL_MSIC_HSLVOLCTRL 0x259

#define	INTEL_MSIC_HSRVOLCTRL 0x25a

#define	INTEL_MSIC_IHFLVOLCTRL 0x25b

#define	INTEL_MSIC_IHFRVOLCTRL 0x25c

#define	INTEL_MSIC_DRIVEREN 0x25d

#define	INTEL_MSIC_LINEOUTCTRL 0x25e

#define	INTEL_MSIC_VIB1CTRL1 0x25f

#define	INTEL_MSIC_VIB1CTRL2 0x260

#define	INTEL_MSIC_VIB1CTRL3 0x261

#define	INTEL_MSIC_VIB1SPIPCM_1 0x262

#define	INTEL_MSIC_VIB1SPIPCM_2 0x263

#define	INTEL_MSIC_VIB1CTRL5 0x264

#define	INTEL_MSIC_VIB2CTRL1 0x265

#define	INTEL_MSIC_VIB2CTRL2 0x266

#define	INTEL_MSIC_VIB2CTRL3 0x267

#define	INTEL_MSIC_VIB2SPIPCM_1 0x268

#define	INTEL_MSIC_VIB2SPIPCM_2 0x269

#define	INTEL_MSIC_VIB2CTRL5 0x26a

#define	INTEL_MSIC_BTNCTRL1 0x26b

#define	INTEL_MSIC_BTNCTRL2 0x26c

#define	INTEL_MSIC_PCM1TXSLOT01 0x26d

#define	INTEL_MSIC_PCM1TXSLOT23 0x26e

#define	INTEL_MSIC_PCM1TXSLOT45 0x26f

#define	INTEL_MSIC_PCM1RXSLOT0123 0x270

#define	INTEL_MSIC_PCM1RXSLOT045 0x271

#define	INTEL_MSIC_PCM2TXSLOT01 0x272

#define	INTEL_MSIC_PCM2TXSLOT23 0x273

#define	INTEL_MSIC_PCM2TXSLOT45 0x274

#define	INTEL_MSIC_PCM2RXSLOT01 0x275

#define	INTEL_MSIC_PCM2RXSLOT23 0x276

#define	INTEL_MSIC_PCM2RXSLOT45 0x277

#define	INTEL_MSIC_PCM1CTRL1 0x278

#define	INTEL_MSIC_PCM1CTRL2 0x279

#define	INTEL_MSIC_PCM1CTRL3 0x27a

#define	INTEL_MSIC_PCM2CTRL1 0x27b

#define	INTEL_MSIC_PCM2CTRL2 0x27c

#define	INTEL_MSIC_HDMIPUEN 0x280

#define	INTEL_MSIC_HDMISTATUS 0x281 /* RO */

#define	INTEL_MSIC_IRQ_PHYS_BASE 0xffff7fc0

#define	pdev_to_intel_msic(pdev) (dev_get_drvdata(pdev->dev.parent))

Enumerations
enum	intel_msic_block { INTEL_MSIC_BLOCK_TOUCH, INTEL_MSIC_BLOCK_ADC, INTEL_MSIC_BLOCK_BATTERY, INTEL_MSIC_BLOCK_GPIO, INTEL_MSIC_BLOCK_AUDIO, INTEL_MSIC_BLOCK_HDMI, INTEL_MSIC_BLOCK_THERMAL, INTEL_MSIC_BLOCK_POWER_BTN, INTEL_MSIC_BLOCK_OCD, INTEL_MSIC_BLOCK_LAST }

Functions
int	intel_msic_reg_read (unsigned short reg, u8 *val)

int	intel_msic_reg_write (unsigned short reg, u8 val)

int	intel_msic_reg_update (unsigned short reg, u8 val, u8 mask)

int	intel_msic_bulk_read (unsigned short reg, u8 buf, size_t count)

int	intel_msic_bulk_write (unsigned short reg, u8 buf, size_t count)

int	intel_msic_irq_read (struct intel_msic msic, unsigned short reg, u8 val)

Macro Definition Documentation

#define INTEL_MSIC_ACCDET 0x00f

Definition at line 33 of file intel_msic.h.

#define INTEL_MSIC_ACCDETMASK 0x01e

Definition at line 48 of file intel_msic.h.

#define INTEL_MSIC_ADC1ADDR0 0x1c5

Definition at line 241 of file intel_msic.h.

#define INTEL_MSIC_ADC1ADDR1 0x1c6

Definition at line 242 of file intel_msic.h.

#define INTEL_MSIC_ADC1ADDR10 0x1cf

Definition at line 251 of file intel_msic.h.

#define INTEL_MSIC_ADC1ADDR11 0x1d0

Definition at line 252 of file intel_msic.h.

#define INTEL_MSIC_ADC1ADDR12 0x1d1

Definition at line 253 of file intel_msic.h.

#define INTEL_MSIC_ADC1ADDR13 0x1d2

Definition at line 254 of file intel_msic.h.

#define INTEL_MSIC_ADC1ADDR14 0x1d3

Definition at line 255 of file intel_msic.h.

#define INTEL_MSIC_ADC1ADDR2 0x1c7

Definition at line 243 of file intel_msic.h.

#define INTEL_MSIC_ADC1ADDR3 0x1c8

Definition at line 244 of file intel_msic.h.

#define INTEL_MSIC_ADC1ADDR4 0x1c9

Definition at line 245 of file intel_msic.h.

#define INTEL_MSIC_ADC1ADDR5 0x1ca

Definition at line 246 of file intel_msic.h.

#define INTEL_MSIC_ADC1ADDR6 0x1cb

Definition at line 247 of file intel_msic.h.

#define INTEL_MSIC_ADC1ADDR7 0x1cc

Definition at line 248 of file intel_msic.h.

#define INTEL_MSIC_ADC1ADDR8 0x1cd

Definition at line 249 of file intel_msic.h.

#define INTEL_MSIC_ADC1ADDR9 0x1ce

Definition at line 250 of file intel_msic.h.

#define INTEL_MSIC_ADC1BI0H 0x1fa /* RO */

Definition at line 294 of file intel_msic.h.

#define INTEL_MSIC_ADC1BI0L 0x1fb /* RO */

Definition at line 295 of file intel_msic.h.

#define INTEL_MSIC_ADC1BI1H 0x1fc /* RO */

Definition at line 296 of file intel_msic.h.

#define INTEL_MSIC_ADC1BI1L 0x1fd /* RO */

Definition at line 297 of file intel_msic.h.

#define INTEL_MSIC_ADC1BI2H 0x1fe /* RO */

Definition at line 298 of file intel_msic.h.

#define INTEL_MSIC_ADC1BI2L 0x1ff /* RO */

Definition at line 299 of file intel_msic.h.

#define INTEL_MSIC_ADC1BI3H 0x200 /* RO */

Definition at line 300 of file intel_msic.h.

#define INTEL_MSIC_ADC1BI3L 0x201 /* RO */

Definition at line 301 of file intel_msic.h.

#define INTEL_MSIC_ADC1BV0H 0x1f2 /* RO */

Definition at line 286 of file intel_msic.h.

#define INTEL_MSIC_ADC1BV0L 0x1f3 /* RO */

Definition at line 287 of file intel_msic.h.

#define INTEL_MSIC_ADC1BV1H 0x1f4 /* RO */

Definition at line 288 of file intel_msic.h.

#define INTEL_MSIC_ADC1BV1L 0x1f5 /* RO */

Definition at line 289 of file intel_msic.h.

#define INTEL_MSIC_ADC1BV2H 0x1f6 /* RO */

Definition at line 290 of file intel_msic.h.

#define INTEL_MSIC_ADC1BV2L 0x1f7 /* RO */

Definition at line 291 of file intel_msic.h.

#define INTEL_MSIC_ADC1BV3H 0x1f8 /* RO */

Definition at line 292 of file intel_msic.h.

#define INTEL_MSIC_ADC1BV3L 0x1f9 /* RO */

Definition at line 293 of file intel_msic.h.

#define INTEL_MSIC_ADC1CNTL1 0x1c0

Definition at line 236 of file intel_msic.h.

#define INTEL_MSIC_ADC1CNTL2 0x1c1

Definition at line 237 of file intel_msic.h.

#define INTEL_MSIC_ADC1CNTL3 0x1c2

Definition at line 238 of file intel_msic.h.

#define INTEL_MSIC_ADC1INT 0x003

Definition at line 21 of file intel_msic.h.

#define INTEL_MSIC_ADC1OFFSETH 0x1c3 /* RO */

Definition at line 239 of file intel_msic.h.

#define INTEL_MSIC_ADC1OFFSETL 0x1c4 /* RO */

Definition at line 240 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS0H 0x1d4 /* RO */

Definition at line 256 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS0L 0x1d5 /* RO */

Definition at line 257 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS10H 0x1e8 /* RO */

Definition at line 276 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS10L 0x1e9 /* RO */

Definition at line 277 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS11H 0x1ea /* RO */

Definition at line 278 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS11L 0x1eb /* RO */

Definition at line 279 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS12H 0x1ec /* RO */

Definition at line 280 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS12L 0x1ed /* RO */

Definition at line 281 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS13H 0x1ee /* RO */

Definition at line 282 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS13L 0x1ef /* RO */

Definition at line 283 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS14H 0x1f0 /* RO */

Definition at line 284 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS14L 0x1f1 /* RO */

Definition at line 285 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS1H 0x1d6 /* RO */

Definition at line 258 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS1L 0x1d7 /* RO */

Definition at line 259 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS2H 0x1d8 /* RO */

Definition at line 260 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS2L 0x1d9 /* RO */

Definition at line 261 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS3H 0x1da /* RO */

Definition at line 262 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS3L 0x1db /* RO */

Definition at line 263 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS4H 0x1dc /* RO */

Definition at line 264 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS4L 0x1dd /* RO */

Definition at line 265 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS5H 0x1de /* RO */

Definition at line 266 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS5L 0x1df /* RO */

Definition at line 267 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS6H 0x1e0 /* RO */

Definition at line 268 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS6L 0x1e1 /* RO */

Definition at line 269 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS7H 0x1e2 /* RO */

Definition at line 270 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS7L 0x1e3 /* RO */

Definition at line 271 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS8H 0x1e4 /* RO */

Definition at line 272 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS8L 0x1e5 /* RO */

Definition at line 273 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS9H 0x1e6 /* RO */

Definition at line 274 of file intel_msic.h.

#define INTEL_MSIC_ADC1SNS9L 0x1e7 /* RO */

Definition at line 275 of file intel_msic.h.

#define INTEL_MSIC_ADCCONFIG 0x248

Definition at line 316 of file intel_msic.h.

#define INTEL_MSIC_ADPDETDBDM 0x186

Definition at line 218 of file intel_msic.h.

#define INTEL_MSIC_ADPHVDET 0x184

Definition at line 216 of file intel_msic.h.

#define INTEL_MSIC_ADPLVDET 0x185

Definition at line 217 of file intel_msic.h.

#define INTEL_MSIC_AUDIOMUX12 0x24c

Definition at line 320 of file intel_msic.h.

#define INTEL_MSIC_AUDIOMUX34 0x24d

Definition at line 321 of file intel_msic.h.

#define INTEL_MSIC_AUDIOSINC 0x24e

Definition at line 322 of file intel_msic.h.

#define INTEL_MSIC_AUDIOTXEN 0x24f

Definition at line 323 of file intel_msic.h.

#define INTEL_MSIC_AUDPLLCTRL 0x240

Definition at line 309 of file intel_msic.h.

#define INTEL_MSIC_BATCURRENTLIMIT12 0x102

Definition at line 178 of file intel_msic.h.

#define INTEL_MSIC_BATTIMEDB 0x105

Definition at line 181 of file intel_msic.h.

#define INTEL_MSIC_BATTIMELIMIT12 0x103

Definition at line 179 of file intel_msic.h.

#define INTEL_MSIC_BATTIMELIMIT3 0x104

Definition at line 180 of file intel_msic.h.

#define INTEL_MSIC_BATTRMV 0x181

Definition at line 213 of file intel_msic.h.

#define INTEL_MSIC_BDTIMER 0x180

Definition at line 212 of file intel_msic.h.

#define INTEL_MSIC_BRSTCONFIGACTIONS 0x107

Definition at line 183 of file intel_msic.h.

#define INTEL_MSIC_BRSTCONFIGOUTPUTS 0x106

Definition at line 182 of file intel_msic.h.

#define INTEL_MSIC_BTNCTRL1 0x26b

Definition at line 351 of file intel_msic.h.

#define INTEL_MSIC_BTNCTRL2 0x26c

Definition at line 352 of file intel_msic.h.

#define INTEL_MSIC_BURSTCONTROLSTATUS 0x108

Definition at line 184 of file intel_msic.h.

#define INTEL_MSIC_CCADCHA 0x205 /* RO */

Definition at line 305 of file intel_msic.h.

#define INTEL_MSIC_CCADCLA 0x206 /* RO */

Definition at line 306 of file intel_msic.h.

#define INTEL_MSIC_CCCNTL 0x202

Definition at line 302 of file intel_msic.h.

#define INTEL_MSIC_CCINT 0x004

Definition at line 22 of file intel_msic.h.

#define INTEL_MSIC_CCOFFSETH 0x203 /* RO */

Definition at line 303 of file intel_msic.h.

#define INTEL_MSIC_CCOFFSETL 0x204 /* RO */

Definition at line 304 of file intel_msic.h.

#define INTEL_MSIC_CHIPCNTRL 0x100 /* WO */

Definition at line 174 of file intel_msic.h.

#define INTEL_MSIC_CHRCCURRENT 0x18a

Definition at line 222 of file intel_msic.h.

#define INTEL_MSIC_CHRCTRL 0x188

Definition at line 220 of file intel_msic.h.

#define INTEL_MSIC_CHRCTRL1 0x18d

Definition at line 225 of file intel_msic.h.

#define INTEL_MSIC_CHRCVOLTAGE 0x189

Definition at line 221 of file intel_msic.h.

#define INTEL_MSIC_CHRINT 0x007

Definition at line 25 of file intel_msic.h.

#define INTEL_MSIC_CHRINT1 0x008

Definition at line 26 of file intel_msic.h.

#define INTEL_MSIC_CHRLEDCTRL 0x195

Definition at line 233 of file intel_msic.h.

#define INTEL_MSIC_CHRLEDPWM 0x194

Definition at line 232 of file intel_msic.h.

#define INTEL_MSIC_CHRSAFELMT 0x191

Definition at line 229 of file intel_msic.h.

#define INTEL_MSIC_CHRSTWDT 0x18f

Definition at line 227 of file intel_msic.h.

#define INTEL_MSIC_CHRTTIME 0x18c

Definition at line 224 of file intel_msic.h.

#define INTEL_MSIC_DACCONFIG 0x257

Definition at line 331 of file intel_msic.h.

#define INTEL_MSIC_DMICBUF0123 0x241

Definition at line 310 of file intel_msic.h.

#define INTEL_MSIC_DMICBUF45 0x242

Definition at line 311 of file intel_msic.h.

#define INTEL_MSIC_DMICCLK 0x246

Definition at line 314 of file intel_msic.h.

#define INTEL_MSIC_DMICGPO 0x244

Definition at line 312 of file intel_msic.h.

#define INTEL_MSIC_DMICMUX 0x245

Definition at line 313 of file intel_msic.h.

#define INTEL_MSIC_DRIVEREN 0x25d

Definition at line 337 of file intel_msic.h.

#define INTEL_MSIC_ERCONFIG 0x101

Definition at line 175 of file intel_msic.h.

#define INTEL_MSIC_GPIO0HV0CTLI 0x078

Definition at line 108 of file intel_msic.h.

#define INTEL_MSIC_GPIO0HV0CTLO 0x070

Definition at line 100 of file intel_msic.h.

#define INTEL_MSIC_GPIO0HV1CTLI 0x077

Definition at line 107 of file intel_msic.h.

#define INTEL_MSIC_GPIO0HV1CTLO 0x06f

Definition at line 99 of file intel_msic.h.

#define INTEL_MSIC_GPIO0HV2CTLI 0x076

Definition at line 106 of file intel_msic.h.

#define INTEL_MSIC_GPIO0HV2CTLO 0x06e

Definition at line 98 of file intel_msic.h.

#define INTEL_MSIC_GPIO0HV3CTLI 0x075

Definition at line 105 of file intel_msic.h.

#define INTEL_MSIC_GPIO0HV3CTLO 0x06d

Definition at line 97 of file intel_msic.h.

#define INTEL_MSIC_GPIO0LV0CTLI 0x057

Definition at line 79 of file intel_msic.h.

#define INTEL_MSIC_GPIO0LV0CTLO 0x047

Definition at line 63 of file intel_msic.h.

#define INTEL_MSIC_GPIO0LV1CTLI 0x056

Definition at line 78 of file intel_msic.h.

#define INTEL_MSIC_GPIO0LV1CTLO 0x046

Definition at line 62 of file intel_msic.h.

#define INTEL_MSIC_GPIO0LV2CTLI 0x055

Definition at line 77 of file intel_msic.h.

#define INTEL_MSIC_GPIO0LV2CTLO 0x045

Definition at line 61 of file intel_msic.h.

#define INTEL_MSIC_GPIO0LV3CTLI 0x054

Definition at line 76 of file intel_msic.h.

#define INTEL_MSIC_GPIO0LV3CTLO 0x044

Definition at line 60 of file intel_msic.h.

#define INTEL_MSIC_GPIO0LV4CTLI 0x053

Definition at line 75 of file intel_msic.h.

#define INTEL_MSIC_GPIO0LV4CTLO 0x043

Definition at line 59 of file intel_msic.h.

#define INTEL_MSIC_GPIO0LV5CTLI 0x052

Definition at line 74 of file intel_msic.h.

#define INTEL_MSIC_GPIO0LV5CTLO 0x042

Definition at line 58 of file intel_msic.h.

#define INTEL_MSIC_GPIO0LV6CTLI 0x051

Definition at line 73 of file intel_msic.h.

#define INTEL_MSIC_GPIO0LV6CTLO 0x041

Definition at line 57 of file intel_msic.h.

#define INTEL_MSIC_GPIO0LV7CTLI 0x050

Definition at line 72 of file intel_msic.h.

#define INTEL_MSIC_GPIO0LV7CTLO 0x040

Definition at line 56 of file intel_msic.h.

#define INTEL_MSIC_GPIO0LVIRQ 0x00a

Definition at line 28 of file intel_msic.h.

#define INTEL_MSIC_GPIO0LVIRQMASK 0x019

Definition at line 43 of file intel_msic.h.

#define INTEL_MSIC_GPIO1HV0CTLI 0x07c

Definition at line 112 of file intel_msic.h.

#define INTEL_MSIC_GPIO1HV0CTLO 0x074

Definition at line 104 of file intel_msic.h.

#define INTEL_MSIC_GPIO1HV1CTLI 0x07b

Definition at line 111 of file intel_msic.h.

#define INTEL_MSIC_GPIO1HV1CTLO 0x073

Definition at line 103 of file intel_msic.h.

#define INTEL_MSIC_GPIO1HV2CTLI 0x07a

Definition at line 110 of file intel_msic.h.

#define INTEL_MSIC_GPIO1HV2CTLO 0x072

Definition at line 102 of file intel_msic.h.

#define INTEL_MSIC_GPIO1HV3CTLI 0x079

Definition at line 109 of file intel_msic.h.

#define INTEL_MSIC_GPIO1HV3CTLO 0x071

Definition at line 101 of file intel_msic.h.

#define INTEL_MSIC_GPIO1LV0CTLI 0x05f

Definition at line 87 of file intel_msic.h.

#define INTEL_MSIC_GPIO1LV0CTLO 0x04f

Definition at line 71 of file intel_msic.h.

#define INTEL_MSIC_GPIO1LV1CTLI 0x05e

Definition at line 86 of file intel_msic.h.

#define INTEL_MSIC_GPIO1LV1CTLO 0x04e

Definition at line 70 of file intel_msic.h.

#define INTEL_MSIC_GPIO1LV2CTLI 0x05d

Definition at line 85 of file intel_msic.h.

#define INTEL_MSIC_GPIO1LV2CTLO 0x04d

Definition at line 69 of file intel_msic.h.

#define INTEL_MSIC_GPIO1LV3CTLI 0x05c

Definition at line 84 of file intel_msic.h.

#define INTEL_MSIC_GPIO1LV3CTLO 0x04c

Definition at line 68 of file intel_msic.h.

#define INTEL_MSIC_GPIO1LV4CTLI 0x05b

Definition at line 83 of file intel_msic.h.

#define INTEL_MSIC_GPIO1LV4CTLO 0x04b

Definition at line 67 of file intel_msic.h.

#define INTEL_MSIC_GPIO1LV5CTLI 0x05a

Definition at line 82 of file intel_msic.h.

#define INTEL_MSIC_GPIO1LV5CTLO 0x04a

Definition at line 66 of file intel_msic.h.

#define INTEL_MSIC_GPIO1LV6CTLI 0x059

Definition at line 81 of file intel_msic.h.

#define INTEL_MSIC_GPIO1LV6CTLO 0x049

Definition at line 65 of file intel_msic.h.

#define INTEL_MSIC_GPIO1LV7CTLIS 0x058

Definition at line 80 of file intel_msic.h.

#define INTEL_MSIC_GPIO1LV7CTLOS 0x048

Definition at line 64 of file intel_msic.h.

#define INTEL_MSIC_GPIO1LVIRQ 0x00b

Definition at line 29 of file intel_msic.h.

#define INTEL_MSIC_GPIO1LVIRQMASK 0x01a

Definition at line 44 of file intel_msic.h.

#define INTEL_MSIC_GPIOHVIRQ 0x00c

Definition at line 30 of file intel_msic.h.

#define INTEL_MSIC_GPIOHVIRQMASK 0x01b

Definition at line 45 of file intel_msic.h.

#define INTEL_MSIC_HDMIPUEN 0x280

Definition at line 371 of file intel_msic.h.

#define INTEL_MSIC_HDMISTATUS 0x281 /* RO */

Definition at line 372 of file intel_msic.h.

#define INTEL_MSIC_HSEPRXCTRL 0x250

Definition at line 324 of file intel_msic.h.

#define INTEL_MSIC_HSLVOLCTRL 0x259

Definition at line 333 of file intel_msic.h.

#define INTEL_MSIC_HSMIXER 0x256

Definition at line 330 of file intel_msic.h.

#define INTEL_MSIC_HSRVOLCTRL 0x25a

Definition at line 334 of file intel_msic.h.

#define INTEL_MSIC_ID0 0x000 /* RO */

Definition at line 16 of file intel_msic.h.

#define INTEL_MSIC_ID1 0x001 /* RO */

Definition at line 17 of file intel_msic.h.

#define INTEL_MSIC_IHFLVOLCTRL 0x25b

Definition at line 335 of file intel_msic.h.

#define INTEL_MSIC_IHFRVOLCTRL 0x25c

Definition at line 336 of file intel_msic.h.

#define INTEL_MSIC_IHFRXCTRL 0x251

Definition at line 325 of file intel_msic.h.

#define INTEL_MSIC_IRQ_PHYS_BASE 0xffff7fc0

Definition at line 375 of file intel_msic.h.

#define INTEL_MSIC_IRQLVL1 0x002

Definition at line 20 of file intel_msic.h.

#define INTEL_MSIC_IRQLVL1MSK 0x021

Definition at line 51 of file intel_msic.h.

#define INTEL_MSIC_LDORAMP1 0x0ca

Definition at line 148 of file intel_msic.h.

#define INTEL_MSIC_LDORAMP2 0x0cb

Definition at line 149 of file intel_msic.h.

#define INTEL_MSIC_LINEOUTCTRL 0x25e

Definition at line 338 of file intel_msic.h.

#define INTEL_MSIC_LOWBATTDET 0x187

Definition at line 219 of file intel_msic.h.

#define INTEL_MSIC_MADC1INT 0x012

Definition at line 36 of file intel_msic.h.

#define INTEL_MSIC_MCCINT 0x013

Definition at line 37 of file intel_msic.h.

#define INTEL_MSIC_MCHRINT 0x016

Definition at line 40 of file intel_msic.h.

#define INTEL_MSIC_MCHRINT1 0x017

Definition at line 41 of file intel_msic.h.

#define INTEL_MSIC_MICAMP1 0x249

Definition at line 317 of file intel_msic.h.

#define INTEL_MSIC_MICAMP2 0x24a

Definition at line 318 of file intel_msic.h.

#define INTEL_MSIC_MICBIAS 0x247

Definition at line 315 of file intel_msic.h.

#define INTEL_MSIC_MPWRSRCINT 0x014

Definition at line 38 of file intel_msic.h.

#define INTEL_MSIC_MPWRSRCINT1 0x015

Definition at line 39 of file intel_msic.h.

#define INTEL_MSIC_MUSICSHARVOL 0x254

Definition at line 328 of file intel_msic.h.

#define INTEL_MSIC_NOISEMUX 0x24b

Definition at line 319 of file intel_msic.h.

#define INTEL_MSIC_OCAUDIO 0x00e

Definition at line 32 of file intel_msic.h.

#define INTEL_MSIC_OCAUDIOMASK 0x01d

Definition at line 47 of file intel_msic.h.

#define INTEL_MSIC_PBCONFIG 0x03e

Definition at line 52 of file intel_msic.h.

#define INTEL_MSIC_PBSTATUS 0x03f /* RO */

Definition at line 53 of file intel_msic.h.

#define INTEL_MSIC_PCM1CTRL1 0x278

Definition at line 364 of file intel_msic.h.

#define INTEL_MSIC_PCM1CTRL2 0x279

Definition at line 365 of file intel_msic.h.

#define INTEL_MSIC_PCM1CTRL3 0x27a

Definition at line 366 of file intel_msic.h.

#define INTEL_MSIC_PCM1RXSLOT0123 0x270

Definition at line 356 of file intel_msic.h.

#define INTEL_MSIC_PCM1RXSLOT045 0x271

Definition at line 357 of file intel_msic.h.

#define INTEL_MSIC_PCM1TXSLOT01 0x26d

Definition at line 353 of file intel_msic.h.

#define INTEL_MSIC_PCM1TXSLOT23 0x26e

Definition at line 354 of file intel_msic.h.

#define INTEL_MSIC_PCM1TXSLOT45 0x26f

Definition at line 355 of file intel_msic.h.

#define INTEL_MSIC_PCM2CTRL1 0x27b

Definition at line 367 of file intel_msic.h.

#define INTEL_MSIC_PCM2CTRL2 0x27c

Definition at line 368 of file intel_msic.h.

#define INTEL_MSIC_PCM2RXSLOT01 0x275

Definition at line 361 of file intel_msic.h.

#define INTEL_MSIC_PCM2RXSLOT23 0x276

Definition at line 362 of file intel_msic.h.

#define INTEL_MSIC_PCM2RXSLOT45 0x277

Definition at line 363 of file intel_msic.h.

#define INTEL_MSIC_PCM2TXSLOT01 0x272

Definition at line 358 of file intel_msic.h.

#define INTEL_MSIC_PCM2TXSLOT23 0x273

Definition at line 359 of file intel_msic.h.

#define INTEL_MSIC_PCM2TXSLOT45 0x274

Definition at line 360 of file intel_msic.h.

#define INTEL_MSIC_PWM0CLKDIV0 0x062

Definition at line 89 of file intel_msic.h.

#define INTEL_MSIC_PWM0CLKDIV1 0x061

Definition at line 88 of file intel_msic.h.

#define INTEL_MSIC_PWM0DUTYCYCLE 0x067

Definition at line 94 of file intel_msic.h.

#define INTEL_MSIC_PWM1CLKDIV0 0x064

Definition at line 91 of file intel_msic.h.

#define INTEL_MSIC_PWM1CLKDIV1 0x063

Definition at line 90 of file intel_msic.h.

#define INTEL_MSIC_PWM1DUTYCYCLE 0x068

Definition at line 95 of file intel_msic.h.

#define INTEL_MSIC_PWM2CLKDIV0 0x066

Definition at line 93 of file intel_msic.h.

#define INTEL_MSIC_PWM2CLKDIV1 0x065

Definition at line 92 of file intel_msic.h.

#define INTEL_MSIC_PWM2DUTYCYCLE 0x069

Definition at line 96 of file intel_msic.h.

#define INTEL_MSIC_PWRSRCINT 0x005

Definition at line 23 of file intel_msic.h.

#define INTEL_MSIC_PWRSRCINT1 0x006

Definition at line 24 of file intel_msic.h.

#define INTEL_MSIC_PWRSRCLMT 0x18e

Definition at line 226 of file intel_msic.h.

#define INTEL_MSIC_RESETIRQ1 0x010

Definition at line 34 of file intel_msic.h.

#define INTEL_MSIC_RESETIRQ1MASK 0x01f

Definition at line 49 of file intel_msic.h.

#define INTEL_MSIC_RESETIRQ2 0x011

Definition at line 35 of file intel_msic.h.

#define INTEL_MSIC_RESETIRQ2MASK 0x020

Definition at line 50 of file intel_msic.h.

#define INTEL_MSIC_RTCAB1 0x148

Definition at line 195 of file intel_msic.h.

#define INTEL_MSIC_RTCAB2 0x149

Definition at line 196 of file intel_msic.h.

#define INTEL_MSIC_RTCAB3 0x14a

Definition at line 197 of file intel_msic.h.

#define INTEL_MSIC_RTCAB4 0x14b

Definition at line 198 of file intel_msic.h.

#define INTEL_MSIC_RTCB1 0x140 /* RO */

Definition at line 187 of file intel_msic.h.

#define INTEL_MSIC_RTCB2 0x141 /* RO */

Definition at line 188 of file intel_msic.h.

#define INTEL_MSIC_RTCB3 0x142 /* RO */

Definition at line 189 of file intel_msic.h.

#define INTEL_MSIC_RTCB4 0x143 /* RO */

Definition at line 190 of file intel_msic.h.

#define INTEL_MSIC_RTCCONFIG1 0x155

Definition at line 208 of file intel_msic.h.

#define INTEL_MSIC_RTCCONFIG2 0x156

Definition at line 209 of file intel_msic.h.

#define INTEL_MSIC_RTCIRQ 0x009

Definition at line 27 of file intel_msic.h.

#define INTEL_MSIC_RTCIRQMASK 0x018

Definition at line 42 of file intel_msic.h.

#define INTEL_MSIC_RTCOB1 0x144

Definition at line 191 of file intel_msic.h.

#define INTEL_MSIC_RTCOB2 0x145

Definition at line 192 of file intel_msic.h.

#define INTEL_MSIC_RTCOB3 0x146

Definition at line 193 of file intel_msic.h.

#define INTEL_MSIC_RTCOB4 0x147

Definition at line 194 of file intel_msic.h.

#define INTEL_MSIC_RTCSC1 0x150

Definition at line 203 of file intel_msic.h.

#define INTEL_MSIC_RTCSC2 0x151

Definition at line 204 of file intel_msic.h.

#define INTEL_MSIC_RTCSC3 0x152

Definition at line 205 of file intel_msic.h.

#define INTEL_MSIC_RTCSC4 0x153

Definition at line 206 of file intel_msic.h.

#define INTEL_MSIC_RTCSTATUS 0x154 /* RO */

Definition at line 207 of file intel_msic.h.

#define INTEL_MSIC_RTCWAB1 0x14c

Definition at line 199 of file intel_msic.h.

#define INTEL_MSIC_RTCWAB2 0x14d

Definition at line 200 of file intel_msic.h.

#define INTEL_MSIC_RTCWAB3 0x14e

Definition at line 201 of file intel_msic.h.

#define INTEL_MSIC_RTCWAB4 0x14f

Definition at line 202 of file intel_msic.h.

#define INTEL_MSIC_SIDETONEVOL 0x253

Definition at line 327 of file intel_msic.h.

#define INTEL_MSIC_SMPSRAMP 0x0c3

Definition at line 141 of file intel_msic.h.

#define INTEL_MSIC_SOFTMUTE 0x258

Definition at line 332 of file intel_msic.h.

#define INTEL_MSIC_SPCHARGER 0x18b

Definition at line 223 of file intel_msic.h.

#define INTEL_MSIC_SPWRSRCINT 0x192 /* RO */

Definition at line 230 of file intel_msic.h.

#define INTEL_MSIC_SPWRSRCINT1 0x193 /* RO */

Definition at line 231 of file intel_msic.h.

#define INTEL_MSIC_SVIDCTRL0 0x080

Definition at line 115 of file intel_msic.h.

#define INTEL_MSIC_SVIDCTRL1 0x081

Definition at line 116 of file intel_msic.h.

#define INTEL_MSIC_SVIDCTRL2 0x082

Definition at line 117 of file intel_msic.h.

#define INTEL_MSIC_SVIDPKTOUTBYTE0 0x08a

Definition at line 125 of file intel_msic.h.

#define INTEL_MSIC_SVIDPKTOUTBYTE1 0x089

Definition at line 124 of file intel_msic.h.

#define INTEL_MSIC_SVIDPKTOUTBYTE2 0x088

Definition at line 123 of file intel_msic.h.

#define INTEL_MSIC_SVIDPKTOUTBYTE3 0x087

Definition at line 122 of file intel_msic.h.

#define INTEL_MSIC_SVIDRXCHKSTATUS0 0x094 /* RO */

Definition at line 135 of file intel_msic.h.

#define INTEL_MSIC_SVIDRXCHKSTATUS1 0x093 /* RO */

Definition at line 134 of file intel_msic.h.

#define INTEL_MSIC_SVIDRXCHKSTATUS2 0x092 /* RO */

Definition at line 133 of file intel_msic.h.

#define INTEL_MSIC_SVIDRXCHKSTATUS3 0x091 /* RO */

Definition at line 132 of file intel_msic.h.

#define INTEL_MSIC_SVIDRXLASTPKT0 0x090 /* RO */

Definition at line 131 of file intel_msic.h.

#define INTEL_MSIC_SVIDRXLASTPKT1 0x08f /* RO */

Definition at line 130 of file intel_msic.h.

#define INTEL_MSIC_SVIDRXLASTPKT2 0x08e /* RO */

Definition at line 129 of file intel_msic.h.

#define INTEL_MSIC_SVIDRXLASTPKT3 0x08d /* RO */

Definition at line 128 of file intel_msic.h.

#define INTEL_MSIC_SVIDRXVPDEBUG0 0x08c

Definition at line 127 of file intel_msic.h.

#define INTEL_MSIC_SVIDRXVPDEBUG1 0x08b

Definition at line 126 of file intel_msic.h.

#define INTEL_MSIC_SVIDTXLASTPKT0 0x086 /* RO */

Definition at line 121 of file intel_msic.h.

#define INTEL_MSIC_SVIDTXLASTPKT1 0x085 /* RO */

Definition at line 120 of file intel_msic.h.

#define INTEL_MSIC_SVIDTXLASTPKT2 0x084 /* RO */

Definition at line 119 of file intel_msic.h.

#define INTEL_MSIC_SVIDTXLASTPKT3 0x083 /* RO */

Definition at line 118 of file intel_msic.h.

#define INTEL_MSIC_V180AONCNT 0x0c7

Definition at line 145 of file intel_msic.h.

#define INTEL_MSIC_V1P35CNT 0x0e0

Definition at line 170 of file intel_msic.h.

#define INTEL_MSIC_V330AONCNT 0x0e1

Definition at line 171 of file intel_msic.h.

#define INTEL_MSIC_V500CNT 0x0c8

Definition at line 146 of file intel_msic.h.

#define INTEL_MSIC_VAUDACNT 0x0db

Definition at line 165 of file intel_msic.h.

#define INTEL_MSIC_VBUSDET 0x182

Definition at line 214 of file intel_msic.h.

#define INTEL_MSIC_VBUSDET1 0x183

Definition at line 215 of file intel_msic.h.

#define INTEL_MSIC_VCC108AONCNT 0x0cc

Definition at line 150 of file intel_msic.h.

#define INTEL_MSIC_VCC108ASCNT 0x0cd

Definition at line 151 of file intel_msic.h.

#define INTEL_MSIC_VCC108CNT 0x0ce

Definition at line 152 of file intel_msic.h.

#define INTEL_MSIC_VCC122AONCNT 0x0c6

Definition at line 144 of file intel_msic.h.

#define INTEL_MSIC_VCC180AONCNT 0x0d1

Definition at line 155 of file intel_msic.h.

#define INTEL_MSIC_VCC180CNT 0x0d2

Definition at line 156 of file intel_msic.h.

#define INTEL_MSIC_VCC330CNT 0x0d3

Definition at line 157 of file intel_msic.h.

#define INTEL_MSIC_VCCA100ASCNT 0x0cf

Definition at line 153 of file intel_msic.h.

#define INTEL_MSIC_VCCA100CNT 0x0d0

Definition at line 154 of file intel_msic.h.

#define INTEL_MSIC_VCCCNT 0x0c2

Definition at line 140 of file intel_msic.h.

#define INTEL_MSIC_VCCLATCH 0x0c0

Definition at line 138 of file intel_msic.h.

#define INTEL_MSIC_VCCSDIOCNT 0x0d5

Definition at line 159 of file intel_msic.h.

#define INTEL_MSIC_VEMMC1CNT 0x0d9

Definition at line 163 of file intel_msic.h.

#define INTEL_MSIC_VEMMC2CNT 0x0da

Definition at line 164 of file intel_msic.h.

#define INTEL_MSIC_VEMMCSCNT 0x0d8

Definition at line 162 of file intel_msic.h.

#define INTEL_MSIC_VHDMICNT 0x0de

Definition at line 168 of file intel_msic.h.

#define INTEL_MSIC_VHSNCNT 0x0dd

Definition at line 167 of file intel_msic.h.

#define INTEL_MSIC_VHSPCNT 0x0dc

Definition at line 166 of file intel_msic.h.

#define INTEL_MSIC_VIB1CTRL1 0x25f

Definition at line 339 of file intel_msic.h.

#define INTEL_MSIC_VIB1CTRL2 0x260

Definition at line 340 of file intel_msic.h.

#define INTEL_MSIC_VIB1CTRL3 0x261

Definition at line 341 of file intel_msic.h.

#define INTEL_MSIC_VIB1CTRL5 0x264

Definition at line 344 of file intel_msic.h.

#define INTEL_MSIC_VIB1SPIPCM_1 0x262

Definition at line 342 of file intel_msic.h.

#define INTEL_MSIC_VIB1SPIPCM_2 0x263

Definition at line 343 of file intel_msic.h.

#define INTEL_MSIC_VIB2CTRL1 0x265

Definition at line 345 of file intel_msic.h.

#define INTEL_MSIC_VIB2CTRL2 0x266

Definition at line 346 of file intel_msic.h.

#define INTEL_MSIC_VIB2CTRL3 0x267

Definition at line 347 of file intel_msic.h.

#define INTEL_MSIC_VIB2CTRL5 0x26a

Definition at line 350 of file intel_msic.h.

#define INTEL_MSIC_VIB2SPIPCM_1 0x268

Definition at line 348 of file intel_msic.h.

#define INTEL_MSIC_VIB2SPIPCM_2 0x269

Definition at line 349 of file intel_msic.h.

#define INTEL_MSIC_VIHFCNT 0x0c9

Definition at line 147 of file intel_msic.h.

#define INTEL_MSIC_VNNAONCNT 0x0c5

Definition at line 143 of file intel_msic.h.

#define INTEL_MSIC_VNNCNT 0x0c4

Definition at line 142 of file intel_msic.h.

#define INTEL_MSIC_VNNLATCH 0x0c1

Definition at line 139 of file intel_msic.h.

#define INTEL_MSIC_VOICETXCTRL 0x255

Definition at line 329 of file intel_msic.h.

#define INTEL_MSIC_VOICETXVOL 0x252

Definition at line 326 of file intel_msic.h.

#define INTEL_MSIC_VOTGCNT 0x0df

Definition at line 169 of file intel_msic.h.

#define INTEL_MSIC_VPROG1CNT 0x0d6

Definition at line 160 of file intel_msic.h.

#define INTEL_MSIC_VPROG2CNT 0x0d7

Definition at line 161 of file intel_msic.h.

#define INTEL_MSIC_VRINT 0x00d

Definition at line 31 of file intel_msic.h.

#define INTEL_MSIC_VRINTMASK 0x01c

Definition at line 46 of file intel_msic.h.

#define INTEL_MSIC_VUSB330CNT 0x0d4

Definition at line 158 of file intel_msic.h.

#define INTEL_MSIC_WDTWRITE 0x190 /* WO */

Definition at line 228 of file intel_msic.h.

#define pdev_to_intel_msic ( pdev ) (dev_get_drvdata(pdev->dev.parent))

Definition at line 451 of file intel_msic.h.

Enumeration Type Documentation

enum intel_msic_block

Enumerator:

INTEL_MSIC_BLOCK_TOUCH
INTEL_MSIC_BLOCK_ADC
INTEL_MSIC_BLOCK_BATTERY
INTEL_MSIC_BLOCK_GPIO
INTEL_MSIC_BLOCK_AUDIO
INTEL_MSIC_BLOCK_HDMI
INTEL_MSIC_BLOCK_THERMAL
INTEL_MSIC_BLOCK_POWER_BTN
INTEL_MSIC_BLOCK_OCD
INTEL_MSIC_BLOCK_LAST

Definition at line 397 of file intel_msic.h.

Function Documentation

int intel_msic_bulk_read	(	unsigned short *	reg,
		u8 *	buf,
		size_t	count
	)

intel_msic_bulk_read - read an array of registers : array of register addresses to read : array where the read values are placed : number of registers to read

Function reads registers from the MSIC using addresses passed in . Read values are placed in . Reads are performed atomically wrt. MSIC.

Returns %0 in case of success and negative errno in case of failure.

Function may sleep.

Definition at line 253 of file intel_msic.c.

int intel_msic_bulk_write	(	unsigned short *	reg,
		u8 *	buf,
		size_t	count
	)

intel_msic_bulk_write - write an array of values to the MSIC registers : array of registers to write : values to write to each register : number of registers to write

Function writes registers in to MSIC. Writes are performed atomically wrt MSIC. Returns %0 in case of success and negative errno in case of failure.

Function may sleep.

Definition at line 274 of file intel_msic.c.

int intel_msic_irq_read	(	struct intel_msic *	msic,
		unsigned short	reg,
		u8 *	val
	)

intel_msic_irq_read - read a register from an MSIC interrupt tree : MSIC instance : interrupt register (between INTEL_MSIC_IRQLVL1 and INTEL_MSIC_RESETIRQ2) : value of the register is placed here

This function can be used by an MSIC subdevice interrupt handler to read a register value from the MSIC interrupt tree. In this way subdevice drivers don't have to map in the interrupt tree themselves but can just call this function instead.

Function doesn't sleep and is callable from interrupt context.

Returns %-EINVAL if is outside of the allowed register region.

Definition at line 299 of file intel_msic.c.

int intel_msic_reg_read	(	unsigned short	reg,
		u8 *	val
	)

intel_msic_reg_read - read a single MSIC register : register to read : register value is placed here

Read a single register from MSIC. Returns %0 on success and negative errno in case of failure.

Function may sleep.

Definition at line 198 of file intel_msic.c.

int intel_msic_reg_update	(	unsigned short	reg,
		u8	val,
		u8	mask
	)

intel_msic_reg_update - update a single MSIC register : register to update : value to write to the register : specifies which of the bits are updated (%0 = don't update, %1 = update)

Perform an update to a register . is used to specify which bits are updated. Returns %0 in case of success and negative errno in case of failure.

Function may sleep.

Definition at line 233 of file intel_msic.c.

int intel_msic_reg_write	(	unsigned short	reg,
		u8	val
	)

intel_msic_reg_write - write a single MSIC register : register to write : value to write to that register

Write a single MSIC register. Returns 0 on success and negative errno in case of failure.

Function may sleep.

Definition at line 214 of file intel_msic.c.

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation