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iomux-mx51.h File Reference
#include <mach/iomux-v3.h>

Go to the source code of this file.

Macros

#define __NA_   0x000
 
#define MX51_UART_PAD_CTRL
 
#define MX51_I2C_PAD_CTRL
 
#define MX51_ESDHC_PAD_CTRL
 
#define MX51_USBH1_PAD_CTRL
 
#define MX51_ECSPI_PAD_CTRL
 
#define MX51_SDHCI_PAD_CTRL
 
#define MX51_GPIO_PAD_CTRL   (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
 
#define MX51_PAD_CTRL_2   (PAD_CTL_PKE | PAD_CTL_HYS)
 
#define MX51_PAD_CTRL_3   (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 
#define MX51_PAD_CTRL_4   (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
 
#define MX51_PAD_CTRL_5   (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 
#define MX51_PAD_EIM_D16__AUD4_RXFS   IOMUX_PAD(0x3f0, 0x05c, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D16__AUD5_TXD   IOMUX_PAD(0x3f0, 0x05c, 7, 0x8d8, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D16__EIM_D16   IOMUX_PAD(0x3f0, 0x05c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D16__GPIO2_0   IOMUX_PAD(0x3f0, 0x05c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_D16__I2C1_SDA   IOMUX_PAD(0x3f0, 0x05c, 0x14, 0x9b4, 0, MX51_I2C_PAD_CTRL)
 
#define MX51_PAD_EIM_D16__UART2_CTS   IOMUX_PAD(0x3f0, 0x05c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_EIM_D16__USBH2_DATA0   IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D17__AUD5_RXD   IOMUX_PAD(0x3f4, 0x060, 7, 0x8d4, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D17__EIM_D17   IOMUX_PAD(0x3f4, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D17__GPIO2_1   IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_D17__UART2_RXD   IOMUX_PAD(0x3f4, 0x060, 3, 0x9ec, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_EIM_D17__UART3_CTS   IOMUX_PAD(0x3f4, 0x060, 4, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_EIM_D17__USBH2_DATA1   IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D18__AUD5_TXC   IOMUX_PAD(0x3f8, 0x064, 7, 0x8e4, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D18__EIM_D18   IOMUX_PAD(0x3f8, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D18__GPIO2_2   IOMUX_PAD(0x3f8, 0x064, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_D18__UART2_TXD   IOMUX_PAD(0x3f8, 0x064, 3, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_EIM_D18__UART3_RTS   IOMUX_PAD(0x3f8, 0x064, 4, 0x9f0, 1, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_EIM_D18__USBH2_DATA2   IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D19__AUD4_RXC   IOMUX_PAD(0x3fc, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D19__AUD5_TXFS   IOMUX_PAD(0x3fc, 0x068, 7, 0x8e8, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D19__EIM_D19   IOMUX_PAD(0x3fc, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D19__GPIO2_3   IOMUX_PAD(0x3fc, 0x068, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_D19__I2C1_SCL   IOMUX_PAD(0x3fc, 0x068, 0x14, 0x9b0, 0, MX51_I2C_PAD_CTRL)
 
#define MX51_PAD_EIM_D19__UART2_RTS   IOMUX_PAD(0x3fc, 0x068, 3, 0x9e8, 1, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_EIM_D19__USBH2_DATA3   IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D20__AUD4_TXD   IOMUX_PAD(0x400, 0x06c, 5, 0x8c8, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D20__EIM_D20   IOMUX_PAD(0x400, 0x06c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D20__GPIO2_4   IOMUX_PAD(0x400, 0x06c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB   IOMUX_PAD(0x400, 0x06c, 4, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D20__USBH2_DATA4   IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D21__AUD4_RXD   IOMUX_PAD(0x404, 0x070, 5, 0x8c4, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D21__EIM_D21   IOMUX_PAD(0x404, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D21__GPIO2_5   IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB   IOMUX_PAD(0x404, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D21__USBH2_DATA5   IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D22__AUD4_TXC   IOMUX_PAD(0x408, 0x074, 5, 0x8cc, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D22__EIM_D22   IOMUX_PAD(0x408, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D22__GPIO2_6   IOMUX_PAD(0x408, 0x074, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_D22__USBH2_DATA6   IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D23__AUD4_TXFS   IOMUX_PAD(0x40c, 0x078, 5, 0x8d0, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D23__EIM_D23   IOMUX_PAD(0x40c, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D23__GPIO2_7   IOMUX_PAD(0x40c, 0x078, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_D23__SPDIF_OUT1   IOMUX_PAD(0x40c, 0x078, 4, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D23__USBH2_DATA7   IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D24__AUD6_RXFS   IOMUX_PAD(0x410, 0x07c, 5, 0x8f8, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D24__EIM_D24   IOMUX_PAD(0x410, 0x07c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D24__GPIO2_8   IOMUX_PAD(0x410, 0x07c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_D24__I2C2_SDA   IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL)
 
#define MX51_PAD_EIM_D24__UART3_CTS   IOMUX_PAD(0x410, 0x07c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_EIM_D24__USBOTG_DATA0   IOMUX_PAD(0x410, 0x07c, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D25__EIM_D25   IOMUX_PAD(0x414, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D25__KEY_COL6   IOMUX_PAD(0x414, 0x080, 1, 0x9c8, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D25__UART2_CTS   IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_EIM_D25__UART3_RXD   IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_EIM_D25__USBOTG_DATA1   IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D25__GPT_CMPOUT1   IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D26__EIM_D26   IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D26__KEY_COL7   IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D26__UART2_RTS   IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_EIM_D26__UART3_TXD   IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_EIM_D26__USBOTG_DATA2   IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D26__GPT_CMPOUT2   IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D27__AUD6_RXC   IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D27__EIM_D27   IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D27__GPIO2_9   IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_D27__I2C2_SCL   IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL)
 
#define MX51_PAD_EIM_D27__UART3_RTS   IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_EIM_D27__USBOTG_DATA3   IOMUX_PAD(0x41c, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D28__AUD6_TXD   IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D28__EIM_D28   IOMUX_PAD(0x420, 0x08c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D28__KEY_ROW4   IOMUX_PAD(0x420, 0x08c, 1, 0x9d0, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D28__USBOTG_DATA4   IOMUX_PAD(0x420, 0x08c, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D29__AUD6_RXD   IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D29__EIM_D29   IOMUX_PAD(0x424, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D29__KEY_ROW5   IOMUX_PAD(0x424, 0x090, 1, 0x9d4, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D29__USBOTG_DATA5   IOMUX_PAD(0x424, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D30__AUD6_TXC   IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D30__EIM_D30   IOMUX_PAD(0x428, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D30__KEY_ROW6   IOMUX_PAD(0x428, 0x094, 1, 0x9d8, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D30__USBOTG_DATA6   IOMUX_PAD(0x428, 0x094, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D31__AUD6_TXFS   IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D31__EIM_D31   IOMUX_PAD(0x42c, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D31__KEY_ROW7   IOMUX_PAD(0x42c, 0x098, 1, 0x9dc, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_D31__USBOTG_DATA7   IOMUX_PAD(0x42c, 0x098, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A16__EIM_A16   IOMUX_PAD(0x430, 0x09c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A16__GPIO2_10   IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0   IOMUX_PAD(0x430, 0x09c, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A17__EIM_A17   IOMUX_PAD(0x434, 0x0a0, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A17__GPIO2_11   IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1   IOMUX_PAD(0x434, 0x0a0, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A18__BOOT_LPB0   IOMUX_PAD(0x438, 0x0a4, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A18__EIM_A18   IOMUX_PAD(0x438, 0x0a4, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A18__GPIO2_12   IOMUX_PAD(0x438, 0x0a4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_A19__BOOT_LPB1   IOMUX_PAD(0x43c, 0x0a8, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A19__EIM_A19   IOMUX_PAD(0x43c, 0x0a8, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A19__GPIO2_13   IOMUX_PAD(0x43c, 0x0a8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_A20__BOOT_UART_SRC0   IOMUX_PAD(0x440, 0x0ac, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A20__EIM_A20   IOMUX_PAD(0x440, 0x0ac, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A20__GPIO2_14   IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_A21__BOOT_UART_SRC1   IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A21__EIM_A21   IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A21__GPIO2_15   IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_A22__EIM_A22   IOMUX_PAD(0x448, 0x0b4, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A22__GPIO2_16   IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_A23__BOOT_HPN_EN   IOMUX_PAD(0x44c, 0x0b8, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A23__EIM_A23   IOMUX_PAD(0x44c, 0x0b8, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A23__GPIO2_17   IOMUX_PAD(0x44c, 0x0b8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_A24__EIM_A24   IOMUX_PAD(0x450, 0x0bc, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A24__GPIO2_18   IOMUX_PAD(0x450, 0x0bc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_A24__USBH2_CLK   IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A25__DISP1_PIN4   IOMUX_PAD(0x454, 0x0c0, 6, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A25__EIM_A25   IOMUX_PAD(0x454, 0x0c0, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A25__GPIO2_19   IOMUX_PAD(0x454, 0x0c0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_A25__USBH2_DIR   IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A26__CSI1_DATA_EN   IOMUX_PAD(0x458, 0x0c4, 5, 0x9a0, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A26__DISP2_EXT_CLK   IOMUX_PAD(0x458, 0x0c4, 6, 0x908, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A26__EIM_A26   IOMUX_PAD(0x458, 0x0c4, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A26__GPIO2_20   IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_A26__USBH2_STP   IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A27__CSI2_DATA_EN   IOMUX_PAD(0x45c, 0x0c8, 5, 0x99c, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A27__DISP1_PIN1   IOMUX_PAD(0x45c, 0x0c8, 6, 0x9a4, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A27__EIM_A27   IOMUX_PAD(0x45c, 0x0c8, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_A27__GPIO2_21   IOMUX_PAD(0x45c, 0x0c8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_A27__USBH2_NXT   IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_EB0__EIM_EB0   IOMUX_PAD(0x460, 0x0cc, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_EB1__EIM_EB1   IOMUX_PAD(0x464, 0x0d0, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_EB2__AUD5_RXFS   IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_EB2__CSI1_D2   IOMUX_PAD(0x468, 0x0d4, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_EB2__EIM_EB2   IOMUX_PAD(0x468, 0x0d4, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_EB2__FEC_MDIO
 
#define MX51_PAD_EIM_EB2__GPIO2_22   IOMUX_PAD(0x468, 0x0d4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_EB2__GPT_CMPOUT1   IOMUX_PAD(0x468, 0x0d4, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_EB3__AUD5_RXC   IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_EB3__CSI1_D3   IOMUX_PAD(0x46c, 0x0d8, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_EB3__EIM_EB3   IOMUX_PAD(0x46c, 0x0d8, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_EB3__FEC_RDATA1   IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_EB3__GPIO2_23   IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_EB3__GPT_CMPOUT2   IOMUX_PAD(0x46c, 0x0d8, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_OE__EIM_OE   IOMUX_PAD(0x470, 0x0dc, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_OE__GPIO2_24   IOMUX_PAD(0x470, 0x0dc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS0__EIM_CS0   IOMUX_PAD(0x474, 0x0e0, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS0__GPIO2_25   IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS1__EIM_CS1   IOMUX_PAD(0x478, 0x0e4, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS1__GPIO2_26   IOMUX_PAD(0x478, 0x0e4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS2__AUD5_TXD   IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS2__CSI1_D4   IOMUX_PAD(0x47c, 0x0e8, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS2__EIM_CS2   IOMUX_PAD(0x47c, 0x0e8, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS2__FEC_RDATA2   IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS2__GPIO2_27   IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS2__USBOTG_STP   IOMUX_PAD(0x47c, 0x0e8, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS3__AUD5_RXD   IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS3__CSI1_D5   IOMUX_PAD(0x480, 0x0ec, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS3__EIM_CS3   IOMUX_PAD(0x480, 0x0ec, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS3__FEC_RDATA3   IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS3__GPIO2_28   IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS3__USBOTG_NXT   IOMUX_PAD(0x480, 0x0ec, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS4__AUD5_TXC   IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS4__CSI1_D6   IOMUX_PAD(0x484, 0x0f0, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS4__EIM_CS4   IOMUX_PAD(0x484, 0x0f0, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS4__FEC_RX_ER   IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2)
 
#define MX51_PAD_EIM_CS4__GPIO2_29   IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS4__USBOTG_CLK   IOMUX_PAD(0x484, 0x0f0, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS5__AUD5_TXFS   IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS5__CSI1_D7   IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK   IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS5__EIM_CS5   IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS5__FEC_CRS   IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2)
 
#define MX51_PAD_EIM_CS5__GPIO2_30   IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_CS5__USBOTG_DIR   IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_DTACK__EIM_DTACK   IOMUX_PAD(0x48c, 0x0f8, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_DTACK__GPIO2_31   IOMUX_PAD(0x48c, 0x0f8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_LBA__EIM_LBA   IOMUX_PAD(0x494, 0x0fc, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_LBA__GPIO3_1   IOMUX_PAD(0x494, 0x0fc, 1, 0x978, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_EIM_CRE__EIM_CRE   IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_CRE__GPIO3_2   IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_DRAM_CS1__DRAM_CS1   IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DRAM_CS1__CCM_CLKO   IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_WE_B__GPIO3_3   IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_WE_B__NANDF_WE_B   IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_WE_B__PATA_DIOW   IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_WE_B__SD3_DATA0   IOMUX_PAD(0x4e4, 0x108, 2, 0x93c, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_NANDF_RE_B__GPIO3_4   IOMUX_PAD(0x4e8, 0x10c, 3, 0x984, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RE_B__NANDF_RE_B   IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RE_B__PATA_DIOR   IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RE_B__SD3_DATA1   IOMUX_PAD(0x4e8, 0x10c, 2, 0x940, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_NANDF_ALE__GPIO3_5   IOMUX_PAD(0x4ec, 0x110, 3, 0x988, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_ALE__NANDF_ALE   IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN   IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CLE__GPIO3_6   IOMUX_PAD(0x4f0, 0x114, 3, 0x98c, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CLE__NANDF_CLE   IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CLE__PATA_RESET_B   IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_WP_B__GPIO3_7   IOMUX_PAD(0x4f4, 0x118, 3, 0x990, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_WP_B__NANDF_WP_B   IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_WP_B__PATA_DMACK   IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_WP_B__SD3_DATA2   IOMUX_PAD(0x4f4, 0x118, 2, 0x944, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB0__ECSPI2_SS1   IOMUX_PAD(0x4f8, 0x11c, 5, 0x930, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB0__GPIO3_8   IOMUX_PAD(0x4f8, 0x11c, 3, 0x994, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB0__NANDF_RB0   IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB0__PATA_DMARQ   IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB0__SD3_DATA3   IOMUX_PAD(0x4f8, 0x11c, 2, 0x948, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB1__CSPI_MOSI   IOMUX_PAD(0x4fc, 0x120, 6, 0x91c, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB1__ECSPI2_RDY   IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB1__GPIO3_9   IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB1__NANDF_RB1   IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB1__PATA_IORDY   IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB1__GPT_CMPOUT2   IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB1__SD4_CMD   IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB2__DISP2_WAIT   IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK   IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB2__FEC_COL   IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2)
 
#define MX51_PAD_NANDF_RB2__GPIO3_10   IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB2__NANDF_RB2   IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB2__GPT_CMPOUT3   IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB2__USBH3_H3_DP   IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB2__USBH3_NXT   IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB3__DISP1_WAIT   IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB3__ECSPI2_MISO   IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB3__FEC_RX_CLK   IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2)
 
#define MX51_PAD_NANDF_RB3__GPIO3_11   IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB3__NANDF_RB3   IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB3__USBH3_CLK   IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RB3__USBH3_H3_DM   IOMUX_PAD(0x504, 0x128, 0x17, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO_NAND__GPIO_NAND   IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_GPIO_NAND__PATA_INTRQ   IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS0__GPIO3_16   IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS0__NANDF_CS0   IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS1__GPIO3_17   IOMUX_PAD(0x51c, 0x134, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS1__NANDF_CS1   IOMUX_PAD(0x51c, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS2__CSPI_SCLK   IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS2__FEC_TX_ER   IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5)
 
#define MX51_PAD_NANDF_CS2__GPIO3_18   IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS2__NANDF_CS2   IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS2__PATA_CS_0   IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS2__SD4_CLK   IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
 
#define MX51_PAD_NANDF_CS2__USBH3_H1_DP   IOMUX_PAD(0x520, 0x138, 0x17, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS3__FEC_MDC   IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5)
 
#define MX51_PAD_NANDF_CS3__GPIO3_19   IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS3__NANDF_CS3   IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS3__PATA_CS_1   IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS3__SD4_DAT0   IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS3__USBH3_H1_DM   IOMUX_PAD(0x524, 0x13c, 0x17, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS4__FEC_TDATA1   IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5)
 
#define MX51_PAD_NANDF_CS4__GPIO3_20   IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS4__NANDF_CS4   IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS4__PATA_DA_0   IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS4__SD4_DAT1   IOMUX_PAD(0x528, 0x140, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS4__USBH3_STP   IOMUX_PAD(0x528, 0x140, 7, 0xa24, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS5__FEC_TDATA2   IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5)
 
#define MX51_PAD_NANDF_CS5__GPIO3_21   IOMUX_PAD(0x52c, 0x144, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS5__NANDF_CS5   IOMUX_PAD(0x52c, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS5__PATA_DA_1   IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS5__SD4_DAT2   IOMUX_PAD(0x52c, 0x144, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS5__USBH3_DIR   IOMUX_PAD(0x52c, 0x144, 7, 0xa1c, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS6__CSPI_SS3   IOMUX_PAD(0x530, 0x148, 7, 0x928, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS6__FEC_TDATA3   IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5)
 
#define MX51_PAD_NANDF_CS6__GPIO3_22   IOMUX_PAD(0x530, 0x148, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS6__NANDF_CS6   IOMUX_PAD(0x530, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS6__PATA_DA_2   IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS6__SD4_DAT3   IOMUX_PAD(0x530, 0x148, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS7__FEC_TX_EN   IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5)
 
#define MX51_PAD_NANDF_CS7__GPIO3_23   IOMUX_PAD(0x534, 0x14c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS7__NANDF_CS7   IOMUX_PAD(0x534, 0x14c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_CS7__SD3_CLK   IOMUX_PAD(0x534, 0x14c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
 
#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0   IOMUX_PAD(0x538, 0x150, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK   IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4)
 
#define MX51_PAD_NANDF_RDY_INT__GPIO3_24   IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT   IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_RDY_INT__SD3_CMD   IOMUX_PAD(0x538, 0x150, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_NANDF_D15__ECSPI2_MOSI   IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_NANDF_D15__GPIO3_25   IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D15__NANDF_D15   IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D15__PATA_DATA15   IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D15__SD3_DAT7   IOMUX_PAD(0x53c, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D14__ECSPI2_SS3   IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_NANDF_D14__GPIO3_26   IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D14__NANDF_D14   IOMUX_PAD(0x540, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D14__PATA_DATA14   IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D14__SD3_DAT6   IOMUX_PAD(0x540, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D13__ECSPI2_SS2   IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_NANDF_D13__GPIO3_27   IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D13__NANDF_D13   IOMUX_PAD(0x544, 0x15c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D13__PATA_DATA13   IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D13__SD3_DAT5   IOMUX_PAD(0x544, 0x15c, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D12__ECSPI2_SS1   IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_NANDF_D12__GPIO3_28   IOMUX_PAD(0x548, 0x160, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D12__NANDF_D12   IOMUX_PAD(0x548, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D12__PATA_DATA12   IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D12__SD3_DAT4   IOMUX_PAD(0x548, 0x160, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D11__FEC_RX_DV   IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D11__GPIO3_29   IOMUX_PAD(0x54c, 0x164, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D11__NANDF_D11   IOMUX_PAD(0x54c, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D11__PATA_DATA11   IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D11__SD3_DATA3   IOMUX_PAD(0x54c, 0x164, 5, 0x948, 1, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D10__GPIO3_30   IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D10__NANDF_D10   IOMUX_PAD(0x550, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D10__PATA_DATA10   IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D10__SD3_DATA2   IOMUX_PAD(0x550, 0x168, 5, 0x944, 1, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D9__FEC_RDATA0   IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4)
 
#define MX51_PAD_NANDF_D9__GPIO3_31   IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D9__NANDF_D9   IOMUX_PAD(0x554, 0x16c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D9__PATA_DATA9   IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D9__SD3_DATA1   IOMUX_PAD(0x554, 0x16c, 5, 0x940, 1, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D8__FEC_TDATA0   IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5)
 
#define MX51_PAD_NANDF_D8__GPIO4_0   IOMUX_PAD(0x558, 0x170, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D8__NANDF_D8   IOMUX_PAD(0x558, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D8__PATA_DATA8   IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D8__SD3_DATA0   IOMUX_PAD(0x558, 0x170, 5, 0x93c, 1, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D7__GPIO4_1   IOMUX_PAD(0x55c, 0x174, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D7__NANDF_D7   IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D7__PATA_DATA7   IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D7__USBH3_DATA0   IOMUX_PAD(0x55c, 0x174, 5, 0x9fc, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D6__GPIO4_2   IOMUX_PAD(0x560, 0x178, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D6__NANDF_D6   IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D6__PATA_DATA6   IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D6__SD4_LCTL   IOMUX_PAD(0x560, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D6__USBH3_DATA1   IOMUX_PAD(0x560, 0x178, 5, 0xa00, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D5__GPIO4_3   IOMUX_PAD(0x564, 0x17c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D5__NANDF_D5   IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D5__PATA_DATA5   IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D5__SD4_WP   IOMUX_PAD(0x564, 0x17c, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D5__USBH3_DATA2   IOMUX_PAD(0x564, 0x17c, 5, 0xa04, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D4__GPIO4_4   IOMUX_PAD(0x568, 0x180, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D4__NANDF_D4   IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D4__PATA_DATA4   IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D4__SD4_CD   IOMUX_PAD(0x568, 0x180, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D4__USBH3_DATA3   IOMUX_PAD(0x568, 0x180, 5, 0xa08, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D3__GPIO4_5   IOMUX_PAD(0x56c, 0x184, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D3__NANDF_D3   IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D3__PATA_DATA3   IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D3__SD4_DAT4   IOMUX_PAD(0x56c, 0x184, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D3__USBH3_DATA4   IOMUX_PAD(0x56c, 0x184, 5, 0xa0c, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D2__GPIO4_6   IOMUX_PAD(0x570, 0x188, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D2__NANDF_D2   IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D2__PATA_DATA2   IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D2__SD4_DAT5   IOMUX_PAD(0x570, 0x188, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D2__USBH3_DATA5   IOMUX_PAD(0x570, 0x188, 5, 0xa10, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D1__GPIO4_7   IOMUX_PAD(0x574, 0x18c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D1__NANDF_D1   IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D1__PATA_DATA1   IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D1__SD4_DAT6   IOMUX_PAD(0x574, 0x18c, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D1__USBH3_DATA6   IOMUX_PAD(0x574, 0x18c, 5, 0xa14, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D0__GPIO4_8   IOMUX_PAD(0x578, 0x190, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D0__NANDF_D0   IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D0__PATA_DATA0   IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D0__SD4_DAT7   IOMUX_PAD(0x578, 0x190, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_NANDF_D0__USBH3_DATA7   IOMUX_PAD(0x578, 0x190, 5, 0xa18, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI1_D8__CSI1_D8   IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI1_D8__GPIO3_12   IOMUX_PAD(0x57c, 0x194, 3, 0x998, 1, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_CSI1_D9__CSI1_D9   IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI1_D9__GPIO3_13   IOMUX_PAD(0x580, 0x198, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_CSI1_D10__CSI1_D10   IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI1_D11__CSI1_D11   IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI1_D12__CSI1_D12   IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI1_D13__CSI1_D13   IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI1_D14__CSI1_D14   IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI1_D15__CSI1_D15   IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI1_D16__CSI1_D16   IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI1_D17__CSI1_D17   IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI1_D18__CSI1_D18   IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI1_D19__CSI1_D19   IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC   IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI1_VSYNC__GPIO3_14   IOMUX_PAD(0x5ac, 0x1c4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC   IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI1_HSYNC__GPIO3_15   IOMUX_PAD(0x5b0, 0x1c8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK   IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI1_MCLK__CSI1_MCLK   IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI2_D12__CSI2_D12   IOMUX_PAD(0x5bc, 0x1cc, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI2_D12__GPIO4_9   IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_CSI2_D13__CSI2_D13   IOMUX_PAD(0x5c0, 0x1d0, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI2_D13__GPIO4_10   IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_CSI2_D14__CSI2_D14   IOMUX_PAD(0x5c4, 0x1d4, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI2_D15__CSI2_D15   IOMUX_PAD(0x5c8, 0x1d8, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI2_D16__CSI2_D16   IOMUX_PAD(0x5cc, 0x1dc, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI2_D17__CSI2_D17   IOMUX_PAD(0x5d0, 0x1e0, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI2_D18__CSI2_D18   IOMUX_PAD(0x5d4, 0x1e4, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI2_D18__GPIO4_11   IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_CSI2_D19__CSI2_D19   IOMUX_PAD(0x5d8, 0x1e8, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI2_D19__GPIO4_12   IOMUX_PAD(0x5d8, 0x1e8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC   IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI2_VSYNC__GPIO4_13   IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC   IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI2_HSYNC__GPIO4_14   IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK   IOMUX_PAD(0x5e4, 0x1f4, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_CSI2_PIXCLK__GPIO4_15   IOMUX_PAD(0x5e4, 0x1f4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_I2C1_CLK__GPIO4_16   IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_I2C1_CLK__I2C1_CLK   IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
 
#define MX51_PAD_I2C1_DAT__GPIO4_17   IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_I2C1_DAT__I2C1_DAT   IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
 
#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD   IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_AUD3_BB_TXD__GPIO4_18   IOMUX_PAD(0x5f0, 0x200, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD   IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_AUD3_BB_RXD__GPIO4_19   IOMUX_PAD(0x5f4, 0x204, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_AUD3_BB_RXD__UART3_RXD   IOMUX_PAD(0x5f4, 0x204, 1, 0x9f4, 2, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_AUD3_BB_CK__AUD3_TXC   IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_AUD3_BB_CK__GPIO4_20   IOMUX_PAD(0x5f8, 0x208, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS   IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_AUD3_BB_FS__GPIO4_21   IOMUX_PAD(0x5fc, 0x20c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_AUD3_BB_FS__UART3_TXD   IOMUX_PAD(0x5fc, 0x20c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI   IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_CSPI1_MOSI__GPIO4_22   IOMUX_PAD(0x600, 0x210, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_CSPI1_MOSI__I2C1_SDA   IOMUX_PAD(0x600, 0x210, 0x11, 0x9b4, 1, MX51_I2C_PAD_CTRL)
 
#define MX51_PAD_CSPI1_MISO__AUD4_RXD   IOMUX_PAD(0x604, 0x214, 1, 0x8c4, 1, NO_PAD_CTRL)
 
#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO   IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_CSPI1_MISO__GPIO4_23   IOMUX_PAD(0x604, 0x214, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_CSPI1_SS0__AUD4_TXC   IOMUX_PAD(0x608, 0x218, 1, 0x8cc, 1, NO_PAD_CTRL)
 
#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0   IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_CSPI1_SS0__GPIO4_24   IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_CSPI1_SS1__AUD4_TXD   IOMUX_PAD(0x60c, 0x21c, 1, 0x8c8, 1, NO_PAD_CTRL)
 
#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1   IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_CSPI1_SS1__GPIO4_25   IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_CSPI1_RDY__AUD4_TXFS   IOMUX_PAD(0x610, 0x220, 1, 0x8d0, 1, NO_PAD_CTRL)
 
#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY   IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_CSPI1_RDY__GPIO4_26   IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK   IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_CSPI1_SCLK__GPIO4_27   IOMUX_PAD(0x614, 0x224, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_CSPI1_SCLK__I2C1_SCL   IOMUX_PAD(0x614, 0x224, 0x11, 0x9b0, 1, MX51_I2C_PAD_CTRL)
 
#define MX51_PAD_UART1_RXD__GPIO4_28   IOMUX_PAD(0x618, 0x228, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_UART1_RXD__UART1_RXD   IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_UART1_TXD__GPIO4_29   IOMUX_PAD(0x61c, 0x22c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_UART1_TXD__PWM2_PWMO   IOMUX_PAD(0x61c, 0x22c, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_UART1_TXD__UART1_TXD   IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_UART1_RTS__GPIO4_30   IOMUX_PAD(0x620, 0x230, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_UART1_RTS__UART1_RTS   IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_UART1_CTS__GPIO4_31   IOMUX_PAD(0x624, 0x234, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_UART1_CTS__UART1_CTS   IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_UART2_RXD__FIRI_TXD   IOMUX_PAD(0x628, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_UART2_RXD__GPIO1_20   IOMUX_PAD(0x628, 0x238, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_UART2_RXD__UART2_RXD   IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_UART2_TXD__FIRI_RXD   IOMUX_PAD(0x62c, 0x23c, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_UART2_TXD__GPIO1_21   IOMUX_PAD(0x62c, 0x23c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_UART2_TXD__UART2_TXD   IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_UART3_RXD__CSI1_D0   IOMUX_PAD(0x630, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_UART3_RXD__GPIO1_22   IOMUX_PAD(0x630, 0x240, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_UART3_RXD__UART1_DTR   IOMUX_PAD(0x630, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_UART3_RXD__UART3_RXD   IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_UART3_TXD__CSI1_D1   IOMUX_PAD(0x634, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_UART3_TXD__GPIO1_23   IOMUX_PAD(0x634, 0x244, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_UART3_TXD__UART1_DSR   IOMUX_PAD(0x634, 0x244, 0, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_UART3_TXD__UART3_TXD   IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_OWIRE_LINE__GPIO1_24   IOMUX_PAD(0x638, 0x248, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_OWIRE_LINE__OWIRE_LINE   IOMUX_PAD(0x638, 0x248, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_OWIRE_LINE__SPDIF_OUT   IOMUX_PAD(0x638, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_KEY_ROW0__KEY_ROW0   IOMUX_PAD(0x63c, 0x24c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_KEY_ROW1__KEY_ROW1   IOMUX_PAD(0x640, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_KEY_ROW2__KEY_ROW2   IOMUX_PAD(0x644, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_KEY_ROW3__KEY_ROW3   IOMUX_PAD(0x648, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_KEY_COL0__KEY_COL0   IOMUX_PAD(0x64c, 0x25c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_KEY_COL0__PLL1_BYP   IOMUX_PAD(0x64c, 0x25c, 7, 0x90c, 0, NO_PAD_CTRL)
 
#define MX51_PAD_KEY_COL1__KEY_COL1   IOMUX_PAD(0x650, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_KEY_COL1__PLL2_BYP   IOMUX_PAD(0x650, 0x260, 7, 0x910, 0, NO_PAD_CTRL)
 
#define MX51_PAD_KEY_COL2__KEY_COL2   IOMUX_PAD(0x654, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_KEY_COL2__PLL3_BYP   IOMUX_PAD(0x654, 0x264, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_KEY_COL3__KEY_COL3   IOMUX_PAD(0x658, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_KEY_COL4__I2C2_SCL   IOMUX_PAD(0x65c, 0x26c, 0x13, 0x9b8, 1, MX51_I2C_PAD_CTRL)
 
#define MX51_PAD_KEY_COL4__KEY_COL4   IOMUX_PAD(0x65c, 0x26c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_KEY_COL4__SPDIF_OUT1   IOMUX_PAD(0x65c, 0x26c, 6, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_KEY_COL4__UART1_RI   IOMUX_PAD(0x65c, 0x26c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_KEY_COL4__UART3_RTS   IOMUX_PAD(0x65c, 0x26c, 2, 0x9f0, 4, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_KEY_COL5__I2C2_SDA   IOMUX_PAD(0x660, 0x270, 0x13, 0x9bc, 1, MX51_I2C_PAD_CTRL)
 
#define MX51_PAD_KEY_COL5__KEY_COL5   IOMUX_PAD(0x660, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_KEY_COL5__UART1_DCD   IOMUX_PAD(0x660, 0x270, 1, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_KEY_COL5__UART3_CTS   IOMUX_PAD(0x660, 0x270, 2, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_USBH1_CLK__CSPI_SCLK   IOMUX_PAD(0x678, 0x278, 1, 0x914, 1, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_USBH1_CLK__GPIO1_25   IOMUX_PAD(0x678, 0x278, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_USBH1_CLK__I2C2_SCL   IOMUX_PAD(0x678, 0x278, 0x15, 0x9b8, 2, MX51_I2C_PAD_CTRL)
 
#define MX51_PAD_USBH1_CLK__USBH1_CLK   IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
 
#define MX51_PAD_USBH1_DIR__CSPI_MOSI   IOMUX_PAD(0x67c, 0x27c, 1, 0x91c, 1, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_USBH1_DIR__GPIO1_26   IOMUX_PAD(0x67c, 0x27c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_USBH1_DIR__I2C2_SDA   IOMUX_PAD(0x67c, 0x27c, 0x15, 0x9bc, 2, MX51_I2C_PAD_CTRL)
 
#define MX51_PAD_USBH1_DIR__USBH1_DIR   IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
 
#define MX51_PAD_USBH1_STP__CSPI_RDY   IOMUX_PAD(0x680, 0x280, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_USBH1_STP__GPIO1_27   IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_USBH1_STP__UART3_RXD   IOMUX_PAD(0x680, 0x280, 5, 0x9f4, 6, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_USBH1_STP__USBH1_STP   IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
 
#define MX51_PAD_USBH1_NXT__CSPI_MISO   IOMUX_PAD(0x684, 0x284, 1, 0x918, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_USBH1_NXT__GPIO1_28   IOMUX_PAD(0x684, 0x284, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_USBH1_NXT__UART3_TXD   IOMUX_PAD(0x684, 0x284, 5, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_USBH1_NXT__USBH1_NXT   IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA0__GPIO1_11   IOMUX_PAD(0x688, 0x288, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA0__UART2_CTS   IOMUX_PAD(0x688, 0x288, 1, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA0__USBH1_DATA0   IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA1__GPIO1_12   IOMUX_PAD(0x68c, 0x28c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA1__UART2_RXD   IOMUX_PAD(0x68c, 0x28c, 1, 0x9ec, 4, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA1__USBH1_DATA1   IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA2__GPIO1_13   IOMUX_PAD(0x690, 0x290, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA2__UART2_TXD   IOMUX_PAD(0x690, 0x290, 1, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA2__USBH1_DATA2   IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA3__GPIO1_14   IOMUX_PAD(0x694, 0x294, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA3__UART2_RTS   IOMUX_PAD(0x694, 0x294, 1, 0x9e8, 5, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA3__USBH1_DATA3   IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA4__CSPI_SS0   IOMUX_PAD(0x698, 0x298, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA4__GPIO1_15   IOMUX_PAD(0x698, 0x298, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA4__USBH1_DATA4   IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA5__CSPI_SS1   IOMUX_PAD(0x69c, 0x29c, 1, 0x920, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA5__GPIO1_16   IOMUX_PAD(0x69c, 0x29c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA5__USBH1_DATA5   IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA6__CSPI_SS3   IOMUX_PAD(0x6a0, 0x2a0, 1, 0x928, 1, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA6__GPIO1_17   IOMUX_PAD(0x6a0, 0x2a0, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA6__USBH1_DATA6   IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3   IOMUX_PAD(0x6a4, 0x2a4, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3   IOMUX_PAD(0x6a4, 0x2a4, 5, 0x934, 1, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA7__GPIO1_18   IOMUX_PAD(0x6a4, 0x2a4, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_USBH1_DATA7__USBH1_DATA7   IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
 
#define MX51_PAD_DI1_PIN11__DI1_PIN11   IOMUX_PAD(0x6a8, 0x2a8, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI1_PIN11__ECSPI1_SS2   IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_DI1_PIN11__GPIO3_0   IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_DI1_PIN12__DI1_PIN12   IOMUX_PAD(0x6ac, 0x2ac, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI1_PIN12__GPIO3_1   IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_DI1_PIN13__DI1_PIN13   IOMUX_PAD(0x6b0, 0x2b0, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI1_PIN13__GPIO3_2   IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_DI1_D0_CS__DI1_D0_CS   IOMUX_PAD(0x6b4, 0x2b4, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI1_D0_CS__GPIO3_3   IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_DI1_D1_CS__DI1_D1_CS   IOMUX_PAD(0x6b8, 0x2b8, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI1_D1_CS__DISP1_PIN14   IOMUX_PAD(0x6b8, 0x2b8, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI1_D1_CS__DISP1_PIN5   IOMUX_PAD(0x6b8, 0x2b8, 3, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI1_D1_CS__GPIO3_4   IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1   IOMUX_PAD(0x6bc, 0x2bc, 2, 0x9a4, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN   IOMUX_PAD(0x6bc, 0x2bc, 0, 0x9c4, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5   IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6   IOMUX_PAD(0x6c0, 0x2c0, 3, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO   IOMUX_PAD(0x6c0, 0x2c0, 0, 0x9c4, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6   IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17   IOMUX_PAD(0x6c4, 0x2c4, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7   IOMUX_PAD(0x6c4, 0x2c4, 3, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK   IOMUX_PAD(0x6c4, 0x2c4, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7   IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK   IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16   IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8   IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISPB2_SER_RS__GPIO3_8   IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT0__DISP1_DAT0   IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT1__DISP1_DAT1   IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT2__DISP1_DAT2   IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT3__DISP1_DAT3   IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT4__DISP1_DAT4   IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT5__DISP1_DAT5   IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC   IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT6__DISP1_DAT6   IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG   IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT7__DISP1_DAT7   IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT8__BOOT_SRC0   IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT8__DISP1_DAT8   IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT9__BOOT_SRC1   IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT9__DISP1_DAT9   IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE   IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT10__DISP1_DAT10   IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2   IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT11__DISP1_DAT11   IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL   IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT12__DISP1_DAT12   IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0   IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT13__DISP1_DAT13   IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1   IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT14__DISP1_DAT14   IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH   IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT15__DISP1_DAT15   IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0   IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT16__DISP1_DAT16   IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1   IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT17__DISP1_DAT17   IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0   IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT18__DISP1_DAT18   IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT18__DISP2_PIN11   IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT18__DISP2_PIN5   IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1   IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT19__DISP1_DAT19   IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT19__DISP2_PIN12   IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT19__DISP2_PIN6   IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0   IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT20__DISP1_DAT20   IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT20__DISP2_PIN13   IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT20__DISP2_PIN7   IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1   IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT21__DISP1_DAT21   IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT21__DISP2_PIN14   IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT21__DISP2_PIN8   IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0   IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT22__DISP1_DAT22   IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS   IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT22__DISP2_DAT16   IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1   IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT23__DISP1_DAT23   IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS   IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT23__DISP2_DAT17   IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS   IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI1_PIN3__DI1_PIN3   IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK   IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI1_PIN2__DI1_PIN2   IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI1_PIN15__DI1_PIN15   IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI_GP2__DISP1_SER_CLK   IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI_GP2__DISP2_WAIT   IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DI_GP3__CSI1_DATA_EN   IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DI_GP3__DISP1_SER_DIO   IOMUX_PAD(0x744, 0x33c, 0, 0x9c0, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI_GP3__FEC_TX_ER   IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5)
 
#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN   IOMUX_PAD(0x748, 0x340, 3, 0x99c, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DI2_PIN4__DI2_PIN4   IOMUX_PAD(0x748, 0x340, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI2_PIN4__FEC_CRS   IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DI2_PIN2__DI2_PIN2   IOMUX_PAD(0x74c, 0x344, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI2_PIN2__FEC_MDC   IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5)
 
#define MX51_PAD_DI2_PIN3__DI2_PIN3   IOMUX_PAD(0x750, 0x348, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI2_PIN3__FEC_MDIO   IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK   IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1   IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DI_GP4__DI2_PIN15   IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI_GP4__DISP1_SER_DIN   IOMUX_PAD(0x758, 0x350, 0, 0x9c0, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DI_GP4__DISP2_PIN1   IOMUX_PAD(0x758, 0x350, 3, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DI_GP4__FEC_RDATA2   IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT0__DISP2_DAT0   IOMUX_PAD(0x75c, 0x354, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT0__FEC_RDATA3   IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT0__KEY_COL6   IOMUX_PAD(0x75c, 0x354, 4, 0x9c8, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT0__UART3_RXD   IOMUX_PAD(0x75c, 0x354, 5, 0x9f4, 8, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT0__USBH3_CLK   IOMUX_PAD(0x75c, 0x354, 3, 0x9f8, 1, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT1__DISP2_DAT1   IOMUX_PAD(0x760, 0x358, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT1__FEC_RX_ER   IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT1__KEY_COL7   IOMUX_PAD(0x760, 0x358, 4, 0x9cc, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT1__UART3_TXD   IOMUX_PAD(0x760, 0x358, 5, __NA_, 0, MX51_UART_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT1__USBH3_DIR   IOMUX_PAD(0x760, 0x358, 3, 0xa1c, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT2__DISP2_DAT2   IOMUX_PAD(0x764, 0x35c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT3__DISP2_DAT3   IOMUX_PAD(0x768, 0x360, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT4__DISP2_DAT4   IOMUX_PAD(0x76c, 0x364, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT5__DISP2_DAT5   IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT6__DISP2_DAT6   IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT6__FEC_TDATA1   IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5)
 
#define MX51_PAD_DISP2_DAT6__GPIO1_19   IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT6__KEY_ROW4   IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT6__USBH3_STP   IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT7__DISP2_DAT7   IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT7__FEC_TDATA2   IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5)
 
#define MX51_PAD_DISP2_DAT7__GPIO1_29   IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT7__KEY_ROW5   IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT7__USBH3_NXT   IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT8__DISP2_DAT8   IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT8__FEC_TDATA3   IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5)
 
#define MX51_PAD_DISP2_DAT8__GPIO1_30   IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT8__KEY_ROW6   IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT8__USBH3_DATA0   IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT9__AUD6_RXC   IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT9__DISP2_DAT9   IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT9__FEC_TX_EN   IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5)
 
#define MX51_PAD_DISP2_DAT9__GPIO1_31   IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT9__USBH3_DATA1   IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT10__DISP2_DAT10   IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS   IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT10__FEC_COL   IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT10__KEY_ROW7   IOMUX_PAD(0x784, 0x37c, 4, 0x9dc, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT10__USBH3_DATA2   IOMUX_PAD(0x784, 0x37c, 3, 0xa04, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT11__AUD6_TXD   IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT11__DISP2_DAT11   IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK   IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT11__GPIO1_10   IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT11__USBH3_DATA3   IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT12__AUD6_RXD   IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT12__DISP2_DAT12   IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT12__FEC_RX_DV   IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT12__USBH3_DATA4   IOMUX_PAD(0x78c, 0x384, 3, 0xa0c, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT13__AUD6_TXC   IOMUX_PAD(0x790, 0x388, 4, 0x8fc, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT13__DISP2_DAT13   IOMUX_PAD(0x790, 0x388, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK   IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4)
 
#define MX51_PAD_DISP2_DAT13__USBH3_DATA5   IOMUX_PAD(0x790, 0x388, 3, 0xa10, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT14__AUD6_TXFS   IOMUX_PAD(0x794, 0x38c, 4, 0x900, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT14__DISP2_DAT14   IOMUX_PAD(0x794, 0x38c, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT14__FEC_RDATA0   IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4)
 
#define MX51_PAD_DISP2_DAT14__USBH3_DATA6   IOMUX_PAD(0x794, 0x38c, 3, 0xa14, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT15__AUD6_RXFS   IOMUX_PAD(0x798, 0x390, 4, 0x8f8, 1, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS   IOMUX_PAD(0x798, 0x390, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT15__DISP2_DAT15   IOMUX_PAD(0x798, 0x390, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_DISP2_DAT15__FEC_TDATA0   IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5)
 
#define MX51_PAD_DISP2_DAT15__USBH3_DATA7   IOMUX_PAD(0x798, 0x390, 3, 0xa18, 1, NO_PAD_CTRL)
 
#define MX51_PAD_SD1_CMD__AUD5_RXFS   IOMUX_PAD(0x79c, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)
 
#define MX51_PAD_SD1_CMD__CSPI_MOSI   IOMUX_PAD(0x79c, 0x394, 2, 0x91c, 2, NO_PAD_CTRL)
 
#define MX51_PAD_SD1_CMD__SD1_CMD   IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_SD1_CLK__AUD5_RXC   IOMUX_PAD(0x7a0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)
 
#define MX51_PAD_SD1_CLK__CSPI_SCLK   IOMUX_PAD(0x7a0, 0x398, 2, 0x914, 2, NO_PAD_CTRL)
 
#define MX51_PAD_SD1_CLK__SD1_CLK   IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
 
#define MX51_PAD_SD1_DATA0__AUD5_TXD   IOMUX_PAD(0x7a4, 0x39c, 1, 0x8d8, 2, NO_PAD_CTRL)
 
#define MX51_PAD_SD1_DATA0__CSPI_MISO   IOMUX_PAD(0x7a4, 0x39c, 2, 0x918, 1, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_SD1_DATA0__SD1_DATA0   IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_EIM_DA0__EIM_DA0   IOMUX_PAD(__NA_, 0x01c, 0, 0x000, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_DA1__EIM_DA1   IOMUX_PAD(__NA_, 0x020, 0, 0x000, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_DA2__EIM_DA2   IOMUX_PAD(__NA_, 0x024, 0, 0x000, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_DA3__EIM_DA3   IOMUX_PAD(__NA_, 0x028, 0, 0x000, 0, NO_PAD_CTRL)
 
#define MX51_PAD_SD1_DATA1__AUD5_RXD   IOMUX_PAD(0x7a8, 0x3a0, 1, 0x8d4, 2, NO_PAD_CTRL)
 
#define MX51_PAD_SD1_DATA1__SD1_DATA1   IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_EIM_DA4__EIM_DA4   IOMUX_PAD(__NA_, 0x02c, 0, 0x000, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_DA5__EIM_DA5   IOMUX_PAD(__NA_, 0x030, 0, 0x000, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_DA6__EIM_DA6   IOMUX_PAD(__NA_, 0x034, 0, 0x000, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_DA7__EIM_DA7   IOMUX_PAD(__NA_, 0x038, 0, 0x000, 0, NO_PAD_CTRL)
 
#define MX51_PAD_SD1_DATA2__AUD5_TXC   IOMUX_PAD(0x7ac, 0x3a4, 1, 0x8e4, 2, NO_PAD_CTRL)
 
#define MX51_PAD_SD1_DATA2__SD1_DATA2   IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_EIM_DA10__EIM_DA10   IOMUX_PAD(__NA_, 0x044, 0, 0x000, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_DA11__EIM_DA11   IOMUX_PAD(__NA_, 0x048, 0, 0x000, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_DA8__EIM_DA8   IOMUX_PAD(__NA_, 0x03c, 0, 0x000, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_DA9__EIM_DA9   IOMUX_PAD(__NA_, 0x040, 0, 0x000, 0, NO_PAD_CTRL)
 
#define MX51_PAD_SD1_DATA3__AUD5_TXFS   IOMUX_PAD(0x7b0, 0x3a8, 1, 0x8e8, 2, NO_PAD_CTRL)
 
#define MX51_PAD_SD1_DATA3__CSPI_SS1   IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_SD1_DATA3__SD1_DATA3   IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_GPIO1_0__CSPI_SS2   IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_GPIO1_0__GPIO1_0   IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_0__SD1_CD   IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
 
#define MX51_PAD_GPIO1_1__CSPI_MISO   IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_GPIO1_1__GPIO1_1   IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_1__SD1_WP   IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
 
#define MX51_PAD_EIM_DA12__EIM_DA12   IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_DA13__EIM_DA13   IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_DA14__EIM_DA14   IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL)
 
#define MX51_PAD_EIM_DA15__EIM_DA15   IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL)
 
#define MX51_PAD_SD2_CMD__CSPI_MOSI   IOMUX_PAD(0x7bc, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_SD2_CMD__I2C1_SCL   IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL)
 
#define MX51_PAD_SD2_CMD__SD2_CMD   IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_SD2_CLK__CSPI_SCLK   IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_SD2_CLK__I2C1_SDA   IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x9b4, 2, MX51_I2C_PAD_CTRL)
 
#define MX51_PAD_SD2_CLK__SD2_CLK   IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
 
#define MX51_PAD_SD2_DATA0__CSPI_MISO   IOMUX_PAD(0x7c4, 0x3bc, 2, 0x918, 3, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_SD2_DATA0__SD1_DAT4   IOMUX_PAD(0x7c4, 0x3bc, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_SD2_DATA0__SD2_DATA0   IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_SD2_DATA1__SD1_DAT5   IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_SD2_DATA1__SD2_DATA1   IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_SD2_DATA1__USBH3_H2_DP   IOMUX_PAD(0x7c8, 0x3c0, 0x12, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_SD2_DATA2__SD1_DAT6   IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_SD2_DATA2__SD2_DATA2   IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_SD2_DATA2__USBH3_H2_DM   IOMUX_PAD(0x7cc, 0x3c4, 0x12, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_SD2_DATA3__CSPI_SS2   IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL)
 
#define MX51_PAD_SD2_DATA3__SD1_DAT7   IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_SD2_DATA3__SD2_DATA3   IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 
#define MX51_PAD_GPIO1_2__CCM_OUT_2   IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_2__GPIO1_2   IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_2__I2C2_SCL   IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL)
 
#define MX51_PAD_GPIO1_2__PLL1_BYP   IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_2__PWM1_PWMO   IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_3__GPIO1_3   IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_3__I2C2_SDA   IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL)
 
#define MX51_PAD_GPIO1_3__CCM_CLKO2   IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_3__GPT_CLKIN   IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_3__PLL2_BYP   IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_3__PWM2_PWMO   IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ   IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B   IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK   IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_4__EIM_RDY   IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_4__GPIO1_4   IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B   IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_4__GPT_CAPIN1   IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_5__CSI2_MCLK   IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_5__DISP2_PIN16   IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_5__GPIO1_5   IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B   IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_5__CCM_CLKO   IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_6__DISP2_PIN17   IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_6__GPIO1_6   IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_6__REF_EN_B   IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_6__GPT_CAPIN2   IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_7__CCM_OUT_0   IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_7__GPIO1_7   IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_7__SD2_WP   IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
 
#define MX51_PAD_GPIO1_7__SPDIF_OUT1   IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_8__CSI2_DATA_EN   IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_8__GPIO1_8   IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_8__SD2_CD   IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
 
#define MX51_PAD_GPIO1_8__USBH3_PWR   IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_8__CCM_CLKO2   IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_9__CCM_OUT_1   IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_9__DISP2_D1_CS   IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_9__DISP2_SER_CS   IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_9__GPIO1_9   IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_9__SD2_LCTL   IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_9__USBH3_OC   IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL)
 
#define MX51_PAD_GPIO1_9__CCM_CLKO   IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL)
 

Macro Definition Documentation

#define __NA_   0x000

Definition at line 17 of file iomux-mx51.h.

#define MX51_ECSPI_PAD_CTRL
Value:
PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)

Definition at line 32 of file iomux-mx51.h.

#define MX51_ESDHC_PAD_CTRL
Value:
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
PAD_CTL_HYS)

Definition at line 26 of file iomux-mx51.h.

#define MX51_GPIO_PAD_CTRL   (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)

Definition at line 37 of file iomux-mx51.h.

#define MX51_I2C_PAD_CTRL
Value:
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
PAD_CTL_HYS)

Definition at line 23 of file iomux-mx51.h.

#define MX51_PAD_AUD3_BB_CK__AUD3_TXC   IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 450 of file iomux-mx51.h.

#define MX51_PAD_AUD3_BB_CK__GPIO4_20   IOMUX_PAD(0x5f8, 0x208, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 451 of file iomux-mx51.h.

#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS   IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 452 of file iomux-mx51.h.

#define MX51_PAD_AUD3_BB_FS__GPIO4_21   IOMUX_PAD(0x5fc, 0x20c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 453 of file iomux-mx51.h.

#define MX51_PAD_AUD3_BB_FS__UART3_TXD   IOMUX_PAD(0x5fc, 0x20c, 1, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 454 of file iomux-mx51.h.

#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD   IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 447 of file iomux-mx51.h.

#define MX51_PAD_AUD3_BB_RXD__GPIO4_19   IOMUX_PAD(0x5f4, 0x204, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 448 of file iomux-mx51.h.

#define MX51_PAD_AUD3_BB_RXD__UART3_RXD   IOMUX_PAD(0x5f4, 0x204, 1, 0x9f4, 2, MX51_UART_PAD_CTRL)

Definition at line 449 of file iomux-mx51.h.

#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD   IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 445 of file iomux-mx51.h.

#define MX51_PAD_AUD3_BB_TXD__GPIO4_18   IOMUX_PAD(0x5f0, 0x200, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 446 of file iomux-mx51.h.

#define MX51_PAD_CSI1_D10__CSI1_D10   IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 407 of file iomux-mx51.h.

#define MX51_PAD_CSI1_D11__CSI1_D11   IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 408 of file iomux-mx51.h.

#define MX51_PAD_CSI1_D12__CSI1_D12   IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 409 of file iomux-mx51.h.

#define MX51_PAD_CSI1_D13__CSI1_D13   IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 410 of file iomux-mx51.h.

#define MX51_PAD_CSI1_D14__CSI1_D14   IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 411 of file iomux-mx51.h.

#define MX51_PAD_CSI1_D15__CSI1_D15   IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 412 of file iomux-mx51.h.

#define MX51_PAD_CSI1_D16__CSI1_D16   IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 413 of file iomux-mx51.h.

#define MX51_PAD_CSI1_D17__CSI1_D17   IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 414 of file iomux-mx51.h.

#define MX51_PAD_CSI1_D18__CSI1_D18   IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 415 of file iomux-mx51.h.

#define MX51_PAD_CSI1_D19__CSI1_D19   IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 416 of file iomux-mx51.h.

#define MX51_PAD_CSI1_D8__CSI1_D8   IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 403 of file iomux-mx51.h.

#define MX51_PAD_CSI1_D8__GPIO3_12   IOMUX_PAD(0x57c, 0x194, 3, 0x998, 1, MX51_GPIO_PAD_CTRL)

Definition at line 404 of file iomux-mx51.h.

#define MX51_PAD_CSI1_D9__CSI1_D9   IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 405 of file iomux-mx51.h.

#define MX51_PAD_CSI1_D9__GPIO3_13   IOMUX_PAD(0x580, 0x198, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 406 of file iomux-mx51.h.

#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC   IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 419 of file iomux-mx51.h.

#define MX51_PAD_CSI1_HSYNC__GPIO3_15   IOMUX_PAD(0x5b0, 0x1c8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 420 of file iomux-mx51.h.

#define MX51_PAD_CSI1_MCLK__CSI1_MCLK   IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL)

Definition at line 422 of file iomux-mx51.h.

#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK   IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL)

Definition at line 421 of file iomux-mx51.h.

#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC   IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 417 of file iomux-mx51.h.

#define MX51_PAD_CSI1_VSYNC__GPIO3_14   IOMUX_PAD(0x5ac, 0x1c4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 418 of file iomux-mx51.h.

#define MX51_PAD_CSI2_D12__CSI2_D12   IOMUX_PAD(0x5bc, 0x1cc, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 423 of file iomux-mx51.h.

#define MX51_PAD_CSI2_D12__GPIO4_9   IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 424 of file iomux-mx51.h.

#define MX51_PAD_CSI2_D13__CSI2_D13   IOMUX_PAD(0x5c0, 0x1d0, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 425 of file iomux-mx51.h.

#define MX51_PAD_CSI2_D13__GPIO4_10   IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 426 of file iomux-mx51.h.

#define MX51_PAD_CSI2_D14__CSI2_D14   IOMUX_PAD(0x5c4, 0x1d4, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 427 of file iomux-mx51.h.

#define MX51_PAD_CSI2_D15__CSI2_D15   IOMUX_PAD(0x5c8, 0x1d8, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 428 of file iomux-mx51.h.

#define MX51_PAD_CSI2_D16__CSI2_D16   IOMUX_PAD(0x5cc, 0x1dc, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 429 of file iomux-mx51.h.

#define MX51_PAD_CSI2_D17__CSI2_D17   IOMUX_PAD(0x5d0, 0x1e0, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 430 of file iomux-mx51.h.

#define MX51_PAD_CSI2_D18__CSI2_D18   IOMUX_PAD(0x5d4, 0x1e4, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 431 of file iomux-mx51.h.

#define MX51_PAD_CSI2_D18__GPIO4_11   IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 432 of file iomux-mx51.h.

#define MX51_PAD_CSI2_D19__CSI2_D19   IOMUX_PAD(0x5d8, 0x1e8, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 433 of file iomux-mx51.h.

#define MX51_PAD_CSI2_D19__GPIO4_12   IOMUX_PAD(0x5d8, 0x1e8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 434 of file iomux-mx51.h.

#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC   IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 437 of file iomux-mx51.h.

#define MX51_PAD_CSI2_HSYNC__GPIO4_14   IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 438 of file iomux-mx51.h.

#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK   IOMUX_PAD(0x5e4, 0x1f4, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 439 of file iomux-mx51.h.

#define MX51_PAD_CSI2_PIXCLK__GPIO4_15   IOMUX_PAD(0x5e4, 0x1f4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 440 of file iomux-mx51.h.

#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC   IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 435 of file iomux-mx51.h.

#define MX51_PAD_CSI2_VSYNC__GPIO4_13   IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 436 of file iomux-mx51.h.

#define MX51_PAD_CSPI1_MISO__AUD4_RXD   IOMUX_PAD(0x604, 0x214, 1, 0x8c4, 1, NO_PAD_CTRL)

Definition at line 458 of file iomux-mx51.h.

#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO   IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 459 of file iomux-mx51.h.

#define MX51_PAD_CSPI1_MISO__GPIO4_23   IOMUX_PAD(0x604, 0x214, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 460 of file iomux-mx51.h.

#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI   IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 455 of file iomux-mx51.h.

#define MX51_PAD_CSPI1_MOSI__GPIO4_22   IOMUX_PAD(0x600, 0x210, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 456 of file iomux-mx51.h.

#define MX51_PAD_CSPI1_MOSI__I2C1_SDA   IOMUX_PAD(0x600, 0x210, 0x11, 0x9b4, 1, MX51_I2C_PAD_CTRL)

Definition at line 457 of file iomux-mx51.h.

#define MX51_PAD_CSPI1_RDY__AUD4_TXFS   IOMUX_PAD(0x610, 0x220, 1, 0x8d0, 1, NO_PAD_CTRL)

Definition at line 467 of file iomux-mx51.h.

#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY   IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 468 of file iomux-mx51.h.

#define MX51_PAD_CSPI1_RDY__GPIO4_26   IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 469 of file iomux-mx51.h.

#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK   IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 470 of file iomux-mx51.h.

#define MX51_PAD_CSPI1_SCLK__GPIO4_27   IOMUX_PAD(0x614, 0x224, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 471 of file iomux-mx51.h.

#define MX51_PAD_CSPI1_SCLK__I2C1_SCL   IOMUX_PAD(0x614, 0x224, 0x11, 0x9b0, 1, MX51_I2C_PAD_CTRL)

Definition at line 472 of file iomux-mx51.h.

#define MX51_PAD_CSPI1_SS0__AUD4_TXC   IOMUX_PAD(0x608, 0x218, 1, 0x8cc, 1, NO_PAD_CTRL)

Definition at line 461 of file iomux-mx51.h.

#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0   IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 462 of file iomux-mx51.h.

#define MX51_PAD_CSPI1_SS0__GPIO4_24   IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 463 of file iomux-mx51.h.

#define MX51_PAD_CSPI1_SS1__AUD4_TXD   IOMUX_PAD(0x60c, 0x21c, 1, 0x8c8, 1, NO_PAD_CTRL)

Definition at line 464 of file iomux-mx51.h.

#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1   IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 465 of file iomux-mx51.h.

#define MX51_PAD_CSPI1_SS1__GPIO4_25   IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 466 of file iomux-mx51.h.

#define MX51_PAD_CTRL_2   (PAD_CTL_PKE | PAD_CTL_HYS)

Definition at line 39 of file iomux-mx51.h.

#define MX51_PAD_CTRL_3   (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)

Definition at line 40 of file iomux-mx51.h.

#define MX51_PAD_CTRL_4   (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)

Definition at line 41 of file iomux-mx51.h.

#define MX51_PAD_CTRL_5   (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)

Definition at line 42 of file iomux-mx51.h.

#define MX51_PAD_DI1_D0_CS__DI1_D0_CS   IOMUX_PAD(0x6b4, 0x2b4, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 567 of file iomux-mx51.h.

#define MX51_PAD_DI1_D0_CS__GPIO3_3   IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL)

Definition at line 568 of file iomux-mx51.h.

#define MX51_PAD_DI1_D1_CS__DI1_D1_CS   IOMUX_PAD(0x6b8, 0x2b8, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 569 of file iomux-mx51.h.

#define MX51_PAD_DI1_D1_CS__DISP1_PIN14   IOMUX_PAD(0x6b8, 0x2b8, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 570 of file iomux-mx51.h.

#define MX51_PAD_DI1_D1_CS__DISP1_PIN5   IOMUX_PAD(0x6b8, 0x2b8, 3, __NA_, 0, NO_PAD_CTRL)

Definition at line 571 of file iomux-mx51.h.

#define MX51_PAD_DI1_D1_CS__GPIO3_4   IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL)

Definition at line 572 of file iomux-mx51.h.

#define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK   IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 645 of file iomux-mx51.h.

#define MX51_PAD_DI1_PIN11__DI1_PIN11   IOMUX_PAD(0x6a8, 0x2a8, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 560 of file iomux-mx51.h.

#define MX51_PAD_DI1_PIN11__ECSPI1_SS2   IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 561 of file iomux-mx51.h.

#define MX51_PAD_DI1_PIN11__GPIO3_0   IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 562 of file iomux-mx51.h.

#define MX51_PAD_DI1_PIN12__DI1_PIN12   IOMUX_PAD(0x6ac, 0x2ac, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 563 of file iomux-mx51.h.

#define MX51_PAD_DI1_PIN12__GPIO3_1   IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL)

Definition at line 564 of file iomux-mx51.h.

#define MX51_PAD_DI1_PIN13__DI1_PIN13   IOMUX_PAD(0x6b0, 0x2b0, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 565 of file iomux-mx51.h.

#define MX51_PAD_DI1_PIN13__GPIO3_2   IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL)

Definition at line 566 of file iomux-mx51.h.

#define MX51_PAD_DI1_PIN15__DI1_PIN15   IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 647 of file iomux-mx51.h.

#define MX51_PAD_DI1_PIN2__DI1_PIN2   IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 646 of file iomux-mx51.h.

#define MX51_PAD_DI1_PIN3__DI1_PIN3   IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 644 of file iomux-mx51.h.

#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK   IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 660 of file iomux-mx51.h.

#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1   IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL)

Definition at line 661 of file iomux-mx51.h.

#define MX51_PAD_DI2_PIN2__DI2_PIN2   IOMUX_PAD(0x74c, 0x344, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 656 of file iomux-mx51.h.

#define MX51_PAD_DI2_PIN2__FEC_MDC   IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5)

Definition at line 657 of file iomux-mx51.h.

#define MX51_PAD_DI2_PIN3__DI2_PIN3   IOMUX_PAD(0x750, 0x348, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 658 of file iomux-mx51.h.

#define MX51_PAD_DI2_PIN3__FEC_MDIO   IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL)

Definition at line 659 of file iomux-mx51.h.

#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN   IOMUX_PAD(0x748, 0x340, 3, 0x99c, 1, NO_PAD_CTRL)

Definition at line 653 of file iomux-mx51.h.

#define MX51_PAD_DI2_PIN4__DI2_PIN4   IOMUX_PAD(0x748, 0x340, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 654 of file iomux-mx51.h.

#define MX51_PAD_DI2_PIN4__FEC_CRS   IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL)

Definition at line 655 of file iomux-mx51.h.

#define MX51_PAD_DI_GP2__DISP1_SER_CLK   IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 648 of file iomux-mx51.h.

#define MX51_PAD_DI_GP2__DISP2_WAIT   IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL)

Definition at line 649 of file iomux-mx51.h.

#define MX51_PAD_DI_GP3__CSI1_DATA_EN   IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL)

Definition at line 650 of file iomux-mx51.h.

#define MX51_PAD_DI_GP3__DISP1_SER_DIO   IOMUX_PAD(0x744, 0x33c, 0, 0x9c0, 0, NO_PAD_CTRL)

Definition at line 651 of file iomux-mx51.h.

#define MX51_PAD_DI_GP3__FEC_TX_ER   IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5)

Definition at line 652 of file iomux-mx51.h.

#define MX51_PAD_DI_GP4__DI2_PIN15   IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL)

Definition at line 662 of file iomux-mx51.h.

#define MX51_PAD_DI_GP4__DISP1_SER_DIN   IOMUX_PAD(0x758, 0x350, 0, 0x9c0, 1, NO_PAD_CTRL)

Definition at line 663 of file iomux-mx51.h.

#define MX51_PAD_DI_GP4__DISP2_PIN1   IOMUX_PAD(0x758, 0x350, 3, __NA_, 0, NO_PAD_CTRL)

Definition at line 664 of file iomux-mx51.h.

#define MX51_PAD_DI_GP4__FEC_RDATA2   IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL)

Definition at line 665 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT0__DISP1_DAT0   IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 589 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE   IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 603 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT10__DISP1_DAT10   IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 604 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2   IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 605 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT11__DISP1_DAT11   IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 606 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL   IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 607 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT12__DISP1_DAT12   IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 608 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0   IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 609 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT13__DISP1_DAT13   IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 610 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1   IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 611 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT14__DISP1_DAT14   IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 612 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH   IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 613 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT15__DISP1_DAT15   IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 614 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0   IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 615 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT16__DISP1_DAT16   IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 616 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1   IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 617 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT17__DISP1_DAT17   IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 618 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0   IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 619 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT18__DISP1_DAT18   IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 620 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT18__DISP2_PIN11   IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 621 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT18__DISP2_PIN5   IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL)

Definition at line 622 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1   IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 623 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT19__DISP1_DAT19   IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 624 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT19__DISP2_PIN12   IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 625 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT19__DISP2_PIN6   IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL)

Definition at line 626 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT1__DISP1_DAT1   IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 590 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0   IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 627 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT20__DISP1_DAT20   IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 628 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT20__DISP2_PIN13   IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 629 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT20__DISP2_PIN7   IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL)

Definition at line 630 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1   IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 631 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT21__DISP1_DAT21   IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 632 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT21__DISP2_PIN14   IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 633 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT21__DISP2_PIN8   IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL)

Definition at line 634 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0   IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 635 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT22__DISP1_DAT22   IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 636 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS   IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL)

Definition at line 637 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT22__DISP2_DAT16   IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 638 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1   IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 639 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT23__DISP1_DAT23   IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 640 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS   IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL)

Definition at line 641 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT23__DISP2_DAT17   IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 642 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS   IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL)

Definition at line 643 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT2__DISP1_DAT2   IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 591 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT3__DISP1_DAT3   IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 592 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT4__DISP1_DAT4   IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 593 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT5__DISP1_DAT5   IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 594 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC   IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 595 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT6__DISP1_DAT6   IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 596 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG   IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 597 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT7__DISP1_DAT7   IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 598 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT8__BOOT_SRC0   IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 599 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT8__DISP1_DAT8   IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 600 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT9__BOOT_SRC1   IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 601 of file iomux-mx51.h.

#define MX51_PAD_DISP1_DAT9__DISP1_DAT9   IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 602 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT0__DISP2_DAT0   IOMUX_PAD(0x75c, 0x354, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 666 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT0__FEC_RDATA3   IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL)

Definition at line 667 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT0__KEY_COL6   IOMUX_PAD(0x75c, 0x354, 4, 0x9c8, 1, NO_PAD_CTRL)

Definition at line 668 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT0__UART3_RXD   IOMUX_PAD(0x75c, 0x354, 5, 0x9f4, 8, MX51_UART_PAD_CTRL)

Definition at line 669 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT0__USBH3_CLK   IOMUX_PAD(0x75c, 0x354, 3, 0x9f8, 1, MX51_UART_PAD_CTRL)

Definition at line 670 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT10__DISP2_DAT10   IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 700 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS   IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 701 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT10__FEC_COL   IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL)

Definition at line 702 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT10__KEY_ROW7   IOMUX_PAD(0x784, 0x37c, 4, 0x9dc, 1, NO_PAD_CTRL)

Definition at line 703 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT10__USBH3_DATA2   IOMUX_PAD(0x784, 0x37c, 3, 0xa04, 1, NO_PAD_CTRL)

Definition at line 704 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT11__AUD6_TXD   IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL)

Definition at line 705 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT11__DISP2_DAT11   IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 706 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK   IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL)

Definition at line 707 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT11__GPIO1_10   IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 708 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT11__USBH3_DATA3   IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL)

Definition at line 709 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT12__AUD6_RXD   IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL)

Definition at line 710 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT12__DISP2_DAT12   IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 711 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT12__FEC_RX_DV   IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL)

Definition at line 712 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT12__USBH3_DATA4   IOMUX_PAD(0x78c, 0x384, 3, 0xa0c, 1, NO_PAD_CTRL)

Definition at line 713 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT13__AUD6_TXC   IOMUX_PAD(0x790, 0x388, 4, 0x8fc, 1, NO_PAD_CTRL)

Definition at line 714 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT13__DISP2_DAT13   IOMUX_PAD(0x790, 0x388, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 715 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK   IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4)

Definition at line 716 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT13__USBH3_DATA5   IOMUX_PAD(0x790, 0x388, 3, 0xa10, 1, NO_PAD_CTRL)

Definition at line 717 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT14__AUD6_TXFS   IOMUX_PAD(0x794, 0x38c, 4, 0x900, 1, NO_PAD_CTRL)

Definition at line 718 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT14__DISP2_DAT14   IOMUX_PAD(0x794, 0x38c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 719 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT14__FEC_RDATA0   IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4)

Definition at line 720 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT14__USBH3_DATA6   IOMUX_PAD(0x794, 0x38c, 3, 0xa14, 1, NO_PAD_CTRL)

Definition at line 721 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT15__AUD6_RXFS   IOMUX_PAD(0x798, 0x390, 4, 0x8f8, 1, NO_PAD_CTRL)

Definition at line 722 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS   IOMUX_PAD(0x798, 0x390, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 723 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT15__DISP2_DAT15   IOMUX_PAD(0x798, 0x390, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 724 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT15__FEC_TDATA0   IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5)

Definition at line 725 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT15__USBH3_DATA7   IOMUX_PAD(0x798, 0x390, 3, 0xa18, 1, NO_PAD_CTRL)

Definition at line 726 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT1__DISP2_DAT1   IOMUX_PAD(0x760, 0x358, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 671 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT1__FEC_RX_ER   IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL)

Definition at line 672 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT1__KEY_COL7   IOMUX_PAD(0x760, 0x358, 4, 0x9cc, 1, NO_PAD_CTRL)

Definition at line 673 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT1__UART3_TXD   IOMUX_PAD(0x760, 0x358, 5, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 674 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT1__USBH3_DIR   IOMUX_PAD(0x760, 0x358, 3, 0xa1c, 1, NO_PAD_CTRL)

Definition at line 675 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT2__DISP2_DAT2   IOMUX_PAD(0x764, 0x35c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 676 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT3__DISP2_DAT3   IOMUX_PAD(0x768, 0x360, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 677 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT4__DISP2_DAT4   IOMUX_PAD(0x76c, 0x364, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 678 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT5__DISP2_DAT5   IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 679 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT6__DISP2_DAT6   IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 680 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT6__FEC_TDATA1   IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5)

Definition at line 681 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT6__GPIO1_19   IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 682 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT6__KEY_ROW4   IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL)

Definition at line 683 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT6__USBH3_STP   IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL)

Definition at line 684 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT7__DISP2_DAT7   IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 685 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT7__FEC_TDATA2   IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5)

Definition at line 686 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT7__GPIO1_29   IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 687 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT7__KEY_ROW5   IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL)

Definition at line 688 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT7__USBH3_NXT   IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL)

Definition at line 689 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT8__DISP2_DAT8   IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 690 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT8__FEC_TDATA3   IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5)

Definition at line 691 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT8__GPIO1_30   IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 692 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT8__KEY_ROW6   IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL)

Definition at line 693 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT8__USBH3_DATA0   IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL)

Definition at line 694 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT9__AUD6_RXC   IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL)

Definition at line 695 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT9__DISP2_DAT9   IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 696 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT9__FEC_TX_EN   IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5)

Definition at line 697 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT9__GPIO1_31   IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 698 of file iomux-mx51.h.

#define MX51_PAD_DISP2_DAT9__USBH3_DATA1   IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL)

Definition at line 699 of file iomux-mx51.h.

#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17   IOMUX_PAD(0x6c4, 0x2c4, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 579 of file iomux-mx51.h.

#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7   IOMUX_PAD(0x6c4, 0x2c4, 3, __NA_, 0, NO_PAD_CTRL)

Definition at line 580 of file iomux-mx51.h.

#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK   IOMUX_PAD(0x6c4, 0x2c4, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 581 of file iomux-mx51.h.

#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7   IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL)

Definition at line 582 of file iomux-mx51.h.

#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1   IOMUX_PAD(0x6bc, 0x2bc, 2, 0x9a4, 1, NO_PAD_CTRL)

Definition at line 573 of file iomux-mx51.h.

#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN   IOMUX_PAD(0x6bc, 0x2bc, 0, 0x9c4, 0, NO_PAD_CTRL)

Definition at line 574 of file iomux-mx51.h.

#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5   IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL)

Definition at line 575 of file iomux-mx51.h.

#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6   IOMUX_PAD(0x6c0, 0x2c0, 3, __NA_, 0, NO_PAD_CTRL)

Definition at line 576 of file iomux-mx51.h.

#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO   IOMUX_PAD(0x6c0, 0x2c0, 0, 0x9c4, 1, NO_PAD_CTRL)

Definition at line 577 of file iomux-mx51.h.

#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6   IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL)

Definition at line 578 of file iomux-mx51.h.

#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK   IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 583 of file iomux-mx51.h.

#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16   IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 584 of file iomux-mx51.h.

#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8   IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL)

Definition at line 585 of file iomux-mx51.h.

#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 587 of file iomux-mx51.h.

#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 587 of file iomux-mx51.h.

#define MX51_PAD_DISPB2_SER_RS__GPIO3_8   IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL)

Definition at line 588 of file iomux-mx51.h.

#define MX51_PAD_DRAM_CS1__CCM_CLKO   IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 233 of file iomux-mx51.h.

#define MX51_PAD_DRAM_CS1__DRAM_CS1   IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 232 of file iomux-mx51.h.

#define MX51_PAD_EIM_A16__EIM_A16   IOMUX_PAD(0x430, 0x09c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 139 of file iomux-mx51.h.

#define MX51_PAD_EIM_A16__GPIO2_10   IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 140 of file iomux-mx51.h.

#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0   IOMUX_PAD(0x430, 0x09c, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 141 of file iomux-mx51.h.

#define MX51_PAD_EIM_A17__EIM_A17   IOMUX_PAD(0x434, 0x0a0, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 142 of file iomux-mx51.h.

#define MX51_PAD_EIM_A17__GPIO2_11   IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 143 of file iomux-mx51.h.

#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1   IOMUX_PAD(0x434, 0x0a0, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 144 of file iomux-mx51.h.

#define MX51_PAD_EIM_A18__BOOT_LPB0   IOMUX_PAD(0x438, 0x0a4, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 145 of file iomux-mx51.h.

#define MX51_PAD_EIM_A18__EIM_A18   IOMUX_PAD(0x438, 0x0a4, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 146 of file iomux-mx51.h.

#define MX51_PAD_EIM_A18__GPIO2_12   IOMUX_PAD(0x438, 0x0a4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 147 of file iomux-mx51.h.

#define MX51_PAD_EIM_A19__BOOT_LPB1   IOMUX_PAD(0x43c, 0x0a8, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 148 of file iomux-mx51.h.

#define MX51_PAD_EIM_A19__EIM_A19   IOMUX_PAD(0x43c, 0x0a8, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 149 of file iomux-mx51.h.

#define MX51_PAD_EIM_A19__GPIO2_13   IOMUX_PAD(0x43c, 0x0a8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 150 of file iomux-mx51.h.

#define MX51_PAD_EIM_A20__BOOT_UART_SRC0   IOMUX_PAD(0x440, 0x0ac, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 151 of file iomux-mx51.h.

#define MX51_PAD_EIM_A20__EIM_A20   IOMUX_PAD(0x440, 0x0ac, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 152 of file iomux-mx51.h.

#define MX51_PAD_EIM_A20__GPIO2_14   IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 153 of file iomux-mx51.h.

#define MX51_PAD_EIM_A21__BOOT_UART_SRC1   IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 154 of file iomux-mx51.h.

#define MX51_PAD_EIM_A21__EIM_A21   IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 155 of file iomux-mx51.h.

#define MX51_PAD_EIM_A21__GPIO2_15   IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 156 of file iomux-mx51.h.

#define MX51_PAD_EIM_A22__EIM_A22   IOMUX_PAD(0x448, 0x0b4, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 157 of file iomux-mx51.h.

#define MX51_PAD_EIM_A22__GPIO2_16   IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 158 of file iomux-mx51.h.

#define MX51_PAD_EIM_A23__BOOT_HPN_EN   IOMUX_PAD(0x44c, 0x0b8, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 159 of file iomux-mx51.h.

#define MX51_PAD_EIM_A23__EIM_A23   IOMUX_PAD(0x44c, 0x0b8, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 160 of file iomux-mx51.h.

#define MX51_PAD_EIM_A23__GPIO2_17   IOMUX_PAD(0x44c, 0x0b8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 161 of file iomux-mx51.h.

#define MX51_PAD_EIM_A24__EIM_A24   IOMUX_PAD(0x450, 0x0bc, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 162 of file iomux-mx51.h.

#define MX51_PAD_EIM_A24__GPIO2_18   IOMUX_PAD(0x450, 0x0bc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 163 of file iomux-mx51.h.

#define MX51_PAD_EIM_A24__USBH2_CLK   IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 164 of file iomux-mx51.h.

#define MX51_PAD_EIM_A25__DISP1_PIN4   IOMUX_PAD(0x454, 0x0c0, 6, __NA_, 0, NO_PAD_CTRL)

Definition at line 165 of file iomux-mx51.h.

#define MX51_PAD_EIM_A25__EIM_A25   IOMUX_PAD(0x454, 0x0c0, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 166 of file iomux-mx51.h.

#define MX51_PAD_EIM_A25__GPIO2_19   IOMUX_PAD(0x454, 0x0c0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 167 of file iomux-mx51.h.

#define MX51_PAD_EIM_A25__USBH2_DIR   IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 168 of file iomux-mx51.h.

#define MX51_PAD_EIM_A26__CSI1_DATA_EN   IOMUX_PAD(0x458, 0x0c4, 5, 0x9a0, 0, NO_PAD_CTRL)

Definition at line 169 of file iomux-mx51.h.

#define MX51_PAD_EIM_A26__DISP2_EXT_CLK   IOMUX_PAD(0x458, 0x0c4, 6, 0x908, 0, NO_PAD_CTRL)

Definition at line 170 of file iomux-mx51.h.

#define MX51_PAD_EIM_A26__EIM_A26   IOMUX_PAD(0x458, 0x0c4, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 171 of file iomux-mx51.h.

#define MX51_PAD_EIM_A26__GPIO2_20   IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 172 of file iomux-mx51.h.

#define MX51_PAD_EIM_A26__USBH2_STP   IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 173 of file iomux-mx51.h.

#define MX51_PAD_EIM_A27__CSI2_DATA_EN   IOMUX_PAD(0x45c, 0x0c8, 5, 0x99c, 0, NO_PAD_CTRL)

Definition at line 174 of file iomux-mx51.h.

#define MX51_PAD_EIM_A27__DISP1_PIN1   IOMUX_PAD(0x45c, 0x0c8, 6, 0x9a4, 0, NO_PAD_CTRL)

Definition at line 175 of file iomux-mx51.h.

#define MX51_PAD_EIM_A27__EIM_A27   IOMUX_PAD(0x45c, 0x0c8, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 176 of file iomux-mx51.h.

#define MX51_PAD_EIM_A27__GPIO2_21   IOMUX_PAD(0x45c, 0x0c8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 177 of file iomux-mx51.h.

#define MX51_PAD_EIM_A27__USBH2_NXT   IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 178 of file iomux-mx51.h.

#define MX51_PAD_EIM_CRE__EIM_CRE   IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 230 of file iomux-mx51.h.

#define MX51_PAD_EIM_CRE__GPIO3_2   IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL)

Definition at line 231 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS0__EIM_CS0   IOMUX_PAD(0x474, 0x0e0, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 197 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS0__GPIO2_25   IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 198 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS1__EIM_CS1   IOMUX_PAD(0x478, 0x0e4, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 199 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS1__GPIO2_26   IOMUX_PAD(0x478, 0x0e4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 200 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS2__AUD5_TXD   IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL)

Definition at line 201 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS2__CSI1_D4   IOMUX_PAD(0x47c, 0x0e8, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 202 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS2__EIM_CS2   IOMUX_PAD(0x47c, 0x0e8, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 203 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS2__FEC_RDATA2   IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL)

Definition at line 204 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS2__GPIO2_27   IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 205 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS2__USBOTG_STP   IOMUX_PAD(0x47c, 0x0e8, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 206 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS3__AUD5_RXD   IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL)

Definition at line 207 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS3__CSI1_D5   IOMUX_PAD(0x480, 0x0ec, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 208 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS3__EIM_CS3   IOMUX_PAD(0x480, 0x0ec, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 209 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS3__FEC_RDATA3   IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL)

Definition at line 210 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS3__GPIO2_28   IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 211 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS3__USBOTG_NXT   IOMUX_PAD(0x480, 0x0ec, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 212 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS4__AUD5_TXC   IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL)

Definition at line 213 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS4__CSI1_D6   IOMUX_PAD(0x484, 0x0f0, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 214 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS4__EIM_CS4   IOMUX_PAD(0x484, 0x0f0, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 215 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS4__FEC_RX_ER   IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2)

Definition at line 216 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS4__GPIO2_29   IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 217 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS4__USBOTG_CLK   IOMUX_PAD(0x484, 0x0f0, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 218 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS5__AUD5_TXFS   IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL)

Definition at line 219 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS5__CSI1_D7   IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 220 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK   IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL)

Definition at line 221 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS5__EIM_CS5   IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 222 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS5__FEC_CRS   IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2)

Definition at line 223 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS5__GPIO2_30   IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 224 of file iomux-mx51.h.

#define MX51_PAD_EIM_CS5__USBOTG_DIR   IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 225 of file iomux-mx51.h.

#define MX51_PAD_EIM_D16__AUD4_RXFS   IOMUX_PAD(0x3f0, 0x05c, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 54 of file iomux-mx51.h.

#define MX51_PAD_EIM_D16__AUD5_TXD   IOMUX_PAD(0x3f0, 0x05c, 7, 0x8d8, 0, NO_PAD_CTRL)

Definition at line 55 of file iomux-mx51.h.

#define MX51_PAD_EIM_D16__EIM_D16   IOMUX_PAD(0x3f0, 0x05c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 56 of file iomux-mx51.h.

#define MX51_PAD_EIM_D16__GPIO2_0   IOMUX_PAD(0x3f0, 0x05c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 57 of file iomux-mx51.h.

#define MX51_PAD_EIM_D16__I2C1_SDA   IOMUX_PAD(0x3f0, 0x05c, 0x14, 0x9b4, 0, MX51_I2C_PAD_CTRL)

Definition at line 58 of file iomux-mx51.h.

#define MX51_PAD_EIM_D16__UART2_CTS   IOMUX_PAD(0x3f0, 0x05c, 3, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 59 of file iomux-mx51.h.

#define MX51_PAD_EIM_D16__USBH2_DATA0   IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 60 of file iomux-mx51.h.

#define MX51_PAD_EIM_D17__AUD5_RXD   IOMUX_PAD(0x3f4, 0x060, 7, 0x8d4, 0, NO_PAD_CTRL)

Definition at line 61 of file iomux-mx51.h.

#define MX51_PAD_EIM_D17__EIM_D17   IOMUX_PAD(0x3f4, 0x060, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 62 of file iomux-mx51.h.

#define MX51_PAD_EIM_D17__GPIO2_1   IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 63 of file iomux-mx51.h.

#define MX51_PAD_EIM_D17__UART2_RXD   IOMUX_PAD(0x3f4, 0x060, 3, 0x9ec, 0, MX51_UART_PAD_CTRL)

Definition at line 64 of file iomux-mx51.h.

#define MX51_PAD_EIM_D17__UART3_CTS   IOMUX_PAD(0x3f4, 0x060, 4, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 65 of file iomux-mx51.h.

#define MX51_PAD_EIM_D17__USBH2_DATA1   IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 66 of file iomux-mx51.h.

#define MX51_PAD_EIM_D18__AUD5_TXC   IOMUX_PAD(0x3f8, 0x064, 7, 0x8e4, 0, NO_PAD_CTRL)

Definition at line 67 of file iomux-mx51.h.

#define MX51_PAD_EIM_D18__EIM_D18   IOMUX_PAD(0x3f8, 0x064, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 68 of file iomux-mx51.h.

#define MX51_PAD_EIM_D18__GPIO2_2   IOMUX_PAD(0x3f8, 0x064, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 69 of file iomux-mx51.h.

#define MX51_PAD_EIM_D18__UART2_TXD   IOMUX_PAD(0x3f8, 0x064, 3, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 70 of file iomux-mx51.h.

#define MX51_PAD_EIM_D18__UART3_RTS   IOMUX_PAD(0x3f8, 0x064, 4, 0x9f0, 1, MX51_UART_PAD_CTRL)

Definition at line 71 of file iomux-mx51.h.

#define MX51_PAD_EIM_D18__USBH2_DATA2   IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 72 of file iomux-mx51.h.

#define MX51_PAD_EIM_D19__AUD4_RXC   IOMUX_PAD(0x3fc, 0x068, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 73 of file iomux-mx51.h.

#define MX51_PAD_EIM_D19__AUD5_TXFS   IOMUX_PAD(0x3fc, 0x068, 7, 0x8e8, 0, NO_PAD_CTRL)

Definition at line 74 of file iomux-mx51.h.

#define MX51_PAD_EIM_D19__EIM_D19   IOMUX_PAD(0x3fc, 0x068, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 75 of file iomux-mx51.h.

#define MX51_PAD_EIM_D19__GPIO2_3   IOMUX_PAD(0x3fc, 0x068, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 76 of file iomux-mx51.h.

#define MX51_PAD_EIM_D19__I2C1_SCL   IOMUX_PAD(0x3fc, 0x068, 0x14, 0x9b0, 0, MX51_I2C_PAD_CTRL)

Definition at line 77 of file iomux-mx51.h.

#define MX51_PAD_EIM_D19__UART2_RTS   IOMUX_PAD(0x3fc, 0x068, 3, 0x9e8, 1, MX51_UART_PAD_CTRL)

Definition at line 78 of file iomux-mx51.h.

#define MX51_PAD_EIM_D19__USBH2_DATA3   IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 79 of file iomux-mx51.h.

#define MX51_PAD_EIM_D20__AUD4_TXD   IOMUX_PAD(0x400, 0x06c, 5, 0x8c8, 0, NO_PAD_CTRL)

Definition at line 80 of file iomux-mx51.h.

#define MX51_PAD_EIM_D20__EIM_D20   IOMUX_PAD(0x400, 0x06c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 81 of file iomux-mx51.h.

#define MX51_PAD_EIM_D20__GPIO2_4   IOMUX_PAD(0x400, 0x06c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 82 of file iomux-mx51.h.

#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB   IOMUX_PAD(0x400, 0x06c, 4, __NA_, 0, NO_PAD_CTRL)

Definition at line 83 of file iomux-mx51.h.

#define MX51_PAD_EIM_D20__USBH2_DATA4   IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 84 of file iomux-mx51.h.

#define MX51_PAD_EIM_D21__AUD4_RXD   IOMUX_PAD(0x404, 0x070, 5, 0x8c4, 0, NO_PAD_CTRL)

Definition at line 85 of file iomux-mx51.h.

#define MX51_PAD_EIM_D21__EIM_D21   IOMUX_PAD(0x404, 0x070, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 86 of file iomux-mx51.h.

#define MX51_PAD_EIM_D21__GPIO2_5   IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 87 of file iomux-mx51.h.

#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB   IOMUX_PAD(0x404, 0x070, 3, __NA_, 0, NO_PAD_CTRL)

Definition at line 88 of file iomux-mx51.h.

#define MX51_PAD_EIM_D21__USBH2_DATA5   IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 89 of file iomux-mx51.h.

#define MX51_PAD_EIM_D22__AUD4_TXC   IOMUX_PAD(0x408, 0x074, 5, 0x8cc, 0, NO_PAD_CTRL)

Definition at line 90 of file iomux-mx51.h.

#define MX51_PAD_EIM_D22__EIM_D22   IOMUX_PAD(0x408, 0x074, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 91 of file iomux-mx51.h.

#define MX51_PAD_EIM_D22__GPIO2_6   IOMUX_PAD(0x408, 0x074, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 92 of file iomux-mx51.h.

#define MX51_PAD_EIM_D22__USBH2_DATA6   IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 93 of file iomux-mx51.h.

#define MX51_PAD_EIM_D23__AUD4_TXFS   IOMUX_PAD(0x40c, 0x078, 5, 0x8d0, 0, NO_PAD_CTRL)

Definition at line 94 of file iomux-mx51.h.

#define MX51_PAD_EIM_D23__EIM_D23   IOMUX_PAD(0x40c, 0x078, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 95 of file iomux-mx51.h.

#define MX51_PAD_EIM_D23__GPIO2_7   IOMUX_PAD(0x40c, 0x078, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 96 of file iomux-mx51.h.

#define MX51_PAD_EIM_D23__SPDIF_OUT1   IOMUX_PAD(0x40c, 0x078, 4, __NA_, 0, NO_PAD_CTRL)

Definition at line 97 of file iomux-mx51.h.

#define MX51_PAD_EIM_D23__USBH2_DATA7   IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 98 of file iomux-mx51.h.

#define MX51_PAD_EIM_D24__AUD6_RXFS   IOMUX_PAD(0x410, 0x07c, 5, 0x8f8, 0, NO_PAD_CTRL)

Definition at line 99 of file iomux-mx51.h.

#define MX51_PAD_EIM_D24__EIM_D24   IOMUX_PAD(0x410, 0x07c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 100 of file iomux-mx51.h.

#define MX51_PAD_EIM_D24__GPIO2_8   IOMUX_PAD(0x410, 0x07c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 101 of file iomux-mx51.h.

#define MX51_PAD_EIM_D24__I2C2_SDA   IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL)

Definition at line 102 of file iomux-mx51.h.

#define MX51_PAD_EIM_D24__UART3_CTS   IOMUX_PAD(0x410, 0x07c, 3, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 103 of file iomux-mx51.h.

#define MX51_PAD_EIM_D24__USBOTG_DATA0   IOMUX_PAD(0x410, 0x07c, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 104 of file iomux-mx51.h.

#define MX51_PAD_EIM_D25__EIM_D25   IOMUX_PAD(0x414, 0x080, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 105 of file iomux-mx51.h.

#define MX51_PAD_EIM_D25__GPT_CMPOUT1   IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 110 of file iomux-mx51.h.

#define MX51_PAD_EIM_D25__KEY_COL6   IOMUX_PAD(0x414, 0x080, 1, 0x9c8, 0, NO_PAD_CTRL)

Definition at line 106 of file iomux-mx51.h.

#define MX51_PAD_EIM_D25__UART2_CTS   IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 107 of file iomux-mx51.h.

#define MX51_PAD_EIM_D25__UART3_RXD   IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL)

Definition at line 108 of file iomux-mx51.h.

#define MX51_PAD_EIM_D25__USBOTG_DATA1   IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 109 of file iomux-mx51.h.

#define MX51_PAD_EIM_D26__EIM_D26   IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 111 of file iomux-mx51.h.

#define MX51_PAD_EIM_D26__GPT_CMPOUT2   IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 116 of file iomux-mx51.h.

#define MX51_PAD_EIM_D26__KEY_COL7   IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL)

Definition at line 112 of file iomux-mx51.h.

#define MX51_PAD_EIM_D26__UART2_RTS   IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL)

Definition at line 113 of file iomux-mx51.h.

#define MX51_PAD_EIM_D26__UART3_TXD   IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 114 of file iomux-mx51.h.

#define MX51_PAD_EIM_D26__USBOTG_DATA2   IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 115 of file iomux-mx51.h.

#define MX51_PAD_EIM_D27__AUD6_RXC   IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL)

Definition at line 117 of file iomux-mx51.h.

#define MX51_PAD_EIM_D27__EIM_D27   IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 118 of file iomux-mx51.h.

#define MX51_PAD_EIM_D27__GPIO2_9   IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 119 of file iomux-mx51.h.

#define MX51_PAD_EIM_D27__I2C2_SCL   IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL)

Definition at line 120 of file iomux-mx51.h.

#define MX51_PAD_EIM_D27__UART3_RTS   IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART_PAD_CTRL)

Definition at line 121 of file iomux-mx51.h.

#define MX51_PAD_EIM_D27__USBOTG_DATA3   IOMUX_PAD(0x41c, 0x088, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 122 of file iomux-mx51.h.

#define MX51_PAD_EIM_D28__AUD6_TXD   IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL)

Definition at line 123 of file iomux-mx51.h.

#define MX51_PAD_EIM_D28__EIM_D28   IOMUX_PAD(0x420, 0x08c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 124 of file iomux-mx51.h.

#define MX51_PAD_EIM_D28__KEY_ROW4   IOMUX_PAD(0x420, 0x08c, 1, 0x9d0, 0, NO_PAD_CTRL)

Definition at line 125 of file iomux-mx51.h.

#define MX51_PAD_EIM_D28__USBOTG_DATA4   IOMUX_PAD(0x420, 0x08c, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 126 of file iomux-mx51.h.

#define MX51_PAD_EIM_D29__AUD6_RXD   IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL)

Definition at line 127 of file iomux-mx51.h.

#define MX51_PAD_EIM_D29__EIM_D29   IOMUX_PAD(0x424, 0x090, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 128 of file iomux-mx51.h.

#define MX51_PAD_EIM_D29__KEY_ROW5   IOMUX_PAD(0x424, 0x090, 1, 0x9d4, 0, NO_PAD_CTRL)

Definition at line 129 of file iomux-mx51.h.

#define MX51_PAD_EIM_D29__USBOTG_DATA5   IOMUX_PAD(0x424, 0x090, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 130 of file iomux-mx51.h.

#define MX51_PAD_EIM_D30__AUD6_TXC   IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL)

Definition at line 131 of file iomux-mx51.h.

#define MX51_PAD_EIM_D30__EIM_D30   IOMUX_PAD(0x428, 0x094, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 132 of file iomux-mx51.h.

#define MX51_PAD_EIM_D30__KEY_ROW6   IOMUX_PAD(0x428, 0x094, 1, 0x9d8, 0, NO_PAD_CTRL)

Definition at line 133 of file iomux-mx51.h.

#define MX51_PAD_EIM_D30__USBOTG_DATA6   IOMUX_PAD(0x428, 0x094, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 134 of file iomux-mx51.h.

#define MX51_PAD_EIM_D31__AUD6_TXFS   IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL)

Definition at line 135 of file iomux-mx51.h.

#define MX51_PAD_EIM_D31__EIM_D31   IOMUX_PAD(0x42c, 0x098, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 136 of file iomux-mx51.h.

#define MX51_PAD_EIM_D31__KEY_ROW7   IOMUX_PAD(0x42c, 0x098, 1, 0x9dc, 0, NO_PAD_CTRL)

Definition at line 137 of file iomux-mx51.h.

#define MX51_PAD_EIM_D31__USBOTG_DATA7   IOMUX_PAD(0x42c, 0x098, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 138 of file iomux-mx51.h.

#define MX51_PAD_EIM_DA0__EIM_DA0   IOMUX_PAD(__NA_, 0x01c, 0, 0x000, 0, NO_PAD_CTRL)

Definition at line 736 of file iomux-mx51.h.

#define MX51_PAD_EIM_DA10__EIM_DA10   IOMUX_PAD(__NA_, 0x044, 0, 0x000, 0, NO_PAD_CTRL)

Definition at line 748 of file iomux-mx51.h.

#define MX51_PAD_EIM_DA11__EIM_DA11   IOMUX_PAD(__NA_, 0x048, 0, 0x000, 0, NO_PAD_CTRL)

Definition at line 749 of file iomux-mx51.h.

#define MX51_PAD_EIM_DA12__EIM_DA12   IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL)

Definition at line 761 of file iomux-mx51.h.

#define MX51_PAD_EIM_DA13__EIM_DA13   IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL)

Definition at line 762 of file iomux-mx51.h.

#define MX51_PAD_EIM_DA14__EIM_DA14   IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL)

Definition at line 763 of file iomux-mx51.h.

#define MX51_PAD_EIM_DA15__EIM_DA15   IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL)

Definition at line 764 of file iomux-mx51.h.

#define MX51_PAD_EIM_DA1__EIM_DA1   IOMUX_PAD(__NA_, 0x020, 0, 0x000, 0, NO_PAD_CTRL)

Definition at line 737 of file iomux-mx51.h.

#define MX51_PAD_EIM_DA2__EIM_DA2   IOMUX_PAD(__NA_, 0x024, 0, 0x000, 0, NO_PAD_CTRL)

Definition at line 738 of file iomux-mx51.h.

#define MX51_PAD_EIM_DA3__EIM_DA3   IOMUX_PAD(__NA_, 0x028, 0, 0x000, 0, NO_PAD_CTRL)

Definition at line 739 of file iomux-mx51.h.

#define MX51_PAD_EIM_DA4__EIM_DA4   IOMUX_PAD(__NA_, 0x02c, 0, 0x000, 0, NO_PAD_CTRL)

Definition at line 742 of file iomux-mx51.h.

#define MX51_PAD_EIM_DA5__EIM_DA5   IOMUX_PAD(__NA_, 0x030, 0, 0x000, 0, NO_PAD_CTRL)

Definition at line 743 of file iomux-mx51.h.

#define MX51_PAD_EIM_DA6__EIM_DA6   IOMUX_PAD(__NA_, 0x034, 0, 0x000, 0, NO_PAD_CTRL)

Definition at line 744 of file iomux-mx51.h.

#define MX51_PAD_EIM_DA7__EIM_DA7   IOMUX_PAD(__NA_, 0x038, 0, 0x000, 0, NO_PAD_CTRL)

Definition at line 745 of file iomux-mx51.h.

#define MX51_PAD_EIM_DA8__EIM_DA8   IOMUX_PAD(__NA_, 0x03c, 0, 0x000, 0, NO_PAD_CTRL)

Definition at line 750 of file iomux-mx51.h.

#define MX51_PAD_EIM_DA9__EIM_DA9   IOMUX_PAD(__NA_, 0x040, 0, 0x000, 0, NO_PAD_CTRL)

Definition at line 751 of file iomux-mx51.h.

#define MX51_PAD_EIM_DTACK__EIM_DTACK   IOMUX_PAD(0x48c, 0x0f8, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 226 of file iomux-mx51.h.

#define MX51_PAD_EIM_DTACK__GPIO2_31   IOMUX_PAD(0x48c, 0x0f8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 227 of file iomux-mx51.h.

#define MX51_PAD_EIM_EB0__EIM_EB0   IOMUX_PAD(0x460, 0x0cc, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 179 of file iomux-mx51.h.

#define MX51_PAD_EIM_EB1__EIM_EB1   IOMUX_PAD(0x464, 0x0d0, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 180 of file iomux-mx51.h.

#define MX51_PAD_EIM_EB2__AUD5_RXFS   IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL)

Definition at line 181 of file iomux-mx51.h.

#define MX51_PAD_EIM_EB2__CSI1_D2   IOMUX_PAD(0x468, 0x0d4, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 182 of file iomux-mx51.h.

#define MX51_PAD_EIM_EB2__EIM_EB2   IOMUX_PAD(0x468, 0x0d4, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 183 of file iomux-mx51.h.

#define MX51_PAD_EIM_EB2__FEC_MDIO
Value:
(IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, 0) | \

Definition at line 184 of file iomux-mx51.h.

#define MX51_PAD_EIM_EB2__GPIO2_22   IOMUX_PAD(0x468, 0x0d4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 187 of file iomux-mx51.h.

#define MX51_PAD_EIM_EB2__GPT_CMPOUT1   IOMUX_PAD(0x468, 0x0d4, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 188 of file iomux-mx51.h.

#define MX51_PAD_EIM_EB3__AUD5_RXC   IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL)

Definition at line 189 of file iomux-mx51.h.

#define MX51_PAD_EIM_EB3__CSI1_D3   IOMUX_PAD(0x46c, 0x0d8, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 190 of file iomux-mx51.h.

#define MX51_PAD_EIM_EB3__EIM_EB3   IOMUX_PAD(0x46c, 0x0d8, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 191 of file iomux-mx51.h.

#define MX51_PAD_EIM_EB3__FEC_RDATA1   IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL)

Definition at line 192 of file iomux-mx51.h.

#define MX51_PAD_EIM_EB3__GPIO2_23   IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 193 of file iomux-mx51.h.

#define MX51_PAD_EIM_EB3__GPT_CMPOUT2   IOMUX_PAD(0x46c, 0x0d8, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 194 of file iomux-mx51.h.

#define MX51_PAD_EIM_LBA__EIM_LBA   IOMUX_PAD(0x494, 0x0fc, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 228 of file iomux-mx51.h.

#define MX51_PAD_EIM_LBA__GPIO3_1   IOMUX_PAD(0x494, 0x0fc, 1, 0x978, 0, MX51_GPIO_PAD_CTRL)

Definition at line 229 of file iomux-mx51.h.

#define MX51_PAD_EIM_OE__EIM_OE   IOMUX_PAD(0x470, 0x0dc, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 195 of file iomux-mx51.h.

#define MX51_PAD_EIM_OE__GPIO2_24   IOMUX_PAD(0x470, 0x0dc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 196 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_0__CSPI_SS2   IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 755 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_0__GPIO1_0   IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 756 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_0__SD1_CD   IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)

Definition at line 757 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_1__CSPI_MISO   IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL)

Definition at line 758 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_1__GPIO1_1   IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 759 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_1__SD1_WP   IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)

Definition at line 760 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_2__CCM_OUT_2   IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 783 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_2__GPIO1_2   IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 784 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_2__I2C2_SCL   IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL)

Definition at line 785 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_2__PLL1_BYP   IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL)

Definition at line 786 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_2__PWM1_PWMO   IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 787 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_3__CCM_CLKO2   IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 790 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_3__GPIO1_3   IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 788 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_3__GPT_CLKIN   IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL)

Definition at line 791 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_3__I2C2_SDA   IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL)

Definition at line 789 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_3__PLL2_BYP   IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL)

Definition at line 792 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_3__PWM2_PWMO   IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 793 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK   IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL)

Definition at line 796 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_4__EIM_RDY   IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL)

Definition at line 797 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_4__GPIO1_4   IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 798 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_4__GPT_CAPIN1   IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL)

Definition at line 800 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B   IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 799 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_5__CCM_CLKO   IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 805 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_5__CSI2_MCLK   IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL)

Definition at line 801 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_5__DISP2_PIN16   IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL)

Definition at line 802 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_5__GPIO1_5   IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 803 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B   IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 804 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_6__DISP2_PIN17   IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL)

Definition at line 806 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_6__GPIO1_6   IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 807 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_6__GPT_CAPIN2   IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL)

Definition at line 809 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_6__REF_EN_B   IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL)

Definition at line 808 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_7__CCM_OUT_0   IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL)

Definition at line 810 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_7__GPIO1_7   IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 811 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_7__SD2_WP   IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)

Definition at line 812 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_7__SPDIF_OUT1   IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 813 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_8__CCM_CLKO2   IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL)

Definition at line 818 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_8__CSI2_DATA_EN   IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL)

Definition at line 814 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_8__GPIO1_8   IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 815 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_8__SD2_CD   IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)

Definition at line 816 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_8__USBH3_PWR   IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 817 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_9__CCM_CLKO   IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL)

Definition at line 825 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_9__CCM_OUT_1   IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL)

Definition at line 819 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_9__DISP2_D1_CS   IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 820 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_9__DISP2_SER_CS   IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 821 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_9__GPIO1_9   IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 822 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_9__SD2_LCTL   IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL)

Definition at line 823 of file iomux-mx51.h.

#define MX51_PAD_GPIO1_9__USBH3_OC   IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 824 of file iomux-mx51.h.

#define MX51_PAD_GPIO_NAND__GPIO_NAND   IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL)

Definition at line 279 of file iomux-mx51.h.

#define MX51_PAD_GPIO_NAND__PATA_INTRQ   IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 280 of file iomux-mx51.h.

#define MX51_PAD_I2C1_CLK__GPIO4_16   IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 441 of file iomux-mx51.h.

#define MX51_PAD_I2C1_CLK__I2C1_CLK   IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)

Definition at line 442 of file iomux-mx51.h.

#define MX51_PAD_I2C1_DAT__GPIO4_17   IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 443 of file iomux-mx51.h.

#define MX51_PAD_I2C1_DAT__I2C1_DAT   IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)

Definition at line 444 of file iomux-mx51.h.

#define MX51_PAD_KEY_COL0__KEY_COL0   IOMUX_PAD(0x64c, 0x25c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 503 of file iomux-mx51.h.

#define MX51_PAD_KEY_COL0__PLL1_BYP   IOMUX_PAD(0x64c, 0x25c, 7, 0x90c, 0, NO_PAD_CTRL)

Definition at line 504 of file iomux-mx51.h.

#define MX51_PAD_KEY_COL1__KEY_COL1   IOMUX_PAD(0x650, 0x260, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 505 of file iomux-mx51.h.

#define MX51_PAD_KEY_COL1__PLL2_BYP   IOMUX_PAD(0x650, 0x260, 7, 0x910, 0, NO_PAD_CTRL)

Definition at line 506 of file iomux-mx51.h.

#define MX51_PAD_KEY_COL2__KEY_COL2   IOMUX_PAD(0x654, 0x264, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 507 of file iomux-mx51.h.

#define MX51_PAD_KEY_COL2__PLL3_BYP   IOMUX_PAD(0x654, 0x264, 7, __NA_, 0, NO_PAD_CTRL)

Definition at line 508 of file iomux-mx51.h.

#define MX51_PAD_KEY_COL3__KEY_COL3   IOMUX_PAD(0x658, 0x268, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 509 of file iomux-mx51.h.

#define MX51_PAD_KEY_COL4__I2C2_SCL   IOMUX_PAD(0x65c, 0x26c, 0x13, 0x9b8, 1, MX51_I2C_PAD_CTRL)

Definition at line 510 of file iomux-mx51.h.

#define MX51_PAD_KEY_COL4__KEY_COL4   IOMUX_PAD(0x65c, 0x26c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 511 of file iomux-mx51.h.

#define MX51_PAD_KEY_COL4__SPDIF_OUT1   IOMUX_PAD(0x65c, 0x26c, 6, __NA_, 0, NO_PAD_CTRL)

Definition at line 512 of file iomux-mx51.h.

#define MX51_PAD_KEY_COL4__UART1_RI   IOMUX_PAD(0x65c, 0x26c, 1, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 513 of file iomux-mx51.h.

#define MX51_PAD_KEY_COL4__UART3_RTS   IOMUX_PAD(0x65c, 0x26c, 2, 0x9f0, 4, MX51_UART_PAD_CTRL)

Definition at line 514 of file iomux-mx51.h.

#define MX51_PAD_KEY_COL5__I2C2_SDA   IOMUX_PAD(0x660, 0x270, 0x13, 0x9bc, 1, MX51_I2C_PAD_CTRL)

Definition at line 515 of file iomux-mx51.h.

#define MX51_PAD_KEY_COL5__KEY_COL5   IOMUX_PAD(0x660, 0x270, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 516 of file iomux-mx51.h.

#define MX51_PAD_KEY_COL5__UART1_DCD   IOMUX_PAD(0x660, 0x270, 1, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 517 of file iomux-mx51.h.

#define MX51_PAD_KEY_COL5__UART3_CTS   IOMUX_PAD(0x660, 0x270, 2, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 518 of file iomux-mx51.h.

#define MX51_PAD_KEY_ROW0__KEY_ROW0   IOMUX_PAD(0x63c, 0x24c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 499 of file iomux-mx51.h.

#define MX51_PAD_KEY_ROW1__KEY_ROW1   IOMUX_PAD(0x640, 0x250, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 500 of file iomux-mx51.h.

#define MX51_PAD_KEY_ROW2__KEY_ROW2   IOMUX_PAD(0x644, 0x254, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 501 of file iomux-mx51.h.

#define MX51_PAD_KEY_ROW3__KEY_ROW3   IOMUX_PAD(0x648, 0x258, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 502 of file iomux-mx51.h.

#define MX51_PAD_NANDF_ALE__GPIO3_5   IOMUX_PAD(0x4ec, 0x110, 3, 0x988, 0, MX51_GPIO_PAD_CTRL)

Definition at line 242 of file iomux-mx51.h.

#define MX51_PAD_NANDF_ALE__NANDF_ALE   IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 243 of file iomux-mx51.h.

#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN   IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 244 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CLE__GPIO3_6   IOMUX_PAD(0x4f0, 0x114, 3, 0x98c, 0, MX51_GPIO_PAD_CTRL)

Definition at line 245 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CLE__NANDF_CLE   IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 246 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CLE__PATA_RESET_B   IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 247 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS0__GPIO3_16   IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 281 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS0__NANDF_CS0   IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 282 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS1__GPIO3_17   IOMUX_PAD(0x51c, 0x134, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 283 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS1__NANDF_CS1   IOMUX_PAD(0x51c, 0x134, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 284 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS2__CSPI_SCLK   IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 285 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS2__FEC_TX_ER   IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5)

Definition at line 286 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS2__GPIO3_18   IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 287 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS2__NANDF_CS2   IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 288 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS2__PATA_CS_0   IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 289 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS2__SD4_CLK   IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)

Definition at line 290 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS2__USBH3_H1_DP   IOMUX_PAD(0x520, 0x138, 0x17, __NA_, 0, NO_PAD_CTRL)

Definition at line 291 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS3__FEC_MDC   IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5)

Definition at line 292 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS3__GPIO3_19   IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 293 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS3__NANDF_CS3   IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 294 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS3__PATA_CS_1   IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 295 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS3__SD4_DAT0   IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 296 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS3__USBH3_H1_DM   IOMUX_PAD(0x524, 0x13c, 0x17, __NA_, 0, NO_PAD_CTRL)

Definition at line 297 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS4__FEC_TDATA1   IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5)

Definition at line 298 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS4__GPIO3_20   IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 299 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS4__NANDF_CS4   IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 300 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS4__PATA_DA_0   IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 301 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS4__SD4_DAT1   IOMUX_PAD(0x528, 0x140, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 302 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS4__USBH3_STP   IOMUX_PAD(0x528, 0x140, 7, 0xa24, 0, NO_PAD_CTRL)

Definition at line 303 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS5__FEC_TDATA2   IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5)

Definition at line 304 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS5__GPIO3_21   IOMUX_PAD(0x52c, 0x144, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 305 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS5__NANDF_CS5   IOMUX_PAD(0x52c, 0x144, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 306 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS5__PATA_DA_1   IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 307 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS5__SD4_DAT2   IOMUX_PAD(0x52c, 0x144, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 308 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS5__USBH3_DIR   IOMUX_PAD(0x52c, 0x144, 7, 0xa1c, 0, NO_PAD_CTRL)

Definition at line 309 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS6__CSPI_SS3   IOMUX_PAD(0x530, 0x148, 7, 0x928, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 310 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS6__FEC_TDATA3   IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5)

Definition at line 311 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS6__GPIO3_22   IOMUX_PAD(0x530, 0x148, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 312 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS6__NANDF_CS6   IOMUX_PAD(0x530, 0x148, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 313 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS6__PATA_DA_2   IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 314 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS6__SD4_DAT3   IOMUX_PAD(0x530, 0x148, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 315 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS7__FEC_TX_EN   IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5)

Definition at line 316 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS7__GPIO3_23   IOMUX_PAD(0x534, 0x14c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 317 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS7__NANDF_CS7   IOMUX_PAD(0x534, 0x14c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 318 of file iomux-mx51.h.

#define MX51_PAD_NANDF_CS7__SD3_CLK   IOMUX_PAD(0x534, 0x14c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)

Definition at line 319 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D0__GPIO4_8   IOMUX_PAD(0x578, 0x190, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 398 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D0__NANDF_D0   IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 399 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D0__PATA_DATA0   IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 400 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D0__SD4_DAT7   IOMUX_PAD(0x578, 0x190, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 401 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D0__USBH3_DATA7   IOMUX_PAD(0x578, 0x190, 5, 0xa18, 0, NO_PAD_CTRL)

Definition at line 402 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D10__GPIO3_30   IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 350 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D10__NANDF_D10   IOMUX_PAD(0x550, 0x168, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 351 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D10__PATA_DATA10   IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 352 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D10__SD3_DATA2   IOMUX_PAD(0x550, 0x168, 5, 0x944, 1, NO_PAD_CTRL)

Definition at line 353 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D11__FEC_RX_DV   IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL)

Definition at line 345 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D11__GPIO3_29   IOMUX_PAD(0x54c, 0x164, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 346 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D11__NANDF_D11   IOMUX_PAD(0x54c, 0x164, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 347 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D11__PATA_DATA11   IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 348 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D11__SD3_DATA3   IOMUX_PAD(0x54c, 0x164, 5, 0x948, 1, NO_PAD_CTRL)

Definition at line 349 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D12__ECSPI2_SS1   IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL)

Definition at line 340 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D12__GPIO3_28   IOMUX_PAD(0x548, 0x160, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 341 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D12__NANDF_D12   IOMUX_PAD(0x548, 0x160, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 342 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D12__PATA_DATA12   IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 343 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D12__SD3_DAT4   IOMUX_PAD(0x548, 0x160, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 344 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D13__ECSPI2_SS2   IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 335 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D13__GPIO3_27   IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 336 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D13__NANDF_D13   IOMUX_PAD(0x544, 0x15c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 337 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D13__PATA_DATA13   IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 338 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D13__SD3_DAT5   IOMUX_PAD(0x544, 0x15c, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 339 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D14__ECSPI2_SS3   IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 330 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D14__GPIO3_26   IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 331 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D14__NANDF_D14   IOMUX_PAD(0x540, 0x158, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 332 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D14__PATA_DATA14   IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 333 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D14__SD3_DAT6   IOMUX_PAD(0x540, 0x158, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 334 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D15__ECSPI2_MOSI   IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 325 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D15__GPIO3_25   IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 326 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D15__NANDF_D15   IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 327 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D15__PATA_DATA15   IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 328 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D15__SD3_DAT7   IOMUX_PAD(0x53c, 0x154, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 329 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D1__GPIO4_7   IOMUX_PAD(0x574, 0x18c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 393 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D1__NANDF_D1   IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 394 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D1__PATA_DATA1   IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 395 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D1__SD4_DAT6   IOMUX_PAD(0x574, 0x18c, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 396 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D1__USBH3_DATA6   IOMUX_PAD(0x574, 0x18c, 5, 0xa14, 0, NO_PAD_CTRL)

Definition at line 397 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D2__GPIO4_6   IOMUX_PAD(0x570, 0x188, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 388 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D2__NANDF_D2   IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 389 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D2__PATA_DATA2   IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 390 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D2__SD4_DAT5   IOMUX_PAD(0x570, 0x188, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 391 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D2__USBH3_DATA5   IOMUX_PAD(0x570, 0x188, 5, 0xa10, 0, NO_PAD_CTRL)

Definition at line 392 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D3__GPIO4_5   IOMUX_PAD(0x56c, 0x184, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 383 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D3__NANDF_D3   IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 384 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D3__PATA_DATA3   IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 385 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D3__SD4_DAT4   IOMUX_PAD(0x56c, 0x184, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 386 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D3__USBH3_DATA4   IOMUX_PAD(0x56c, 0x184, 5, 0xa0c, 0, NO_PAD_CTRL)

Definition at line 387 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D4__GPIO4_4   IOMUX_PAD(0x568, 0x180, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 378 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D4__NANDF_D4   IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 379 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D4__PATA_DATA4   IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 380 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D4__SD4_CD   IOMUX_PAD(0x568, 0x180, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 381 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D4__USBH3_DATA3   IOMUX_PAD(0x568, 0x180, 5, 0xa08, 0, NO_PAD_CTRL)

Definition at line 382 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D5__GPIO4_3   IOMUX_PAD(0x564, 0x17c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 373 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D5__NANDF_D5   IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 374 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D5__PATA_DATA5   IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 375 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D5__SD4_WP   IOMUX_PAD(0x564, 0x17c, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 376 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D5__USBH3_DATA2   IOMUX_PAD(0x564, 0x17c, 5, 0xa04, 0, NO_PAD_CTRL)

Definition at line 377 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D6__GPIO4_2   IOMUX_PAD(0x560, 0x178, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 368 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D6__NANDF_D6   IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 369 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D6__PATA_DATA6   IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 370 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D6__SD4_LCTL   IOMUX_PAD(0x560, 0x178, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 371 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D6__USBH3_DATA1   IOMUX_PAD(0x560, 0x178, 5, 0xa00, 0, NO_PAD_CTRL)

Definition at line 372 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D7__GPIO4_1   IOMUX_PAD(0x55c, 0x174, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 364 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D7__NANDF_D7   IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 365 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D7__PATA_DATA7   IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 366 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D7__USBH3_DATA0   IOMUX_PAD(0x55c, 0x174, 5, 0x9fc, 0, NO_PAD_CTRL)

Definition at line 367 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D8__FEC_TDATA0   IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5)

Definition at line 359 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D8__GPIO4_0   IOMUX_PAD(0x558, 0x170, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 360 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D8__NANDF_D8   IOMUX_PAD(0x558, 0x170, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 361 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D8__PATA_DATA8   IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 362 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D8__SD3_DATA0   IOMUX_PAD(0x558, 0x170, 5, 0x93c, 1, NO_PAD_CTRL)

Definition at line 363 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D9__FEC_RDATA0   IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4)

Definition at line 354 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D9__GPIO3_31   IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 355 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D9__NANDF_D9   IOMUX_PAD(0x554, 0x16c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 356 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D9__PATA_DATA9   IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 357 of file iomux-mx51.h.

#define MX51_PAD_NANDF_D9__SD3_DATA1   IOMUX_PAD(0x554, 0x16c, 5, 0x940, 1, NO_PAD_CTRL)

Definition at line 358 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB0__ECSPI2_SS1   IOMUX_PAD(0x4f8, 0x11c, 5, 0x930, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 252 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB0__GPIO3_8   IOMUX_PAD(0x4f8, 0x11c, 3, 0x994, 0, MX51_GPIO_PAD_CTRL)

Definition at line 253 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB0__NANDF_RB0   IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 254 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB0__PATA_DMARQ   IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 255 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB0__SD3_DATA3   IOMUX_PAD(0x4f8, 0x11c, 2, 0x948, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 256 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB1__CSPI_MOSI   IOMUX_PAD(0x4fc, 0x120, 6, 0x91c, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 257 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB1__ECSPI2_RDY   IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 258 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB1__GPIO3_9   IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 259 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB1__GPT_CMPOUT2   IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL)

Definition at line 262 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB1__NANDF_RB1   IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 260 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB1__PATA_IORDY   IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 261 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB1__SD4_CMD   IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 263 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB2__DISP2_WAIT   IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL)

Definition at line 264 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK   IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 265 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB2__FEC_COL   IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2)

Definition at line 266 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB2__GPIO3_10   IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 267 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB2__GPT_CMPOUT3   IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL)

Definition at line 269 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB2__NANDF_RB2   IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 268 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB2__USBH3_H3_DP   IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL)

Definition at line 270 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB2__USBH3_NXT   IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL)

Definition at line 271 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB3__DISP1_WAIT   IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL)

Definition at line 272 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB3__ECSPI2_MISO   IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 273 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB3__FEC_RX_CLK   IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2)

Definition at line 274 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB3__GPIO3_11   IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 275 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB3__NANDF_RB3   IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 276 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB3__USBH3_CLK   IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL)

Definition at line 277 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RB3__USBH3_H3_DM   IOMUX_PAD(0x504, 0x128, 0x17, __NA_, 0, NO_PAD_CTRL)

Definition at line 278 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0   IOMUX_PAD(0x538, 0x150, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 320 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK   IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4)

Definition at line 321 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RDY_INT__GPIO3_24   IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 322 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT   IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL)

Definition at line 323 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RDY_INT__SD3_CMD   IOMUX_PAD(0x538, 0x150, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 324 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RE_B__GPIO3_4   IOMUX_PAD(0x4e8, 0x10c, 3, 0x984, 0, MX51_GPIO_PAD_CTRL)

Definition at line 238 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RE_B__NANDF_RE_B   IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 239 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RE_B__PATA_DIOR   IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 240 of file iomux-mx51.h.

#define MX51_PAD_NANDF_RE_B__SD3_DATA1   IOMUX_PAD(0x4e8, 0x10c, 2, 0x940, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 241 of file iomux-mx51.h.

#define MX51_PAD_NANDF_WE_B__GPIO3_3   IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL)

Definition at line 234 of file iomux-mx51.h.

#define MX51_PAD_NANDF_WE_B__NANDF_WE_B   IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 235 of file iomux-mx51.h.

#define MX51_PAD_NANDF_WE_B__PATA_DIOW   IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 236 of file iomux-mx51.h.

#define MX51_PAD_NANDF_WE_B__SD3_DATA0   IOMUX_PAD(0x4e4, 0x108, 2, 0x93c, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 237 of file iomux-mx51.h.

#define MX51_PAD_NANDF_WP_B__GPIO3_7   IOMUX_PAD(0x4f4, 0x118, 3, 0x990, 0, MX51_GPIO_PAD_CTRL)

Definition at line 248 of file iomux-mx51.h.

#define MX51_PAD_NANDF_WP_B__NANDF_WP_B   IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 249 of file iomux-mx51.h.

#define MX51_PAD_NANDF_WP_B__PATA_DMACK   IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 250 of file iomux-mx51.h.

#define MX51_PAD_NANDF_WP_B__SD3_DATA2   IOMUX_PAD(0x4f4, 0x118, 2, 0x944, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 251 of file iomux-mx51.h.

#define MX51_PAD_OWIRE_LINE__GPIO1_24   IOMUX_PAD(0x638, 0x248, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 496 of file iomux-mx51.h.

#define MX51_PAD_OWIRE_LINE__OWIRE_LINE   IOMUX_PAD(0x638, 0x248, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 497 of file iomux-mx51.h.

#define MX51_PAD_OWIRE_LINE__SPDIF_OUT   IOMUX_PAD(0x638, 0x248, 6, __NA_, 0, NO_PAD_CTRL)

Definition at line 498 of file iomux-mx51.h.

#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ   IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 794 of file iomux-mx51.h.

#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B   IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 795 of file iomux-mx51.h.

#define MX51_PAD_SD1_CLK__AUD5_RXC   IOMUX_PAD(0x7a0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)

Definition at line 730 of file iomux-mx51.h.

#define MX51_PAD_SD1_CLK__CSPI_SCLK   IOMUX_PAD(0x7a0, 0x398, 2, 0x914, 2, NO_PAD_CTRL)

Definition at line 731 of file iomux-mx51.h.

#define MX51_PAD_SD1_CLK__SD1_CLK   IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)

Definition at line 732 of file iomux-mx51.h.

#define MX51_PAD_SD1_CMD__AUD5_RXFS   IOMUX_PAD(0x79c, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)

Definition at line 727 of file iomux-mx51.h.

#define MX51_PAD_SD1_CMD__CSPI_MOSI   IOMUX_PAD(0x79c, 0x394, 2, 0x91c, 2, NO_PAD_CTRL)

Definition at line 728 of file iomux-mx51.h.

#define MX51_PAD_SD1_CMD__SD1_CMD   IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 729 of file iomux-mx51.h.

#define MX51_PAD_SD1_DATA0__AUD5_TXD   IOMUX_PAD(0x7a4, 0x39c, 1, 0x8d8, 2, NO_PAD_CTRL)

Definition at line 733 of file iomux-mx51.h.

#define MX51_PAD_SD1_DATA0__CSPI_MISO   IOMUX_PAD(0x7a4, 0x39c, 2, 0x918, 1, MX51_ECSPI_PAD_CTRL)

Definition at line 734 of file iomux-mx51.h.

#define MX51_PAD_SD1_DATA0__SD1_DATA0   IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 735 of file iomux-mx51.h.

#define MX51_PAD_SD1_DATA1__AUD5_RXD   IOMUX_PAD(0x7a8, 0x3a0, 1, 0x8d4, 2, NO_PAD_CTRL)

Definition at line 740 of file iomux-mx51.h.

#define MX51_PAD_SD1_DATA1__SD1_DATA1   IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 741 of file iomux-mx51.h.

#define MX51_PAD_SD1_DATA2__AUD5_TXC   IOMUX_PAD(0x7ac, 0x3a4, 1, 0x8e4, 2, NO_PAD_CTRL)

Definition at line 746 of file iomux-mx51.h.

#define MX51_PAD_SD1_DATA2__SD1_DATA2   IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 747 of file iomux-mx51.h.

#define MX51_PAD_SD1_DATA3__AUD5_TXFS   IOMUX_PAD(0x7b0, 0x3a8, 1, 0x8e8, 2, NO_PAD_CTRL)

Definition at line 752 of file iomux-mx51.h.

#define MX51_PAD_SD1_DATA3__CSPI_SS1   IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL)

Definition at line 753 of file iomux-mx51.h.

#define MX51_PAD_SD1_DATA3__SD1_DATA3   IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 754 of file iomux-mx51.h.

#define MX51_PAD_SD2_CLK__CSPI_SCLK   IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL)

Definition at line 768 of file iomux-mx51.h.

#define MX51_PAD_SD2_CLK__I2C1_SDA   IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x9b4, 2, MX51_I2C_PAD_CTRL)

Definition at line 769 of file iomux-mx51.h.

#define MX51_PAD_SD2_CLK__SD2_CLK   IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)

Definition at line 770 of file iomux-mx51.h.

#define MX51_PAD_SD2_CMD__CSPI_MOSI   IOMUX_PAD(0x7bc, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL)

Definition at line 765 of file iomux-mx51.h.

#define MX51_PAD_SD2_CMD__I2C1_SCL   IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL)

Definition at line 766 of file iomux-mx51.h.

#define MX51_PAD_SD2_CMD__SD2_CMD   IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 767 of file iomux-mx51.h.

#define MX51_PAD_SD2_DATA0__CSPI_MISO   IOMUX_PAD(0x7c4, 0x3bc, 2, 0x918, 3, MX51_ECSPI_PAD_CTRL)

Definition at line 771 of file iomux-mx51.h.

#define MX51_PAD_SD2_DATA0__SD1_DAT4   IOMUX_PAD(0x7c4, 0x3bc, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 772 of file iomux-mx51.h.

#define MX51_PAD_SD2_DATA0__SD2_DATA0   IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 773 of file iomux-mx51.h.

#define MX51_PAD_SD2_DATA1__SD1_DAT5   IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 774 of file iomux-mx51.h.

#define MX51_PAD_SD2_DATA1__SD2_DATA1   IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 775 of file iomux-mx51.h.

#define MX51_PAD_SD2_DATA1__USBH3_H2_DP   IOMUX_PAD(0x7c8, 0x3c0, 0x12, __NA_, 0, NO_PAD_CTRL)

Definition at line 776 of file iomux-mx51.h.

#define MX51_PAD_SD2_DATA2__SD1_DAT6   IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 777 of file iomux-mx51.h.

#define MX51_PAD_SD2_DATA2__SD2_DATA2   IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 778 of file iomux-mx51.h.

#define MX51_PAD_SD2_DATA2__USBH3_H2_DM   IOMUX_PAD(0x7cc, 0x3c4, 0x12, __NA_, 0, NO_PAD_CTRL)

Definition at line 779 of file iomux-mx51.h.

#define MX51_PAD_SD2_DATA3__CSPI_SS2   IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL)

Definition at line 780 of file iomux-mx51.h.

#define MX51_PAD_SD2_DATA3__SD1_DAT7   IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 781 of file iomux-mx51.h.

#define MX51_PAD_SD2_DATA3__SD2_DATA3   IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)

Definition at line 782 of file iomux-mx51.h.

#define MX51_PAD_UART1_CTS__GPIO4_31   IOMUX_PAD(0x624, 0x234, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 480 of file iomux-mx51.h.

#define MX51_PAD_UART1_CTS__UART1_CTS   IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 481 of file iomux-mx51.h.

#define MX51_PAD_UART1_RTS__GPIO4_30   IOMUX_PAD(0x620, 0x230, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 478 of file iomux-mx51.h.

#define MX51_PAD_UART1_RTS__UART1_RTS   IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL)

Definition at line 479 of file iomux-mx51.h.

#define MX51_PAD_UART1_RXD__GPIO4_28   IOMUX_PAD(0x618, 0x228, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 473 of file iomux-mx51.h.

#define MX51_PAD_UART1_RXD__UART1_RXD   IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL)

Definition at line 474 of file iomux-mx51.h.

#define MX51_PAD_UART1_TXD__GPIO4_29   IOMUX_PAD(0x61c, 0x22c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 475 of file iomux-mx51.h.

#define MX51_PAD_UART1_TXD__PWM2_PWMO   IOMUX_PAD(0x61c, 0x22c, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 476 of file iomux-mx51.h.

#define MX51_PAD_UART1_TXD__UART1_TXD   IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 477 of file iomux-mx51.h.

#define MX51_PAD_UART2_RXD__FIRI_TXD   IOMUX_PAD(0x628, 0x238, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 482 of file iomux-mx51.h.

#define MX51_PAD_UART2_RXD__GPIO1_20   IOMUX_PAD(0x628, 0x238, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 483 of file iomux-mx51.h.

#define MX51_PAD_UART2_RXD__UART2_RXD   IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL)

Definition at line 484 of file iomux-mx51.h.

#define MX51_PAD_UART2_TXD__FIRI_RXD   IOMUX_PAD(0x62c, 0x23c, 1, __NA_, 0, NO_PAD_CTRL)

Definition at line 485 of file iomux-mx51.h.

#define MX51_PAD_UART2_TXD__GPIO1_21   IOMUX_PAD(0x62c, 0x23c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 486 of file iomux-mx51.h.

#define MX51_PAD_UART2_TXD__UART2_TXD   IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 487 of file iomux-mx51.h.

#define MX51_PAD_UART3_RXD__CSI1_D0   IOMUX_PAD(0x630, 0x240, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 488 of file iomux-mx51.h.

#define MX51_PAD_UART3_RXD__GPIO1_22   IOMUX_PAD(0x630, 0x240, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 489 of file iomux-mx51.h.

#define MX51_PAD_UART3_RXD__UART1_DTR   IOMUX_PAD(0x630, 0x240, 0, __NA_, 0, NO_PAD_CTRL)

Definition at line 490 of file iomux-mx51.h.

#define MX51_PAD_UART3_RXD__UART3_RXD   IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL)

Definition at line 491 of file iomux-mx51.h.

#define MX51_PAD_UART3_TXD__CSI1_D1   IOMUX_PAD(0x634, 0x244, 2, __NA_, 0, NO_PAD_CTRL)

Definition at line 492 of file iomux-mx51.h.

#define MX51_PAD_UART3_TXD__GPIO1_23   IOMUX_PAD(0x634, 0x244, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 493 of file iomux-mx51.h.

#define MX51_PAD_UART3_TXD__UART1_DSR   IOMUX_PAD(0x634, 0x244, 0, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 494 of file iomux-mx51.h.

#define MX51_PAD_UART3_TXD__UART3_TXD   IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 495 of file iomux-mx51.h.

#define MX51_PAD_USBH1_CLK__CSPI_SCLK   IOMUX_PAD(0x678, 0x278, 1, 0x914, 1, MX51_ECSPI_PAD_CTRL)

Definition at line 519 of file iomux-mx51.h.

#define MX51_PAD_USBH1_CLK__GPIO1_25   IOMUX_PAD(0x678, 0x278, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 520 of file iomux-mx51.h.

#define MX51_PAD_USBH1_CLK__I2C2_SCL   IOMUX_PAD(0x678, 0x278, 0x15, 0x9b8, 2, MX51_I2C_PAD_CTRL)

Definition at line 521 of file iomux-mx51.h.

#define MX51_PAD_USBH1_CLK__USBH1_CLK   IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)

Definition at line 522 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA0__GPIO1_11   IOMUX_PAD(0x688, 0x288, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 535 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA0__UART2_CTS   IOMUX_PAD(0x688, 0x288, 1, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 536 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA0__USBH1_DATA0   IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)

Definition at line 537 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA1__GPIO1_12   IOMUX_PAD(0x68c, 0x28c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 538 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA1__UART2_RXD   IOMUX_PAD(0x68c, 0x28c, 1, 0x9ec, 4, MX51_UART_PAD_CTRL)

Definition at line 539 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA1__USBH1_DATA1   IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)

Definition at line 540 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA2__GPIO1_13   IOMUX_PAD(0x690, 0x290, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 541 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA2__UART2_TXD   IOMUX_PAD(0x690, 0x290, 1, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 542 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA2__USBH1_DATA2   IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)

Definition at line 543 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA3__GPIO1_14   IOMUX_PAD(0x694, 0x294, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 544 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA3__UART2_RTS   IOMUX_PAD(0x694, 0x294, 1, 0x9e8, 5, MX51_UART_PAD_CTRL)

Definition at line 545 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA3__USBH1_DATA3   IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)

Definition at line 546 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA4__CSPI_SS0   IOMUX_PAD(0x698, 0x298, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 547 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA4__GPIO1_15   IOMUX_PAD(0x698, 0x298, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 548 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA4__USBH1_DATA4   IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)

Definition at line 549 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA5__CSPI_SS1   IOMUX_PAD(0x69c, 0x29c, 1, 0x920, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 550 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA5__GPIO1_16   IOMUX_PAD(0x69c, 0x29c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 551 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA5__USBH1_DATA5   IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)

Definition at line 552 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA6__CSPI_SS3   IOMUX_PAD(0x6a0, 0x2a0, 1, 0x928, 1, MX51_ECSPI_PAD_CTRL)

Definition at line 553 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA6__GPIO1_17   IOMUX_PAD(0x6a0, 0x2a0, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 554 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA6__USBH1_DATA6   IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)

Definition at line 555 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3   IOMUX_PAD(0x6a4, 0x2a4, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 556 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3   IOMUX_PAD(0x6a4, 0x2a4, 5, 0x934, 1, MX51_ECSPI_PAD_CTRL)

Definition at line 557 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA7__GPIO1_18   IOMUX_PAD(0x6a4, 0x2a4, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 558 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DATA7__USBH1_DATA7   IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)

Definition at line 559 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DIR__CSPI_MOSI   IOMUX_PAD(0x67c, 0x27c, 1, 0x91c, 1, MX51_ECSPI_PAD_CTRL)

Definition at line 523 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DIR__GPIO1_26   IOMUX_PAD(0x67c, 0x27c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 524 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DIR__I2C2_SDA   IOMUX_PAD(0x67c, 0x27c, 0x15, 0x9bc, 2, MX51_I2C_PAD_CTRL)

Definition at line 525 of file iomux-mx51.h.

#define MX51_PAD_USBH1_DIR__USBH1_DIR   IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)

Definition at line 526 of file iomux-mx51.h.

#define MX51_PAD_USBH1_NXT__CSPI_MISO   IOMUX_PAD(0x684, 0x284, 1, 0x918, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 531 of file iomux-mx51.h.

#define MX51_PAD_USBH1_NXT__GPIO1_28   IOMUX_PAD(0x684, 0x284, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 532 of file iomux-mx51.h.

#define MX51_PAD_USBH1_NXT__UART3_TXD   IOMUX_PAD(0x684, 0x284, 5, __NA_, 0, MX51_UART_PAD_CTRL)

Definition at line 533 of file iomux-mx51.h.

#define MX51_PAD_USBH1_NXT__USBH1_NXT   IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)

Definition at line 534 of file iomux-mx51.h.

#define MX51_PAD_USBH1_STP__CSPI_RDY   IOMUX_PAD(0x680, 0x280, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)

Definition at line 527 of file iomux-mx51.h.

#define MX51_PAD_USBH1_STP__GPIO1_27   IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)

Definition at line 528 of file iomux-mx51.h.

#define MX51_PAD_USBH1_STP__UART3_RXD   IOMUX_PAD(0x680, 0x280, 5, 0x9f4, 6, MX51_UART_PAD_CTRL)

Definition at line 529 of file iomux-mx51.h.

#define MX51_PAD_USBH1_STP__USBH1_STP   IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)

Definition at line 530 of file iomux-mx51.h.

#define MX51_SDHCI_PAD_CTRL
Value:
PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
PAD_CTL_SRE_FAST | PAD_CTL_DVS)

Definition at line 34 of file iomux-mx51.h.

#define MX51_UART_PAD_CTRL
Value:

Definition at line 21 of file iomux-mx51.h.

#define MX51_USBH1_PAD_CTRL
Value:
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
PAD_CTL_HYS | PAD_CTL_PUE)

Definition at line 29 of file iomux-mx51.h.