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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Go to the source code of this file.
Functions | |
| void | iop13xx_init_early (void) |
| void | iop13xx_init_irq (void) |
| void | iop13xx_map_io (void) |
| void | iop13xx_platform_init (void) |
| void | iop13xx_add_tpmi_devices (void) |
| void | iop13xx_restart (char, const char *) |
| unsigned long | get_iop_tick_rate (void) |
Variables | |
| u32 | iop13xx_atux_pmmr_offset |
| u32 | iop13xx_atue_pmmr_offset |
| #define IOP13XX_ADMA_PHYS_BASE | ( | chan | ) | IOP13XX_REG_ADDR32_PHYS((chan << 9)) |
| #define IOP13XX_ADMA_UPPER_PA | ( | chan | ) | (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0) |
| #define IOP13XX_ATUE_ATUCMD |
| #define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70) |
| #define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78) |
| #define IOP13XX_ATUE_ATUSR |
| #define IOP13XX_ATUE_DID |
| #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31) |
| #define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10) |
| #define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18) |
| #define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20) |
| #define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40) |
| #define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c) |
| #define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58) |
| #define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44) |
| #define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50) |
| #define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c) |
| #define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14) |
| #define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c) |
| #define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24) |
| #define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48) |
| #define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54) |
| #define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60) |
| #define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c) |
| #define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330) |
| #define IOP13XX_ATUE_OFFSET | ( | ofs | ) |
| #define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300) |
| #define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304) |
| #define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308) |
| #define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310) |
| #define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318) |
| #define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320) |
| #define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c) |
| #define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314) |
| #define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c) |
| #define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324) |
| #define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74) |
| #define IOP13XX_ATUE_PE_LSTS |
| #define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388) |
| #define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384) |
| #define IOP13XX_ATUX_ATUCMD |
| #define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70) |
| #define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78) |
| #define IOP13XX_ATUX_ATUSR |
| #define IOP13XX_ATUX_DID |
| #define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10) |
| #define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18) |
| #define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20) |
| #define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200) |
| #define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40) |
| #define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c) |
| #define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58) |
| #define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208) |
| #define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44) |
| #define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50) |
| #define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c) |
| #define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c) |
| #define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14) |
| #define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c) |
| #define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24) |
| #define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204) |
| #define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48) |
| #define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54) |
| #define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60) |
| #define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210) |
| #define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330) |
| #define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334) |
| #define IOP13XX_ATUX_OFFSET | ( | ofs | ) |
| #define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300) |
| #define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304) |
| #define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328) |
| #define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308) |
| #define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310) |
| #define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318) |
| #define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320) |
| #define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c) |
| #define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c) |
| #define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314) |
| #define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c) |
| #define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324) |
| #define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4) |
| #define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74) |
| #define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188) |
| #define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */ |
| #define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500) |
| #define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500) |
| #define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520) |
| #define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520) |
| #define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540) |
| #define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540) |
| #define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20) |
| #define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28) |
| #define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24) |
| #define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10) |
| #define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14) |
| #define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38) |
| #define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48) |
| #define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48) |
| #define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84) |
| #define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50) |
| #define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C) |
| #define IOP13XX_MU_OFFSET | ( | ofs | ) |
| #define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34) |
| #define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30) |
| #define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18) |
| #define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C) |
| #define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C) |
| #define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54) |
| #define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8) |
| #define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10) |
| #define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0) |
| #define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE |
| #define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc) |
| #define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) |
| #define IOP13XX_PBI_OFFSET | ( | ofs | ) |
| #define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4) |
| #define IOP13XX_PBI_UPPER_MEM_RA |
| #define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE |
| #define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET) |
| #define IOP13XX_PCIE_LOWER_MEM_PA |
| #define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE |
| #define IOP13XX_PCIE_MEM_OFFSET |
| #define IOP13XX_PCIE_UPPER_MEM_BA |
| #define IOP13XX_PCIE_UPPER_MEM_PA |
| #define IOP13XX_PCIE_UPPER_MEM_RA |
| #define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET) |
| #define IOP13XX_PCIX_LOWER_MEM_PA |
| #define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE |
| #define IOP13XX_PCIX_MEM_OFFSET |
| #define IOP13XX_PCIX_UPPER_MEM_BA |
| #define IOP13XX_PCIX_UPPER_MEM_PA |
| #define IOP13XX_PCIX_UPPER_MEM_RA |
| #define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */ |
| #define IOP13XX_PMMR_PHYS_TO_VIRT | ( | addr | ) |
| #define IOP13XX_PMMR_UPPER_MEM_PA |
| #define IOP13XX_PMMR_UPPER_MEM_VA |
| #define IOP13XX_PMMR_VIRT_TO_PHYS | ( | addr | ) |
| #define IOP13XX_PMON_BASE |
| #define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0) |
| #define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30) |
| #define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70) |
| #define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC) |
| #define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C) |
| #define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C) |
| #define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4) |
| #define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34) |
| #define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74) |
| #define IOP13XX_PMON_PHYSBASE |
| #define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8) |
| #define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38) |
| #define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78) |
| #define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040) |
| #define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044) |
| #define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180) |
| #define IOP13XX_REG_ADDR16 | ( | reg | ) | (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) |
| #define IOP13XX_REG_ADDR16_PHYS | ( | reg | ) | (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) |
| #define IOP13XX_REG_ADDR32 | ( | reg | ) | (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) |
| #define IOP13XX_REG_ADDR32_PHYS | ( | reg | ) | (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) |
| #define IOP13XX_REG_ADDR8 | ( | reg | ) | (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) |
| #define IOP13XX_REG_ADDR8_PHYS | ( | reg | ) | (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) |
| #define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300) |
| #define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300) |
| #define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340) |
| #define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340) |
| #define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c) |
| #define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790) |
| #define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794) |
| #define IQ81340_MAX_PLAT_DEVICES |
| #define is_atue_occdr_error | ( | x | ) |
| #define is_atux_occdr_error | ( | x | ) |
1.8.2