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17 static inline int iop13xx_cpu_id(
void)
20 asm volatile(
"mrc p6, 0, %0, c0, c0, 0":
"=r" (
id));
25 static inline u32 read_wdtcr(
void)
28 asm volatile(
"mrc p6, 0, %0, c7, c9, 0":
"=r" (
val));
31 static inline void write_wdtcr(
u32 val)
33 asm volatile(
"mcr p6, 0, %0, c7, c9, 0"::
"r" (
val));
37 static inline u32 read_wdtsr(
void)
40 asm volatile(
"mrc p6, 0, %0, c8, c9, 0":
"=r" (
val));
43 static inline void write_wdtsr(
u32 val)
45 asm volatile(
"mcr p6, 0, %0, c8, c9, 0"::
"r" (
val));
49 static inline u32 read_rcsr(
void)
52 asm volatile(
"mrc p6, 0, %0, c0, c1, 0":
"=r" (
val));
62 #define IOP13XX_MAX_RAM_SIZE 0x80000000UL
63 #define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
75 #define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
76 #define IOP13XX_PCIX_LOWER_IO_BA 0x0UL
78 #define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
79 #define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
80 #define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
81 #define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
82 IOP13XX_PCIX_LOWER_MEM_BA)
83 #define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\
84 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
85 #define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\
86 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
88 #define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL
89 #define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE
90 #define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\
91 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
92 #define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\
93 IOP13XX_PCIX_LOWER_MEM_BA)
96 #define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
97 #define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL
99 #define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
100 #define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
101 #define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
102 #define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
103 IOP13XX_PCIE_LOWER_MEM_BA)
104 #define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\
105 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
106 #define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\
107 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
110 #define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL
111 #define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE
112 #define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\
113 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
114 #define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\
115 IOP13XX_PCIE_LOWER_MEM_BA)
118 #define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL
119 #define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL
120 #define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL
121 #define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE
122 #define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\
123 IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
128 #define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL
129 #define IOP13XX_PMMR_VIRT_MEM_BASE (void __iomem *)(0xfee80000UL)
130 #define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
131 #define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
132 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
133 #define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
134 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
135 #define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\
136 + IOP13XX_PMMR_PHYS_MEM_BASE)
137 #define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\
138 + IOP13XX_PMMR_VIRT_MEM_BASE)
139 #define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
140 #define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
141 #define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
142 #define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
143 #define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
144 #define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
145 #define IOP13XX_PMMR_SIZE 0x00080000
148 #define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300)
149 #define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340)
150 #define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300)
151 #define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340)
153 #define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
154 #define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
155 #define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
156 #define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
157 #define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
158 #define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
162 #define IOP13XX_INIT_ATU_DEFAULT (0)
163 #define IOP13XX_INIT_ATU_ATUX (1 << 0)
164 #define IOP13XX_INIT_ATU_ATUE (1 << 1)
165 #define IOP13XX_INIT_ATU_NONE (1 << 2)
169 #define IOP13XX_INIT_UART_DEFAULT (0)
170 #define IOP13XX_INIT_UART_0 (1 << 0)
171 #define IOP13XX_INIT_UART_1 (1 << 1)
175 #define IOP13XX_INIT_I2C_DEFAULT (0)
176 #define IOP13XX_INIT_I2C_0 (1 << 0)
177 #define IOP13XX_INIT_I2C_1 (1 << 1)
178 #define IOP13XX_INIT_I2C_2 (1 << 2)
182 #define IOP13XX_INIT_ADMA_DEFAULT (0)
183 #define IOP13XX_INIT_ADMA_0 (1 << 0)
184 #define IOP13XX_INIT_ADMA_1 (1 << 1)
185 #define IOP13XX_INIT_ADMA_2 (1 << 2)
188 #define IQ81340_NUM_UART 2
189 #define IQ81340_NUM_I2C 3
190 #define IQ81340_NUM_PHYS_MAP_FLASH 1
191 #define IQ81340_NUM_ADMA 3
192 #define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \
194 IQ81340_NUM_PHYS_MAP_FLASH + \
198 #define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
199 #define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000
200 #define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000
201 #define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000
202 #define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
203 #define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
204 #define IOP13XX_PBI_PMMR_OFFSET 0x00001580
205 #define IOP13XX_MU_PMMR_OFFSET 0x00004000
206 #define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
207 #define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
209 #define IOP13XX_ESSR0_IFACE_MASK 0x00004000
210 #define IOP13XX_CONTROLLER_ONLY (1 << 14)
211 #define IOP13XX_INTERFACE_SEL_PCIX (1 << 15)
213 #define IOP13XX_PMON_PMMR_OFFSET 0x0001A000
214 #define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\
215 IOP13XX_PMON_PMMR_OFFSET)
216 #define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\
217 IOP13XX_PMON_PMMR_OFFSET)
219 #define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0)
220 #define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4)
221 #define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8)
222 #define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC)
224 #define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30)
225 #define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34)
226 #define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38)
227 #define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C)
229 #define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70)
230 #define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74)
231 #define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78)
232 #define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C)
234 #define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
235 #define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
238 #define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\
239 iop13xx_atux_pmmr_offset + (ofs))
241 #define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\
242 iop13xx_atux_pmmr_offset + 0x2)
244 #define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\
245 iop13xx_atux_pmmr_offset + 0x4)
246 #define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\
247 iop13xx_atux_pmmr_offset + 0x6)
249 #define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10)
250 #define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14)
251 #define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18)
252 #define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c)
253 #define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20)
254 #define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24)
255 #define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40)
256 #define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44)
257 #define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48)
258 #define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c)
259 #define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50)
260 #define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54)
261 #define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58)
262 #define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c)
263 #define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60)
264 #define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70)
265 #define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74)
266 #define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78)
267 #define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4)
268 #define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200)
269 #define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204)
270 #define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208)
271 #define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c)
272 #define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210)
274 #define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300)
275 #define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304)
276 #define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308)
277 #define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c)
278 #define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310)
279 #define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314)
280 #define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318)
281 #define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c)
282 #define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320)
283 #define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324)
284 #define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328)
285 #define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c)
286 #define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330)
287 #define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334)
289 #define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1)
290 #define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25)
291 #define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21)
292 #define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15)
293 #define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14)
294 #define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16)
296 #define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
297 #define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17)
298 #define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16)
299 #define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15)
300 #define IOP13XX_ATUX_STAT_ERR_COR (1 << 14)
301 #define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13)
302 #define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12)
303 #define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11)
304 #define IOP13XX_ATUX_STAT_TX_SERR (1 << 10)
305 #define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 )
306 #define IOP13XX_ATUX_STAT_BIST (1 << 8 )
307 #define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 )
308 #define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 )
309 #define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 )
310 #define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 )
311 #define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 )
312 #define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 )
314 #define IOP13XX_ATUX_PCIXSR_BUS_NUM (8)
315 #define IOP13XX_ATUX_PCIXSR_DEV_NUM (3)
316 #define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0)
318 #define IOP13XX_ATUX_IALR_DISABLE 0x00000001
319 #define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000
321 #define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\
322 iop13xx_atue_pmmr_offset + (ofs))
324 #define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\
325 iop13xx_atue_pmmr_offset + 0x2)
326 #define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\
327 iop13xx_atue_pmmr_offset + 0x4)
328 #define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\
329 iop13xx_atue_pmmr_offset + 0x6)
331 #define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10)
332 #define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14)
333 #define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18)
334 #define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c)
335 #define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20)
336 #define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24)
337 #define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40)
338 #define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44)
339 #define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48)
340 #define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c)
341 #define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50)
342 #define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54)
343 #define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58)
344 #define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c)
345 #define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60)
346 #define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\
347 iop13xx_atue_pmmr_offset + 0xe2)
348 #define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304)
349 #define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308)
350 #define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c)
351 #define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310)
352 #define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314)
353 #define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318)
354 #define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c)
355 #define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320)
356 #define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324)
358 #define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70)
359 #define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74)
360 #define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78)
361 #define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300)
362 #define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c)
363 #define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330)
365 #define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384)
366 #define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388)
368 #define IOP13XX_ATUE_ATUCR_IVM (1 << 6)
369 #define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1)
370 #define IOP13XX_ATUE_OCCAR_BUS_NUM (24)
371 #define IOP13XX_ATUE_OCCAR_DEV_NUM (19)
372 #define IOP13XX_ATUE_OCCAR_FUNC_NUM (16)
373 #define IOP13XX_ATUE_OCCAR_EXT_REG (8)
374 #define IOP13XX_ATUE_OCCAR_REG (2)
376 #define IOP13XX_ATUE_PCSR_BUS_NUM (24)
377 #define IOP13XX_ATUE_PCSR_DEV_NUM (19)
378 #define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
379 #define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15)
380 #define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14)
381 #define IOP13XX_ATUE_PCSR_END_POINT (1 << 13)
382 #define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12)
384 #define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff)
385 #define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f)
386 #define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
388 #define IOP13XX_ATUE_PCSR_CORE_RESET (8)
389 #define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
391 #define IOP13XX_ATUE_LSTS_TRAINING (1 << 11)
392 #define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28)
393 #define IOP13XX_ATUE_STAT_PME (1 << 27)
394 #define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26)
395 #define IOP13XX_ATUE_STAT_IVM (1 << 25)
396 #define IOP13XX_ATUE_STAT_BIST (1 << 24)
397 #define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18)
398 #define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17)
399 #define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16)
400 #define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
401 #define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12)
402 #define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11)
403 #define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
404 #define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 )
405 #define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 )
406 #define IOP13XX_ATUE_STAT_CRS (1 << 7 )
407 #define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 )
408 #define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 )
409 #define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 )
410 #define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 )
411 #define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 )
412 #define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 )
413 #define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 )
415 #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31)
416 #define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30)
417 #define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29)
418 #define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28)
419 #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20)
420 #define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19)
421 #define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18)
422 #define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
423 #define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16)
424 #define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15)
425 #define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14)
426 #define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13)
427 #define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12)
428 #define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 )
429 #define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 )
431 #define IOP13XX_ATUE_IALR_DISABLE (0x00000001)
432 #define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000)
433 #define IOP13XX_ATU_OUMBAR_FUNC_NUM (28)
434 #define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7)
438 #define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\
441 #define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10)
442 #define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14)
443 #define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18)
444 #define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C)
445 #define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20)
446 #define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24)
447 #define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28)
448 #define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C)
449 #define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30)
450 #define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34)
451 #define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38)
452 #define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C)
453 #define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48)
454 #define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50)
455 #define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54)
456 #define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84)
458 #define IOP13XX_MU_WINDOW_SIZE (8 * 1024)
459 #define IOP13XX_MU_BASE_PHYS (0xff000000)
460 #define IOP13XX_MU_BASE_PCI (0xff000000)
461 #define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48)
462 #define IOP13XX_MU_MIMR_CORE_SELECT (15)
466 #define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
467 #define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
470 #define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c)
471 #define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790)
472 #define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794)
473 #define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
474 IOP13XX_PMMR_VIRT_TO_PHYS(\
475 IOP13XX_ATUE_OCCDR))\
476 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
477 #define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
478 IOP13XX_PMMR_VIRT_TO_PHYS(\
479 IOP13XX_ATUX_OCCDR))\
480 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
483 #define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
486 #define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0)
487 #define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4)
488 #define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8)
489 #define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc)
490 #define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
491 #define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
493 #define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180)
496 #define IOP_WDTCR_EN_ARM 0x1e1e1e1e
497 #define IOP_WDTCR_EN 0xe1e1e1e1
498 #define IOP_WDTCR_DIS_ARM 0x1f1f1f1f
499 #define IOP_WDTCR_DIS 0xf1f1f1f1
500 #define IOP_RCSR_WDT (1 << 5)
501 #define IOP13XX_WDTSR_WRITE_EN (1 << 31)
502 #define IOP13XX_WDTCR_IB_RESET (1 << 0)