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29 #include <linux/sched.h>
31 #include <linux/netdevice.h>
33 #include <linux/list.h>
37 #include <linux/socket.h>
38 #include <linux/if_arp.h>
39 #include <linux/wireless.h>
42 #ifdef CONFIG_IPW2100_MONITOR
55 #define IPW_DL_UNINIT 0x80000000
56 #define IPW_DL_NONE 0x00000000
57 #define IPW_DL_ALL 0x7FFFFFFF
85 #define IPW_DL_ERROR (1<<0)
86 #define IPW_DL_WARNING (1<<1)
87 #define IPW_DL_INFO (1<<2)
88 #define IPW_DL_WX (1<<3)
89 #define IPW_DL_HC (1<<5)
90 #define IPW_DL_STATE (1<<6)
92 #define IPW_DL_NOTIF (1<<10)
93 #define IPW_DL_SCAN (1<<11)
94 #define IPW_DL_ASSOC (1<<12)
95 #define IPW_DL_DROP (1<<13)
97 #define IPW_DL_IOCTL (1<<14)
98 #define IPW_DL_RF_KILL (1<<17)
100 #define IPW_DL_MANAGE (1<<15)
101 #define IPW_DL_FW (1<<16)
103 #define IPW_DL_FRAG (1<<21)
104 #define IPW_DL_WEP (1<<22)
105 #define IPW_DL_TX (1<<23)
106 #define IPW_DL_RX (1<<24)
107 #define IPW_DL_ISR (1<<25)
108 #define IPW_DL_IO (1<<26)
109 #define IPW_DL_TRACE (1<<28)
111 #define IPW_DEBUG_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
112 #define IPW_DEBUG_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
113 #define IPW_DEBUG_INFO(f...) IPW_DEBUG(IPW_DL_INFO, ## f)
114 #define IPW_DEBUG_WX(f...) IPW_DEBUG(IPW_DL_WX, ## f)
115 #define IPW_DEBUG_SCAN(f...) IPW_DEBUG(IPW_DL_SCAN, ## f)
116 #define IPW_DEBUG_NOTIF(f...) IPW_DEBUG(IPW_DL_NOTIF, ## f)
117 #define IPW_DEBUG_TRACE(f...) IPW_DEBUG(IPW_DL_TRACE, ## f)
118 #define IPW_DEBUG_RX(f...) IPW_DEBUG(IPW_DL_RX, ## f)
119 #define IPW_DEBUG_TX(f...) IPW_DEBUG(IPW_DL_TX, ## f)
120 #define IPW_DEBUG_ISR(f...) IPW_DEBUG(IPW_DL_ISR, ## f)
121 #define IPW_DEBUG_MANAGEMENT(f...) IPW_DEBUG(IPW_DL_MANAGE, ## f)
122 #define IPW_DEBUG_WEP(f...) IPW_DEBUG(IPW_DL_WEP, ## f)
123 #define IPW_DEBUG_HC(f...) IPW_DEBUG(IPW_DL_HC, ## f)
124 #define IPW_DEBUG_FRAG(f...) IPW_DEBUG(IPW_DL_FRAG, ## f)
125 #define IPW_DEBUG_FW(f...) IPW_DEBUG(IPW_DL_FW, ## f)
126 #define IPW_DEBUG_RF_KILL(f...) IPW_DEBUG(IPW_DL_RF_KILL, ## f)
127 #define IPW_DEBUG_DROP(f...) IPW_DEBUG(IPW_DL_DROP, ## f)
128 #define IPW_DEBUG_IO(f...) IPW_DEBUG(IPW_DL_IO, ## f)
129 #define IPW_DEBUG_IOCTL(f...) IPW_DEBUG(IPW_DL_IOCTL, ## f)
130 #define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
131 #define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
141 #define NUMBER_OF_BD_PER_COMMAND_PACKET 1
142 #define NUMBER_OF_BD_PER_DATA_PACKET 2
144 #define IPW_MAX_BDS 6
145 #define NUMBER_OF_OVERHEAD_BDS_PER_PACKETR 2
146 #define NUMBER_OF_BDS_TO_LEAVE_FOR_COMMANDS 1
148 #define REQUIRED_SPACE_IN_RING_FOR_COMMAND_PACKET \
149 (IPW_BD_QUEUE_W_R_MIN_SPARE + NUMBER_OF_BD_PER_COMMAND_PACKET)
170 #define IPW_BD_QUEUE_LENGTH(n) (1<<n)
171 #define IPW_BD_ALIGNMENT(L) (L*sizeof(struct ipw2100_bd))
173 #define IPW_BD_STATUS_TX_FRAME_802_3 0x00
174 #define IPW_BD_STATUS_TX_FRAME_NOT_LAST_FRAGMENT 0x01
175 #define IPW_BD_STATUS_TX_FRAME_COMMAND 0x02
176 #define IPW_BD_STATUS_TX_FRAME_802_11 0x04
177 #define IPW_BD_STATUS_TX_INTERRUPT_ENABLE 0x08
203 #define RX_QUEUE_LENGTH 256
204 #define TX_QUEUE_LENGTH 256
205 #define HW_QUEUE_LENGTH 256
207 #define TX_PENDED_QUEUE_LENGTH (TX_QUEUE_LENGTH / NUMBER_OF_BD_PER_DATA_PACKET)
209 #define STATUS_TYPE_MASK 0x0000000f
210 #define COMMAND_STATUS_VAL 0
211 #define STATUS_CHANGE_VAL 1
212 #define P80211_DATA_VAL 2
213 #define P8023_DATA_VAL 3
214 #define HOST_NOTIFICATION_VAL 4
216 #define IPW2100_RSSI_TO_DBM (-98)
222 #define IPW_STATUS_FLAG_DECRYPTED (1<<0)
223 #define IPW_STATUS_FLAG_WEP_ENCRYPTED (1<<1)
224 #define IPW_STATUS_FLAG_CRC_ERROR (1<<2)
239 #define HOST_COMMAND_PARAMS_REG_LEN 100
240 #define CMD_STATUS_PARAMS_REG_LEN 3
242 #define IPW_WPA_CAPABILITIES 0x1
243 #define IPW_WPA_LISTENINTERVAL 0x2
244 #define IPW_WPA_AP_ADDRESS 0x4
246 #define IPW_MAX_VAR_IE_LEN ((HOST_COMMAND_PARAMS_REG_LEN - 4) * sizeof(u32))
260 #define IPW_MONITOR 2
353 #define FRAG_DISABLED (1<<31)
354 #define RTS_DISABLED (1<<31)
355 #define MAX_RTS_THRESHOLD 2304U
356 #define MIN_RTS_THRESHOLD 1U
357 #define DEFAULT_RTS_THRESHOLD 1000U
359 #define DEFAULT_BEACON_INTERVAL 100U
360 #define DEFAULT_SHORT_RETRY_LIMIT 7U
361 #define DEFAULT_LONG_RETRY_LIMIT 4U
378 #define MAX_KEY_SIZE 16
381 #define IPW2100_WEP_ENABLE (1<<1)
382 #define IPW2100_WEP_DROP_CLEAR (1<<2)
384 #define IPW_NONE_CIPHER (1<<0)
385 #define IPW_WEP40_CIPHER (1<<1)
386 #define IPW_TKIP_CIPHER (1<<2)
387 #define IPW_CCMP_CIPHER (1<<4)
388 #define IPW_WEP104_CIPHER (1<<5)
389 #define IPW_CKIP_CIPHER (1<<6)
391 #define IPW_AUTH_OPEN 0
392 #define IPW_AUTH_SHARED 1
393 #define IPW_AUTH_LEAP 2
394 #define IPW_AUTH_LEAP_CISCO_ID 0x80
402 #define INIT_STAT(x) do { \
403 (x)->value = (x)->hi = 0; \
404 (x)->lo = 0x7fffffff; \
406 #define SET_STAT(x,y) do { \
408 if ((x)->value > (x)->hi) (x)->hi = (x)->value; \
409 if ((x)->value < (x)->lo) (x)->lo = (x)->value; \
411 #define INC_STAT(x) do { if (++(x)->value > (x)->hi) (x)->hi = (x)->value; } \
413 #define DEC_STAT(x) do { if (--(x)->value < (x)->lo) (x)->lo = (x)->value; } \
416 #define IPW2100_ERROR_QUEUE 5
429 #define STATUS_POWERED (1<<0)
430 #define STATUS_CMD_ACTIVE (1<<1)
431 #define STATUS_RUNNING (1<<2)
432 #define STATUS_ENABLED (1<<3)
433 #define STATUS_STOPPING (1<<4)
434 #define STATUS_INITIALIZED (1<<5)
435 #define STATUS_ASSOCIATING (1<<9)
436 #define STATUS_ASSOCIATED (1<<10)
437 #define STATUS_INT_ENABLED (1<<11)
438 #define STATUS_RF_KILL_HW (1<<12)
439 #define STATUS_RF_KILL_SW (1<<13)
440 #define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)
441 #define STATUS_EXIT_PENDING (1<<14)
443 #define STATUS_SCAN_PENDING (1<<23)
444 #define STATUS_SCANNING (1<<24)
445 #define STATUS_SCAN_ABORTING (1<<25)
446 #define STATUS_SCAN_COMPLETE (1<<26)
447 #define STATUS_WX_EVENT_PENDING (1<<27)
448 #define STATUS_RESET_PENDING (1<<29)
449 #define STATUS_SECURITY_UPDATED (1<<30)
452 #define IPW_STATE_INITIALIZED (1<<0)
453 #define IPW_STATE_COUNTRY_FOUND (1<<1)
454 #define IPW_STATE_ASSOCIATED (1<<2)
455 #define IPW_STATE_ASSN_LOST (1<<3)
456 #define IPW_STATE_ASSN_CHANGED (1<<4)
457 #define IPW_STATE_SCAN_COMPLETE (1<<5)
458 #define IPW_STATE_ENTERED_PSP (1<<6)
459 #define IPW_STATE_LEFT_PSP (1<<7)
460 #define IPW_STATE_RF_KILL (1<<8)
461 #define IPW_STATE_DISABLED (1<<9)
462 #define IPW_STATE_POWER_DOWN (1<<10)
463 #define IPW_STATE_SCANNING (1<<11)
465 #define CFG_STATIC_CHANNEL (1<<0)
466 #define CFG_STATIC_ESSID (1<<1)
467 #define CFG_STATIC_BSSID (1<<2)
468 #define CFG_CUSTOM_MAC (1<<3)
469 #define CFG_LONG_PREAMBLE (1<<4)
470 #define CFG_ASSOCIATE (1<<6)
471 #define CFG_FIXED_RATE (1<<7)
472 #define CFG_ADHOC_CREATE (1<<8)
473 #define CFG_PASSIVE_SCAN (1<<10)
474 #ifdef CONFIG_IPW2100_MONITOR
475 #define CFG_CRC_CHECK (1<<11)
478 #define CAP_SHARED_KEY (1<<0)
479 #define CAP_PRIVACY_ON (1<<1)
608 #define HOST_COMPLETE 2
609 #define SYSTEM_CONFIG 6
611 #define MANDATORY_BSSID 9
612 #define AUTHENTICATION_TYPE 10
613 #define ADAPTER_ADDRESS 11
615 #define INTERNATIONAL_MODE 13
617 #define RTS_THRESHOLD 15
618 #define FRAG_THRESHOLD 16
619 #define POWER_MODE 17
621 #define BASIC_TX_RATES 19
622 #define WEP_KEY_INFO 20
623 #define WEP_KEY_INDEX 25
625 #define ADD_MULTICAST 27
626 #define CLEAR_ALL_MULTICAST 28
627 #define BEACON_INTERVAL 29
628 #define ATIM_WINDOW 30
629 #define CLEAR_STATISTICS 31
631 #define TX_POWER_INDEX 36
632 #define BROADCAST_SCAN 43
633 #define CARD_DISABLE 44
634 #define PREFERRED_BSSID 45
635 #define SET_SCAN_OPTIONS 46
636 #define SCAN_DWELL_TIME 47
637 #define SWEEP_TABLE 48
638 #define AP_OR_STATION_TABLE 49
639 #define GROUP_ORDINALS 50
640 #define SHORT_RETRY_LIMIT 51
641 #define LONG_RETRY_LIMIT 52
643 #define HOST_PRE_POWER_DOWN 58
644 #define CARD_DISABLE_PHY_OFF 61
645 #define MSDU_TX_RATES 62
648 #define SET_STATION_STAT_BITS 64
649 #define CLEAR_STATIONS_STAT_BITS 65
650 #define LEAP_ROGUE_MODE 66 //TODO tbw replaced by CFG_LEAP_ROGUE_AP
651 #define SET_SECURITY_INFORMATION 67
652 #define DISASSOCIATION_BSSID 68
653 #define SET_WPA_IE 69
656 #define IPW_CFG_MONITOR 0x00004
657 #define IPW_CFG_PREAMBLE_AUTO 0x00010
658 #define IPW_CFG_IBSS_AUTO_START 0x00020
659 #define IPW_CFG_LOOPBACK 0x00100
660 #define IPW_CFG_ANSWER_BCSSID_PROBE 0x00800
661 #define IPW_CFG_BT_SIDEBAND_SIGNAL 0x02000
662 #define IPW_CFG_802_1x_ENABLE 0x04000
663 #define IPW_CFG_BSS_MASK 0x08000
664 #define IPW_CFG_IBSS_MASK 0x10000
666 #define IPW_SCAN_NOASSOCIATE (1<<0)
667 #define IPW_SCAN_MIXED_CELL (1<<1)
669 #define IPW_SCAN_PASSIVE (1<<3)
671 #define IPW_NIC_FATAL_ERROR 0x2A7F0
672 #define IPW_ERROR_ADDR(x) (x & 0x3FFFF)
673 #define IPW_ERROR_CODE(x) ((x & 0xFF000000) >> 24)
674 #define IPW2100_ERR_C3_CORRUPTION (0x10 << 24)
675 #define IPW2100_ERR_MSG_TIMEOUT (0x11 << 24)
676 #define IPW2100_ERR_FW_LOAD (0x12 << 24)
678 #define IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND 0x200
679 #define IPW_MEM_SRAM_HOST_INTERRUPT_AREA_LOWER_BOUND IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x0D80
681 #define IPW_MEM_HOST_SHARED_RX_BD_BASE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x40)
682 #define IPW_MEM_HOST_SHARED_RX_STATUS_BASE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x44)
683 #define IPW_MEM_HOST_SHARED_RX_BD_SIZE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x48)
684 #define IPW_MEM_HOST_SHARED_RX_READ_INDEX (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0xa0)
686 #define IPW_MEM_HOST_SHARED_TX_QUEUE_BD_BASE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x00)
687 #define IPW_MEM_HOST_SHARED_TX_QUEUE_BD_SIZE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x04)
688 #define IPW_MEM_HOST_SHARED_TX_QUEUE_READ_INDEX (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x80)
690 #define IPW_MEM_HOST_SHARED_RX_WRITE_INDEX \
691 (IPW_MEM_SRAM_HOST_INTERRUPT_AREA_LOWER_BOUND + 0x20)
693 #define IPW_MEM_HOST_SHARED_TX_QUEUE_WRITE_INDEX \
694 (IPW_MEM_SRAM_HOST_INTERRUPT_AREA_LOWER_BOUND)
696 #define IPW_MEM_HOST_SHARED_ORDINALS_TABLE_1 (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x180)
697 #define IPW_MEM_HOST_SHARED_ORDINALS_TABLE_2 (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x184)
699 #define IPW2100_INTA_TX_TRANSFER (0x00000001) // Bit 0 (LSB)
700 #define IPW2100_INTA_RX_TRANSFER (0x00000002) // Bit 1
701 #define IPW2100_INTA_TX_COMPLETE (0x00000004) // Bit 2
702 #define IPW2100_INTA_EVENT_INTERRUPT (0x00000008) // Bit 3
703 #define IPW2100_INTA_STATUS_CHANGE (0x00000010) // Bit 4
704 #define IPW2100_INTA_BEACON_PERIOD_EXPIRED (0x00000020) // Bit 5
705 #define IPW2100_INTA_SLAVE_MODE_HOST_COMMAND_DONE (0x00010000) // Bit 16
706 #define IPW2100_INTA_FW_INIT_DONE (0x01000000) // Bit 24
707 #define IPW2100_INTA_FW_CALIBRATION_CALC (0x02000000) // Bit 25
708 #define IPW2100_INTA_FATAL_ERROR (0x40000000) // Bit 30
709 #define IPW2100_INTA_PARITY_ERROR (0x80000000) // Bit 31 (MSB)
711 #define IPW_AUX_HOST_RESET_REG_PRINCETON_RESET (0x00000001)
712 #define IPW_AUX_HOST_RESET_REG_FORCE_NMI (0x00000002)
713 #define IPW_AUX_HOST_RESET_REG_PCI_HOST_CLUSTER_FATAL_NMI (0x00000004)
714 #define IPW_AUX_HOST_RESET_REG_CORE_FATAL_NMI (0x00000008)
715 #define IPW_AUX_HOST_RESET_REG_SW_RESET (0x00000080)
716 #define IPW_AUX_HOST_RESET_REG_MASTER_DISABLED (0x00000100)
717 #define IPW_AUX_HOST_RESET_REG_STOP_MASTER (0x00000200)
719 #define IPW_AUX_HOST_GP_CNTRL_BIT_CLOCK_READY (0x00000001) // Bit 0 (LSB)
720 #define IPW_AUX_HOST_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY (0x00000002) // Bit 1
721 #define IPW_AUX_HOST_GP_CNTRL_BIT_INIT_DONE (0x00000004) // Bit 2
722 #define IPW_AUX_HOST_GP_CNTRL_BITS_SYS_CONFIG (0x000007c0) // Bits 6-10
723 #define IPW_AUX_HOST_GP_CNTRL_BIT_BUS_TYPE (0x00000200) // Bit 9
724 #define IPW_AUX_HOST_GP_CNTRL_BIT_BAR0_BLOCK_SIZE (0x00000400) // Bit 10
725 #define IPW_AUX_HOST_GP_CNTRL_BIT_USB_MODE (0x20000000) // Bit 29
726 #define IPW_AUX_HOST_GP_CNTRL_BIT_HOST_FORCES_SYS_CLK (0x40000000) // Bit 30
727 #define IPW_AUX_HOST_GP_CNTRL_BIT_FW_FORCES_SYS_CLK (0x80000000) // Bit 31 (MSB)
729 #define IPW_BIT_GPIO_GPIO1_MASK 0x0000000C
730 #define IPW_BIT_GPIO_GPIO3_MASK 0x000000C0
731 #define IPW_BIT_GPIO_GPIO1_ENABLE 0x00000008
732 #define IPW_BIT_GPIO_RF_KILL 0x00010000
734 #define IPW_BIT_GPIO_LED_OFF 0x00002000 // Bit 13 = 1
736 #define IPW_REG_DOMAIN_0_OFFSET 0x0000
737 #define IPW_REG_DOMAIN_1_OFFSET IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND
739 #define IPW_REG_INTA IPW_REG_DOMAIN_0_OFFSET + 0x0008
740 #define IPW_REG_INTA_MASK IPW_REG_DOMAIN_0_OFFSET + 0x000C
741 #define IPW_REG_INDIRECT_ACCESS_ADDRESS IPW_REG_DOMAIN_0_OFFSET + 0x0010
742 #define IPW_REG_INDIRECT_ACCESS_DATA IPW_REG_DOMAIN_0_OFFSET + 0x0014
743 #define IPW_REG_AUTOINCREMENT_ADDRESS IPW_REG_DOMAIN_0_OFFSET + 0x0018
744 #define IPW_REG_AUTOINCREMENT_DATA IPW_REG_DOMAIN_0_OFFSET + 0x001C
745 #define IPW_REG_RESET_REG IPW_REG_DOMAIN_0_OFFSET + 0x0020
746 #define IPW_REG_GP_CNTRL IPW_REG_DOMAIN_0_OFFSET + 0x0024
747 #define IPW_REG_GPIO IPW_REG_DOMAIN_0_OFFSET + 0x0030
748 #define IPW_REG_FW_TYPE IPW_REG_DOMAIN_1_OFFSET + 0x0188
749 #define IPW_REG_FW_VERSION IPW_REG_DOMAIN_1_OFFSET + 0x018C
750 #define IPW_REG_FW_COMPATABILITY_VERSION IPW_REG_DOMAIN_1_OFFSET + 0x0190
752 #define IPW_REG_INDIRECT_ADDR_MASK 0x00FFFFFC
754 #define IPW_INTERRUPT_MASK 0xC1010013
756 #define IPW2100_CONTROL_REG 0x220000
757 #define IPW2100_CONTROL_PHY_OFF 0x8
759 #define IPW2100_COMMAND 0x00300004
760 #define IPW2100_COMMAND_PHY_ON 0x0
761 #define IPW2100_COMMAND_PHY_OFF 0x1
764 #define IPW_REG_DOA_DEBUG_AREA_START IPW_REG_DOMAIN_0_OFFSET + 0x0090
765 #define IPW_REG_DOA_DEBUG_AREA_END IPW_REG_DOMAIN_0_OFFSET + 0x00FF
766 #define IPW_DATA_DOA_DEBUG_VALUE 0xd55555d5
768 #define IPW_INTERNAL_REGISTER_HALT_AND_RESET 0x003000e0
770 #define IPW_WAIT_CLOCK_STABILIZATION_DELAY 50 // micro seconds
771 #define IPW_WAIT_RESET_ARC_COMPLETE_DELAY 10 // micro seconds
772 #define IPW_WAIT_RESET_MASTER_ASSERT_COMPLETE_DELAY 10 // micro seconds
775 #define IPW_BD_QUEUE_W_R_MIN_SPARE 2
777 #define IPW_CACHE_LINE_LENGTH_DEFAULT 0x80
779 #define IPW_CARD_DISABLE_PHY_OFF_COMPLETE_WAIT 100 // 100 milli
780 #define IPW_PREPARE_POWER_DOWN_COMPLETE_WAIT 100 // 100 milli
782 #define IPW_HEADER_802_11_SIZE sizeof(struct libipw_hdr_3addr)
783 #define IPW_MAX_80211_PAYLOAD_SIZE 2304U
784 #define IPW_MAX_802_11_PAYLOAD_LENGTH 2312
785 #define IPW_MAX_ACCEPTABLE_TX_FRAME_LENGTH 1536
786 #define IPW_MIN_ACCEPTABLE_RX_FRAME_LENGTH 60
787 #define IPW_MAX_ACCEPTABLE_RX_FRAME_LENGTH \
788 (IPW_MAX_ACCEPTABLE_TX_FRAME_LENGTH + IPW_HEADER_802_11_SIZE - \
789 sizeof(struct ethhdr))
791 #define IPW_802_11_FCS_LENGTH 4
792 #define IPW_RX_NIC_BUFFER_LENGTH \
793 (IPW_MAX_802_11_PAYLOAD_LENGTH + IPW_HEADER_802_11_SIZE + \
794 IPW_802_11_FCS_LENGTH)
796 #define IPW_802_11_PAYLOAD_OFFSET \
797 (sizeof(struct libipw_hdr_3addr) + \
798 sizeof(struct libipw_snap_hdr))
811 #define TX_RATE_1_MBIT 0x0001
812 #define TX_RATE_2_MBIT 0x0002
813 #define TX_RATE_5_5_MBIT 0x0004
814 #define TX_RATE_11_MBIT 0x0008
815 #define TX_RATE_MASK 0x000F
816 #define DEFAULT_TX_RATES 0x000F
818 #define IPW_POWER_MODE_CAM 0x00 //(always on)
819 #define IPW_POWER_INDEX_1 0x01
820 #define IPW_POWER_INDEX_2 0x02
821 #define IPW_POWER_INDEX_3 0x03
822 #define IPW_POWER_INDEX_4 0x04
823 #define IPW_POWER_INDEX_5 0x05
824 #define IPW_POWER_AUTO 0x06
825 #define IPW_POWER_MASK 0x0F
826 #define IPW_POWER_ENABLED 0x10
827 #define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK)
829 #define IPW_TX_POWER_AUTO 0
830 #define IPW_TX_POWER_ENHANCED 1
832 #define IPW_TX_POWER_DEFAULT 32
833 #define IPW_TX_POWER_MIN 0
834 #define IPW_TX_POWER_MAX 16
835 #define IPW_TX_POWER_MIN_DBM (-12)
836 #define IPW_TX_POWER_MAX_DBM 16
838 #define FW_SCAN_DONOT_ASSOCIATE 0x0001 // Dont Attempt to Associate after Scan
839 #define FW_SCAN_PASSIVE 0x0008 // Force PASSSIVE Scan
841 #define REG_MIN_CHANNEL 0
842 #define REG_MAX_CHANNEL 14
844 #define REG_CHANNEL_MASK 0x00003FFF
845 #define IPW_IBSS_11B_DEFAULT_MASK 0x87ff
847 #define DIVERSITY_EITHER 0 // Use both antennas
848 #define DIVERSITY_ANTENNA_A 1 // Use antenna A
849 #define DIVERSITY_ANTENNA_B 2 // Use antenna B
851 #define HOST_COMMAND_WAIT 0
852 #define HOST_COMMAND_NO_WAIT 1
855 #define LOCK_DRIVER 1
858 #define TYPE_SWEEP_ORD 0x000D
859 #define TYPE_IBSS_STTN_ORD 0x000E
860 #define TYPE_BSS_AP_ORD 0x000F
861 #define TYPE_RAW_BEACON_ENTRY 0x0010
862 #define TYPE_CALIBRATION_DATA 0x0011
863 #define TYPE_ROGUE_AP_DATA 0x0012
864 #define TYPE_ASSOCIATION_REQUEST 0x0013
865 #define TYPE_REASSOCIATION_REQUEST 0x0014
867 #define HW_FEATURE_RFKILL 0x0001
868 #define RF_KILLSWITCH_OFF 1
869 #define RF_KILLSWITCH_ON 0
871 #define IPW_COMMAND_POOL_SIZE 40
873 #define IPW_START_ORD_TAB_1 1
874 #define IPW_START_ORD_TAB_2 1000
876 #define IPW_ORD_TAB_1_ENTRY_SIZE sizeof(u32)
878 #define IS_ORDINAL_TABLE_ONE(mgr,id) \
879 ((id >= IPW_START_ORD_TAB_1) && (id < mgr->table1_size))
880 #define IS_ORDINAL_TABLE_TWO(mgr,id) \
881 ((id >= IPW_START_ORD_TAB_2) && (id < (mgr->table2_size + IPW_START_ORD_TAB_2)))
883 #define BSS_ID_LENGTH 6
1091 #define IPW_FIRST_VARIABLE_LENGTH_ORDINAL 1001
1115 #define IPW_LAST_VARIABLE_LENGTH_ORDINAL 1018
1117 #ifndef WIRELESS_SPY
1118 #define WIRELESS_SPY // enable iwspy support
1121 #define IPW_HOST_FW_SHARED_AREA0 0x0002f200
1122 #define IPW_HOST_FW_SHARED_AREA0_END 0x0002f510 // 0x310 bytes
1124 #define IPW_HOST_FW_SHARED_AREA1 0x0002f610
1125 #define IPW_HOST_FW_SHARED_AREA1_END 0x0002f630 // 0x20 bytes
1127 #define IPW_HOST_FW_SHARED_AREA2 0x0002fa00
1128 #define IPW_HOST_FW_SHARED_AREA2_END 0x0002fa20 // 0x20 bytes
1130 #define IPW_HOST_FW_SHARED_AREA3 0x0002fc00
1131 #define IPW_HOST_FW_SHARED_AREA3_END 0x0002fc10 // 0x10 bytes
1133 #define IPW_HOST_FW_INTERRUPT_AREA 0x0002ff80
1134 #define IPW_HOST_FW_INTERRUPT_AREA_END 0x00030000 // 0x80 bytes
1155 #define MAX_FW_VERSION_LEN 14