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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Enumerations | |
| enum | { ASYNC_EVENT_LINK_DOWN = 0x0, ASYNC_EVENT_LINK_UP = 0x1 } |
| enum | { QTYPE_EQ = 1, QTYPE_CQ, QTYPE_MCCQ, QTYPE_WRBQ, QTYPE_DPDUQ, QTYPE_SGL } |
Variables | |
| struct be_async_event_link_state | __packed |
| #define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */ |
| #define BE_NUMBER_OF_FIELD | ( | _type_, | |
| _field_ | |||
| ) | (FIELD_SIZEOF(_type_, _field_)/sizeof((((_type_ *)0)->_field_[0])))\ |
| #define CMD_CXN_KILLED_ICD_INVALID |
| #define CMD_CXN_KILLED_INVALID_DATASN_RCVD |
| #define CMD_CXN_KILLED_ITT_INVALID |
| #define CMD_CXN_KILLED_LUN_INVALID |
| #define CMD_CXN_KILLED_SEQ_OUTOFORDER |
| #define CMD_INVALIDATED_NOTIFY |
| #define CMD_KILLED_INVALID_R2T_RCVD |
| #define CMD_KILLED_INVALID_STATSN_RCVD |
| #define CONNECTION_UPLOAD_ABORT |
| #define CONNECTION_UPLOAD_ABORT_RESET |
| #define CONNECTION_UPLOAD_ABORT_WITH_SEQ |
| #define CONNECTION_UPLOAD_GRACEFUL 1 /* Graceful upload */ |
| #define CXN_INVALIDATE_INDEX_NOTIFY |
| #define CXN_INVALIDATE_NOTIFY |
| #define CXN_KILLED_AHS_RCVD |
| #define CXN_KILLED_BAD_UNSOL_PDU_RCVD |
| #define CXN_KILLED_BAD_WRB_INDEX_ERROR |
| #define CXN_KILLED_BURST_LEN_MISMATCH |
| #define CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN |
| #define CXN_KILLED_FIN_RCVD |
| #define CXN_KILLED_HDR_DIGEST_ERR |
| #define CXN_KILLED_IMM_DATA_RCVD |
| #define CXN_KILLED_INVALID_ITT_TTT_RCVD |
| #define CXN_KILLED_OVER_RUN_RESIDUAL |
| #define CXN_KILLED_PDU_SIZE_EXCEEDS_DSL |
| #define CXN_KILLED_RST_RCVD |
| #define CXN_KILLED_RST_SENT |
| #define CXN_KILLED_STALE_ITT_TTT_RCVD |
| #define CXN_KILLED_SYN_RCVD |
| #define CXN_KILLED_TIMED_OUT |
| #define CXN_KILLED_UNDER_RUN_RESIDUAL |
| #define CXN_KILLED_UNKNOWN_HDR |
| #define DB_WRB_POST_CID_MASK 0x3FF /* bits 0 - 9 */ |
| #define DRIVERMSG_NOTIFY |
| #define INI_RD_CMD |
| #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */ |
| #define MPU_MAILBOX_DB_OFFSET 0x160 |
Used for driver communication with the FW. The software must write this register twice to post any command. First, it writes the register with hi=1 and the upper bits of the physical address for the MAILBOX structure. Software must poll the ready bit until this is acknowledged. Then, sotware writes the register with hi=0 with the lower bits in the address. It must poll the ready bit until the command is complete. Upon completion, the MAILBOX will contain a valid completion queue entry.
| #define OPCODE_COMMON_CQ_CREATE 12 |
| #define OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES 2 |
| #define OPCODE_COMMON_ISCSI_ERROR_RECOVERY_INVALIDATE_COMMANDS 1 |
| #define OPCODE_COMMON_ISCSI_NTWK_CONFIG_STATELESS_IP_ADDR 17 |
| #define OPCODE_COMMON_ISCSI_NTWK_MODIFY_DEFAULT_GATEWAY 23 |
| #define OPCODE_COMMON_ISCSI_SET_FRAGNUM_BITS_FOR_SGL_CRA 61 |
| #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */ |
| #define SOL_CMD_COMPLETE |
| #define SOL_CMD_KILLED_DATA_DIGEST_ERR |
| #define SOL_CMD_KILLED_DIF_ERR |
| #define TGT_DATAIN_CMD |
| #define TGT_DM_CMD |
| #define TGT_SOS_PDU |
| #define TGT_STS_CMD |
| #define UNSOL_DATA_DIGEST_ERROR_NOTIFY |
| #define UNSOL_DATA_NOTIFY 29 /* Unsolicited data notify.*/ |
| #define UNSOL_HDR_NOTIFY 28 /* Unsolicited header notify.*/ |
| anonymous enum |
| anonymous enum |
| unsigned int alloc_mcc_tag | ( | struct beiscsi_hba * | phba | ) |
| int be_chk_reset_complete | ( | struct beiscsi_hba * | phba | ) |
| int be_cmd_create_default_pdu_queue | ( | struct be_ctrl_info * | ctrl, |
| struct be_queue_info * | cq, | ||
| struct be_queue_info * | dq, | ||
| int | length, | ||
| int | entry_size | ||
| ) |
| int be_cmd_fw_initialize | ( | struct be_ctrl_info * | ctrl | ) |
| unsigned int be_cmd_get_initname | ( | struct beiscsi_hba * | phba | ) |
| unsigned int be_cmd_get_port_speed | ( | struct beiscsi_hba * | phba | ) |
| int be_cmd_iscsi_post_sgl_pages | ( | struct be_ctrl_info * | ctrl, |
| struct be_dma_mem * | q_mem, | ||
| u32 | page_offset, | ||
| u32 | num_pages | ||
| ) |
| int be_cmd_set_vlan | ( | struct beiscsi_hba * | phba, |
| uint16_t | vlan_tag | ||
| ) |
| int be_cmd_wrbq_create | ( | struct be_ctrl_info * | ctrl, |
| struct be_dma_mem * | q_mem, | ||
| struct be_queue_info * | wrbq | ||
| ) |
| int be_mbox_notify | ( | struct be_ctrl_info * | ctrl | ) |
| int be_mcc_compl_process_isr | ( | struct be_ctrl_info * | ctrl, |
| struct be_mcc_compl * | compl | ||
| ) |
| void be_mcc_notify | ( | struct beiscsi_hba * | phba | ) |
| int be_mcc_notify_wait | ( | struct beiscsi_hba * | phba | ) |
| int be_poll_mcc | ( | struct be_ctrl_info * | ctrl | ) |
| void beiscsi_async_link_state_process | ( | struct beiscsi_hba * | phba, |
| struct be_async_event_link_state * | evt | ||
| ) |
| int beiscsi_cmd_cq_create | ( | struct be_ctrl_info * | ctrl, |
| struct be_queue_info * | cq, | ||
| struct be_queue_info * | eq, | ||
| bool | sol_evts, | ||
| bool | no_delay, | ||
| int | num_cqe_dma_coalesce | ||
| ) |
| int beiscsi_cmd_eq_create | ( | struct be_ctrl_info * | ctrl, |
| struct be_queue_info * | eq, | ||
| int | eq_delay | ||
| ) |
| int beiscsi_cmd_mccq_create | ( | struct beiscsi_hba * | phba, |
| struct be_queue_info * | mccq, | ||
| struct be_queue_info * | cq | ||
| ) |
| int beiscsi_cmd_q_destroy | ( | struct be_ctrl_info * | ctrl, |
| struct be_queue_info * | q, | ||
| int | type | ||
| ) |
| int beiscsi_cmd_reset_function | ( | struct beiscsi_hba * | phba | ) |
| int beiscsi_pci_soft_reset | ( | struct beiscsi_hba * | phba | ) |
Copyright (C) 2005 - 2011 Emulex All rights reserved.
This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License version 2 as published by the Free Software Foundation. The full GNU General Public License is included in this distribution in the file called COPYING.
Contact Information: linux-drivers@emulex.com
Emulex 3333 Susan Street Costa Mesa, CA 92626
| void free_mcc_tag | ( | struct be_ctrl_info * | ctrl, |
| unsigned int | tag | ||
| ) |
| int mgmt_check_supported_fw | ( | struct be_ctrl_info * | ctrl, |
| struct beiscsi_hba * | phba | ||
| ) |
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1.8.2