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ipw2200.h
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1 /******************************************************************************
2 
3  Copyright(c) 2003 - 2006 Intel Corporation. All rights reserved.
4 
5  This program is free software; you can redistribute it and/or modify it
6  under the terms of version 2 of the GNU General Public License as
7  published by the Free Software Foundation.
8 
9  This program is distributed in the hope that it will be useful, but WITHOUT
10  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12  more details.
13 
14  You should have received a copy of the GNU General Public License along with
15  this program; if not, write to the Free Software Foundation, Inc., 59
16  Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 
18  The full GNU General Public License is included in this distribution in the
19  file called LICENSE.
20 
21  Contact Information:
22  Intel Linux Wireless <[email protected]>
23  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 
25 ******************************************************************************/
26 
27 #ifndef __ipw2200_h__
28 #define __ipw2200_h__
29 
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/init.h>
33 #include <linux/interrupt.h>
34 #include <linux/mutex.h>
35 
36 #include <linux/pci.h>
37 #include <linux/netdevice.h>
38 #include <linux/ethtool.h>
39 #include <linux/skbuff.h>
40 #include <linux/etherdevice.h>
41 #include <linux/delay.h>
42 #include <linux/random.h>
43 #include <linux/dma-mapping.h>
44 
45 #include <linux/firmware.h>
46 #include <linux/wireless.h>
47 #include <linux/jiffies.h>
48 #include <asm/io.h>
49 
50 #include <net/lib80211.h>
51 #include <net/ieee80211_radiotap.h>
52 
53 #define DRV_NAME "ipw2200"
54 
55 #include <linux/workqueue.h>
56 
57 #include "libipw.h"
58 
59 /* Authentication and Association States */
61  CMAS_INIT = 0,
75 };
76 
77 #define IPW_WAIT (1<<0)
78 #define IPW_QUIET (1<<1)
79 #define IPW_ROAMING (1<<2)
80 
81 #define IPW_POWER_MODE_CAM 0x00 //(always on)
82 #define IPW_POWER_INDEX_1 0x01
83 #define IPW_POWER_INDEX_2 0x02
84 #define IPW_POWER_INDEX_3 0x03
85 #define IPW_POWER_INDEX_4 0x04
86 #define IPW_POWER_INDEX_5 0x05
87 #define IPW_POWER_AC 0x06
88 #define IPW_POWER_BATTERY 0x07
89 #define IPW_POWER_LIMIT 0x07
90 #define IPW_POWER_MASK 0x0F
91 #define IPW_POWER_ENABLED 0x10
92 #define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK)
93 
94 #define IPW_CMD_HOST_COMPLETE 2
95 #define IPW_CMD_POWER_DOWN 4
96 #define IPW_CMD_SYSTEM_CONFIG 6
97 #define IPW_CMD_MULTICAST_ADDRESS 7
98 #define IPW_CMD_SSID 8
99 #define IPW_CMD_ADAPTER_ADDRESS 11
100 #define IPW_CMD_PORT_TYPE 12
101 #define IPW_CMD_RTS_THRESHOLD 15
102 #define IPW_CMD_FRAG_THRESHOLD 16
103 #define IPW_CMD_POWER_MODE 17
104 #define IPW_CMD_WEP_KEY 18
105 #define IPW_CMD_TGI_TX_KEY 19
106 #define IPW_CMD_SCAN_REQUEST 20
107 #define IPW_CMD_ASSOCIATE 21
108 #define IPW_CMD_SUPPORTED_RATES 22
109 #define IPW_CMD_SCAN_ABORT 23
110 #define IPW_CMD_TX_FLUSH 24
111 #define IPW_CMD_QOS_PARAMETERS 25
112 #define IPW_CMD_SCAN_REQUEST_EXT 26
113 #define IPW_CMD_DINO_CONFIG 30
114 #define IPW_CMD_RSN_CAPABILITIES 31
115 #define IPW_CMD_RX_KEY 32
116 #define IPW_CMD_CARD_DISABLE 33
117 #define IPW_CMD_SEED_NUMBER 34
118 #define IPW_CMD_TX_POWER 35
119 #define IPW_CMD_COUNTRY_INFO 36
120 #define IPW_CMD_AIRONET_INFO 37
121 #define IPW_CMD_AP_TX_POWER 38
122 #define IPW_CMD_CCKM_INFO 39
123 #define IPW_CMD_CCX_VER_INFO 40
124 #define IPW_CMD_SET_CALIBRATION 41
125 #define IPW_CMD_SENSITIVITY_CALIB 42
126 #define IPW_CMD_RETRY_LIMIT 51
127 #define IPW_CMD_IPW_PRE_POWER_DOWN 58
128 #define IPW_CMD_VAP_BEACON_TEMPLATE 60
129 #define IPW_CMD_VAP_DTIM_PERIOD 61
130 #define IPW_CMD_EXT_SUPPORTED_RATES 62
131 #define IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT 63
132 #define IPW_CMD_VAP_QUIET_INTERVALS 64
133 #define IPW_CMD_VAP_CHANNEL_SWITCH 65
134 #define IPW_CMD_VAP_MANDATORY_CHANNELS 66
135 #define IPW_CMD_VAP_CELL_PWR_LIMIT 67
136 #define IPW_CMD_VAP_CF_PARAM_SET 68
137 #define IPW_CMD_VAP_SET_BEACONING_STATE 69
138 #define IPW_CMD_MEASUREMENT 80
139 #define IPW_CMD_POWER_CAPABILITY 81
140 #define IPW_CMD_SUPPORTED_CHANNELS 82
141 #define IPW_CMD_TPC_REPORT 83
142 #define IPW_CMD_WME_INFO 84
143 #define IPW_CMD_PRODUCTION_COMMAND 85
144 #define IPW_CMD_LINKSYS_EOU_INFO 90
145 
146 #define RFD_SIZE 4
147 #define NUM_TFD_CHUNKS 6
148 
149 #define TX_QUEUE_SIZE 32
150 #define RX_QUEUE_SIZE 32
151 
152 #define DINO_CMD_WEP_KEY 0x08
153 #define DINO_CMD_TX 0x0B
154 #define DCT_ANTENNA_A 0x01
155 #define DCT_ANTENNA_B 0x02
156 
157 #define IPW_A_MODE 0
158 #define IPW_B_MODE 1
159 #define IPW_G_MODE 2
160 
161 /*
162  * TX Queue Flag Definitions
163  */
164 
165 /* tx wep key definition */
166 #define DCT_WEP_KEY_NOT_IMMIDIATE 0x00
167 #define DCT_WEP_KEY_64Bit 0x40
168 #define DCT_WEP_KEY_128Bit 0x80
169 #define DCT_WEP_KEY_128bitIV 0xC0
170 #define DCT_WEP_KEY_SIZE_MASK 0xC0
171 
172 #define DCT_WEP_KEY_INDEX_MASK 0x0F
173 #define DCT_WEP_INDEX_USE_IMMEDIATE 0x20
174 
175 /* abort attempt if mgmt frame is rx'd */
176 #define DCT_FLAG_ABORT_MGMT 0x01
177 
178 /* require CTS */
179 #define DCT_FLAG_CTS_REQUIRED 0x02
180 
181 /* use short preamble */
182 #define DCT_FLAG_LONG_PREAMBLE 0x00
183 #define DCT_FLAG_SHORT_PREAMBLE 0x04
184 
185 /* RTS/CTS first */
186 #define DCT_FLAG_RTS_REQD 0x08
187 
188 /* dont calculate duration field */
189 #define DCT_FLAG_DUR_SET 0x10
190 
191 /* even if MAC WEP set (allows pre-encrypt) */
192 #define DCT_FLAG_NO_WEP 0x20
193 
194 /* overwrite TSF field */
195 #define DCT_FLAG_TSF_REQD 0x40
196 
197 /* ACK rx is expected to follow */
198 #define DCT_FLAG_ACK_REQD 0x80
199 
200 /* TX flags extension */
201 #define DCT_FLAG_EXT_MODE_CCK 0x01
202 #define DCT_FLAG_EXT_MODE_OFDM 0x00
203 
204 #define DCT_FLAG_EXT_SECURITY_WEP 0x00
205 #define DCT_FLAG_EXT_SECURITY_NO DCT_FLAG_EXT_SECURITY_WEP
206 #define DCT_FLAG_EXT_SECURITY_CKIP 0x04
207 #define DCT_FLAG_EXT_SECURITY_CCM 0x08
208 #define DCT_FLAG_EXT_SECURITY_TKIP 0x0C
209 #define DCT_FLAG_EXT_SECURITY_MASK 0x0C
210 
211 #define DCT_FLAG_EXT_QOS_ENABLED 0x10
212 
213 #define DCT_FLAG_EXT_HC_NO_SIFS_PIFS 0x00
214 #define DCT_FLAG_EXT_HC_SIFS 0x20
215 #define DCT_FLAG_EXT_HC_PIFS 0x40
216 
217 #define TX_RX_TYPE_MASK 0xFF
218 #define TX_FRAME_TYPE 0x00
219 #define TX_HOST_COMMAND_TYPE 0x01
220 #define RX_FRAME_TYPE 0x09
221 #define RX_HOST_NOTIFICATION_TYPE 0x03
222 #define RX_HOST_CMD_RESPONSE_TYPE 0x04
223 #define RX_TX_FRAME_RESPONSE_TYPE 0x05
224 #define TFD_NEED_IRQ_MASK 0x04
225 
226 #define HOST_CMD_DINO_CONFIG 30
227 
228 #define HOST_NOTIFICATION_STATUS_ASSOCIATED 10
229 #define HOST_NOTIFICATION_STATUS_AUTHENTICATE 11
230 #define HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT 12
231 #define HOST_NOTIFICATION_STATUS_SCAN_COMPLETED 13
232 #define HOST_NOTIFICATION_STATUS_FRAG_LENGTH 14
233 #define HOST_NOTIFICATION_STATUS_LINK_DETERIORATION 15
234 #define HOST_NOTIFICATION_DINO_CONFIG_RESPONSE 16
235 #define HOST_NOTIFICATION_STATUS_BEACON_STATE 17
236 #define HOST_NOTIFICATION_STATUS_TGI_TX_KEY 18
237 #define HOST_NOTIFICATION_TX_STATUS 19
238 #define HOST_NOTIFICATION_CALIB_KEEP_RESULTS 20
239 #define HOST_NOTIFICATION_MEASUREMENT_STARTED 21
240 #define HOST_NOTIFICATION_MEASUREMENT_ENDED 22
241 #define HOST_NOTIFICATION_CHANNEL_SWITCHED 23
242 #define HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD 24
243 #define HOST_NOTIFICATION_NOISE_STATS 25
244 #define HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED 30
245 #define HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED 31
246 
247 #define HOST_NOTIFICATION_STATUS_BEACON_MISSING 1
248 #define IPW_MB_SCAN_CANCEL_THRESHOLD 3
249 #define IPW_MB_ROAMING_THRESHOLD_MIN 1
250 #define IPW_MB_ROAMING_THRESHOLD_DEFAULT 8
251 #define IPW_MB_ROAMING_THRESHOLD_MAX 30
252 #define IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT 3*IPW_MB_ROAMING_THRESHOLD_DEFAULT
253 #define IPW_REAL_RATE_RX_PACKET_THRESHOLD 300
254 
255 #define MACADRR_BYTE_LEN 6
256 
257 #define DCR_TYPE_AP 0x01
258 #define DCR_TYPE_WLAP 0x02
259 #define DCR_TYPE_MU_ESS 0x03
260 #define DCR_TYPE_MU_IBSS 0x04
261 #define DCR_TYPE_MU_PIBSS 0x05
262 #define DCR_TYPE_SNIFFER 0x06
263 #define DCR_TYPE_MU_BSS DCR_TYPE_MU_ESS
264 
265 /* QoS definitions */
266 
267 #define CW_MIN_OFDM 15
268 #define CW_MAX_OFDM 1023
269 #define CW_MIN_CCK 31
270 #define CW_MAX_CCK 1023
271 
272 #define QOS_TX0_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
273 #define QOS_TX1_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
274 #define QOS_TX2_CW_MIN_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/2 - 1)
275 #define QOS_TX3_CW_MIN_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/4 - 1)
276 
277 #define QOS_TX0_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
278 #define QOS_TX1_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
279 #define QOS_TX2_CW_MIN_CCK cpu_to_le16((CW_MIN_CCK + 1)/2 - 1)
280 #define QOS_TX3_CW_MIN_CCK cpu_to_le16((CW_MIN_CCK + 1)/4 - 1)
281 
282 #define QOS_TX0_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
283 #define QOS_TX1_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
284 #define QOS_TX2_CW_MAX_OFDM cpu_to_le16(CW_MIN_OFDM)
285 #define QOS_TX3_CW_MAX_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/2 - 1)
286 
287 #define QOS_TX0_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
288 #define QOS_TX1_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
289 #define QOS_TX2_CW_MAX_CCK cpu_to_le16(CW_MIN_CCK)
290 #define QOS_TX3_CW_MAX_CCK cpu_to_le16((CW_MIN_CCK + 1)/2 - 1)
291 
292 #define QOS_TX0_AIFS (3 - QOS_AIFSN_MIN_VALUE)
293 #define QOS_TX1_AIFS (7 - QOS_AIFSN_MIN_VALUE)
294 #define QOS_TX2_AIFS (2 - QOS_AIFSN_MIN_VALUE)
295 #define QOS_TX3_AIFS (2 - QOS_AIFSN_MIN_VALUE)
296 
297 #define QOS_TX0_ACM 0
298 #define QOS_TX1_ACM 0
299 #define QOS_TX2_ACM 0
300 #define QOS_TX3_ACM 0
301 
302 #define QOS_TX0_TXOP_LIMIT_CCK 0
303 #define QOS_TX1_TXOP_LIMIT_CCK 0
304 #define QOS_TX2_TXOP_LIMIT_CCK cpu_to_le16(6016)
305 #define QOS_TX3_TXOP_LIMIT_CCK cpu_to_le16(3264)
306 
307 #define QOS_TX0_TXOP_LIMIT_OFDM 0
308 #define QOS_TX1_TXOP_LIMIT_OFDM 0
309 #define QOS_TX2_TXOP_LIMIT_OFDM cpu_to_le16(3008)
310 #define QOS_TX3_TXOP_LIMIT_OFDM cpu_to_le16(1504)
311 
312 #define DEF_TX0_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
313 #define DEF_TX1_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
314 #define DEF_TX2_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
315 #define DEF_TX3_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
316 
317 #define DEF_TX0_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
318 #define DEF_TX1_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
319 #define DEF_TX2_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
320 #define DEF_TX3_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
321 
322 #define DEF_TX0_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
323 #define DEF_TX1_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
324 #define DEF_TX2_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
325 #define DEF_TX3_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
326 
327 #define DEF_TX0_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
328 #define DEF_TX1_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
329 #define DEF_TX2_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
330 #define DEF_TX3_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
331 
332 #define DEF_TX0_AIFS 0
333 #define DEF_TX1_AIFS 0
334 #define DEF_TX2_AIFS 0
335 #define DEF_TX3_AIFS 0
336 
337 #define DEF_TX0_ACM 0
338 #define DEF_TX1_ACM 0
339 #define DEF_TX2_ACM 0
340 #define DEF_TX3_ACM 0
341 
342 #define DEF_TX0_TXOP_LIMIT_CCK 0
343 #define DEF_TX1_TXOP_LIMIT_CCK 0
344 #define DEF_TX2_TXOP_LIMIT_CCK 0
345 #define DEF_TX3_TXOP_LIMIT_CCK 0
346 
347 #define DEF_TX0_TXOP_LIMIT_OFDM 0
348 #define DEF_TX1_TXOP_LIMIT_OFDM 0
349 #define DEF_TX2_TXOP_LIMIT_OFDM 0
350 #define DEF_TX3_TXOP_LIMIT_OFDM 0
351 
352 #define QOS_QOS_SETS 3
353 #define QOS_PARAM_SET_ACTIVE 0
354 #define QOS_PARAM_SET_DEF_CCK 1
355 #define QOS_PARAM_SET_DEF_OFDM 2
356 
357 #define CTRL_QOS_NO_ACK (0x0020)
358 
359 #define IPW_TX_QUEUE_1 1
360 #define IPW_TX_QUEUE_2 2
361 #define IPW_TX_QUEUE_3 3
362 #define IPW_TX_QUEUE_4 4
363 
364 /* QoS sturctures */
365 struct ipw_qos_info {
373 };
374 
375 /**************************************************************/
381 struct clx2_queue {
382  int n_bd;
384  int last_used;
388  int low_mark;
389  int high_mark;
390 } __packed; /* XXX */
391 
392 struct machdr32 {
394  __le16 duration; // watch out for endians!
398  __le16 seq_ctrl; // more endians!
401 } __packed;
402 
403 struct machdr30 {
405  __le16 duration; // watch out for endians!
409  __le16 seq_ctrl; // more endians!
411 } __packed;
412 
413 struct machdr26 {
415  __le16 duration; // watch out for endians!
419  __le16 seq_ctrl; // more endians!
421 } __packed;
422 
423 struct machdr24 {
425  __le16 duration; // watch out for endians!
429  __le16 seq_ctrl; // more endians!
430 } __packed;
431 
432 // TX TFD with 32 byte MAC Header
433 struct tx_tfd_32 {
434  struct machdr32 mchdr; // 32
436 } __packed;
437 
438 // TX TFD with 30 byte MAC Header
439 struct tx_tfd_30 {
440  struct machdr30 mchdr; // 30
441  u8 reserved[2]; // 2
443 } __packed;
444 
445 // tx tfd with 26 byte mac header
446 struct tx_tfd_26 {
447  struct machdr26 mchdr; // 26
448  u8 reserved1[2]; // 2
450  u8 reserved2[4]; // 4
451 } __packed;
452 
453 // tx tfd with 24 byte mac header
454 struct tx_tfd_24 {
455  struct machdr24 mchdr; // 24
457  u8 reserved[8]; // 8
458 } __packed;
459 
460 #define DCT_WEP_KEY_FIELD_LENGTH 16
461 
462 struct tfd_command {
467 } __packed;
468 
469 struct tfd_data {
470  /* Header */
472  u8 station_number; /* 0 for BSS */
475 
476  /* Tx Parameters */
493 
494  /* 802.11 MAC Header */
495  union {
500  } tfd;
501 
502  /* Payload DMA info */
506 } __packed;
507 
513 } __packed;
514 
515 #define TFD_SIZE 128
516 #define TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH (TFD_SIZE - sizeof(struct txrx_control_flags))
517 
518 struct tfd_frame {
520  union {
521  struct tfd_data data;
522  struct tfd_command cmd;
524  } u;
525 } __packed;
526 
527 typedef void destructor_func(const void *);
528 
534  struct clx2_queue q;
535  struct tfd_frame *bd;
536  struct libipw_txb **txb;
537 };
538 
539 /*
540  * RX related structures and functions
541  */
542 #define RX_FREE_BUFFERS 32
543 #define RX_LOW_WATERMARK 8
544 
545 #define SUP_RATE_11A_MAX_NUM_CHANNELS 8
546 #define SUP_RATE_11B_MAX_NUM_CHANNELS 4
547 #define SUP_RATE_11G_MAX_NUM_CHANNELS 12
548 
549 // Used for passing to driver number of successes and failures per rate
551  union {
555  } success;
556  union {
560  } failed;
561 } __packed;
562 
563 /* statistics command response */
588 } __packed;
589 
594 } __packed;
595 
596 #define SCAN_COMPLETED_STATUS_COMPLETE 1
597 #define SCAN_COMPLETED_STATUS_ABORTED 2
598 
604 } __packed;
605 
609 } __packed;
610 
614 } __packed;
615 
621 } __packed;
622 
623 #define SILENCE_OVER_THRESH (1)
624 #define SILENCE_UNDER_THRESH (2)
625 
631  u8 silence_notification_type; /* SILENCE_OVER/UNDER_THRESH */
633 } __packed;
634 
637 } __packed;
638 
641  struct machdr24 addr;
643 } __packed;
644 
646  u8 data[104];
647 } __packed;
648 
649 struct notif_noise {
651 } __packed;
652 
658  union {
669  u8 raw[0];
670  } u;
671 } __packed;
672 
673 struct ipw_rx_frame {
675  u8 parent_tsf[4]; // fw_use[0] is boolean for OUR_TSF_IS_GREATER
676  u8 received_channel; // The channel that this frame was received on.
677  // Note that for .11b this does not have to be
678  // the same as the channel that it was sent.
679  // Filled by LMAC
688  u8 control; // control bit should be on in bg
689  u8 rtscts_rate; // rate of rts or cts (in rts cts sequence rate
690  // is identical)
691  u8 rtscts_seen; // 0x1 RTS seen ; 0x2 CTS seen
693  u8 data[0];
694 } __packed;
695 
701 } __packed;
702 
705  union {
708  } u;
709 } __packed;
710 
711 #define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12
712 #define IPW_RX_FRAME_SIZE (unsigned int)(sizeof(struct ipw_rx_header) + \
713  sizeof(struct ipw_rx_frame))
714 
717  struct sk_buff *skb;
718  struct list_head list;
719 }; /* Not transferred over network, so not __packed */
720 
721 struct ipw_rx_queue {
724  u32 processed; /* Internal index to last handled Rx packet */
725  u32 read; /* Shared index to newest available Rx buffer */
726  u32 write; /* Shared index to oldest written Rx packet */
727  u32 free_count; /* Number of pre-allocated buffers in rx_free */
728  /* Each of these lists is used as a FIFO for ipw_rx_mem_buffers */
729  struct list_head rx_free; /* Own an SKBs */
730  struct list_head rx_used; /* No SKB allocated */
732 }; /* Not transferred over network, so not __packed */
733 
745  u8 time_stamp[5]; /* month, day, year, hours, minutes */
747 } __packed;
748 
749 #define IPW_MAX_RATES 12
750 
751 struct ipw_rates {
754 } __packed;
755 
757  unsigned int control;
760  unsigned int status;
761 } __packed;
762 
763 #define CB_NUMBER_OF_ELEMENTS_SMALL 64
765  unsigned long last_cb_index;
766  unsigned long current_cb_index;
768  void *v_addr;
769  unsigned long p_addr;
770  unsigned long len;
771 };
772 
794 } __packed;
795 
799  u8 mac1[6];
800  u8 mac2[6];
801  u8 mac3[6];
802  u8 mac4[6];
803 } __packed;
804 
805 #define DCW_WEP_KEY_INDEX_MASK 0x03 /* bits [0:1] */
806 #define DCW_WEP_KEY_SEC_TYPE_MASK 0x30 /* bits [4:5] */
807 
808 #define DCW_WEP_KEY_SEC_TYPE_WEP 0x00
809 #define DCW_WEP_KEY_SEC_TYPE_CCM 0x20
810 #define DCW_WEP_KEY_SEC_TYPE_TKIP 0x30
811 
812 #define DCW_WEP_KEY_INVALID_SIZE 0x00 /* 0 = Invalid key */
813 #define DCW_WEP_KEY64Bit_SIZE 0x05 /* 64-bit encryption */
814 #define DCW_WEP_KEY128Bit_SIZE 0x0D /* 128-bit encryption */
815 #define DCW_CCM_KEY128Bit_SIZE 0x10 /* 128-bit key */
816 //#define DCW_WEP_KEY128BitIV_SIZE 0x10 /* 128-bit key and 128-bit IV */
817 
818 struct ipw_wep_key {
823  u8 key[16];
824 } __packed;
825 
831  u8 key[16];
833 } __packed;
834 
835 #define IPW_SCAN_CHANNELS 54
836 
842 } __packed;
843 
844 enum {
851 };
852 
859 } __packed;
860 
861 static inline u8 ipw_get_scan_type(struct ipw_scan_request_ext *scan, u8 index)
862 {
863  if (index % 2)
864  return scan->scan_type[index / 2] & 0x0F;
865  else
866  return (scan->scan_type[index / 2] & 0xF0) >> 4;
867 }
868 
869 static inline void ipw_set_scan_type(struct ipw_scan_request_ext *scan,
870  u8 index, u8 scan_type)
871 {
872  if (index % 2)
873  scan->scan_type[index / 2] =
874  (scan->scan_type[index / 2] & 0xF0) | (scan_type & 0x0F);
875  else
876  scan->scan_type[index / 2] =
877  (scan->scan_type[index / 2] & 0x0F) |
878  ((scan_type & 0x0F) << 4);
879 }
880 
883 #ifdef __LITTLE_ENDIAN_BITFIELD
884  u8 auth_type:4, auth_key:4;
885 #else
887 #endif
904 } __packed;
905 
912 } __packed;
913 
917 } __packed;
918 
922 } __packed;
923 
928 } __packed;
929 
935 } __packed;
936 
941 } __packed;
942 
943 struct ipw_rx_key {
948  u8 key[16];
952 } __packed;
953 
958 } __packed;
959 
965 } __packed;
966 
970 } __packed;
971 
972 #define SCAN_ASSOCIATED_INTERVAL (HZ)
973 #define SCAN_INTERVAL (HZ / 10)
974 #define MAX_A_CHANNELS 37
975 #define MAX_B_CHANNELS 14
976 
977 struct ipw_tx_power {
981 } __packed;
982 
987 } __packed;
988 
992 } __packed;
993 
1007 struct ipw_cmd { /* XXX */
1010  u32 status_len;
1021 } __packed;
1022 
1023 #define STATUS_HCMD_ACTIVE (1<<0)
1025 #define STATUS_INT_ENABLED (1<<1)
1026 #define STATUS_RF_KILL_HW (1<<2)
1027 #define STATUS_RF_KILL_SW (1<<3)
1028 #define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)
1029 
1030 #define STATUS_INIT (1<<5)
1031 #define STATUS_AUTH (1<<6)
1032 #define STATUS_ASSOCIATED (1<<7)
1033 #define STATUS_STATE_MASK (STATUS_INIT | STATUS_AUTH | STATUS_ASSOCIATED)
1034 
1035 #define STATUS_ASSOCIATING (1<<8)
1036 #define STATUS_DISASSOCIATING (1<<9)
1037 #define STATUS_ROAMING (1<<10)
1038 #define STATUS_EXIT_PENDING (1<<11)
1039 #define STATUS_DISASSOC_PENDING (1<<12)
1040 #define STATUS_STATE_PENDING (1<<13)
1041 
1042 #define STATUS_DIRECT_SCAN_PENDING (1<<19)
1043 #define STATUS_SCAN_PENDING (1<<20)
1044 #define STATUS_SCANNING (1<<21)
1045 #define STATUS_SCAN_ABORTING (1<<22)
1046 #define STATUS_SCAN_FORCED (1<<23)
1047 
1048 #define STATUS_LED_LINK_ON (1<<24)
1049 #define STATUS_LED_ACT_ON (1<<25)
1050 
1051 #define STATUS_INDIRECT_BYTE (1<<28) /* sysfs entry configured for access */
1052 #define STATUS_INDIRECT_DWORD (1<<29) /* sysfs entry configured for access */
1053 #define STATUS_DIRECT_DWORD (1<<30) /* sysfs entry configured for access */
1054 
1055 #define STATUS_SECURITY_UPDATED (1<<31) /* Security sync needed */
1056 
1057 #define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */
1058 #define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */
1059 #define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */
1060 #define CFG_CUSTOM_MAC (1<<3)
1061 #define CFG_PREAMBLE_LONG (1<<4)
1062 #define CFG_ADHOC_PERSIST (1<<5)
1063 #define CFG_ASSOCIATE (1<<6)
1064 #define CFG_FIXED_RATE (1<<7)
1065 #define CFG_ADHOC_CREATE (1<<8)
1066 #define CFG_NO_LED (1<<9)
1067 #define CFG_BACKGROUND_SCAN (1<<10)
1068 #define CFG_SPEED_SCAN (1<<11)
1069 #define CFG_NET_STATS (1<<12)
1070 
1071 #define CAP_SHARED_KEY (1<<0) /* Off = OPEN */
1072 #define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */
1073 
1074 #define MAX_STATIONS 32
1075 #define IPW_INVALID_STATION (0xff)
1076 
1081 };
1082 
1083 #define AVG_ENTRIES 8
1084 struct average {
1089 };
1090 
1091 #define MAX_SPEED_SCAN 100
1092 #define IPW_IBSS_MAC_HASH_SIZE 31
1093 
1098  unsigned long packet_time;
1099  struct list_head list;
1100 };
1101 
1102 struct ipw_error_elem { /* XXX */
1110 };
1111 
1112 struct ipw_event { /* XXX */
1116 } __packed;
1117 
1118 struct ipw_fw_error { /* XXX */
1119  unsigned long jiffies;
1125  struct ipw_event *log;
1127 } __packed;
1128 
1129 #ifdef CONFIG_IPW2200_PROMISCUOUS
1130 
1131 enum ipw_prom_filter {
1132  IPW_PROM_CTL_HEADER_ONLY = (1 << 0),
1133  IPW_PROM_MGMT_HEADER_ONLY = (1 << 1),
1134  IPW_PROM_DATA_HEADER_ONLY = (1 << 2),
1135  IPW_PROM_ALL_HEADER_ONLY = 0xf, /* bits 0..3 */
1136  IPW_PROM_NO_TX = (1 << 4),
1137  IPW_PROM_NO_RX = (1 << 5),
1138  IPW_PROM_NO_CTL = (1 << 6),
1139  IPW_PROM_NO_MGMT = (1 << 7),
1140  IPW_PROM_NO_DATA = (1 << 8),
1141 };
1142 
1143 struct ipw_priv;
1144 struct ipw_prom_priv {
1145  struct ipw_priv *priv;
1146  struct libipw_device *ieee;
1147  enum ipw_prom_filter filter;
1148  int tx_packets;
1149  int rx_packets;
1150 };
1151 #endif
1152 
1153 #if defined(CONFIG_IPW2200_RADIOTAP) || defined(CONFIG_IPW2200_PROMISCUOUS)
1154 /* Magic struct that slots into the radiotap header -- no reason
1155  * to build this manually element by element, we can write it much
1156  * more efficiently than we can parse it. ORDER MATTERS HERE
1157  *
1158  * When sent to us via the simulated Rx interface in sysfs, the entire
1159  * structure is provided regardless of any bits unset.
1160  */
1161 struct ipw_rt_hdr {
1162  struct ieee80211_radiotap_header rt_hdr;
1163  u64 rt_tsf; /* TSF */ /* XXX */
1164  u8 rt_flags; /* radiotap packet flags */
1165  u8 rt_rate; /* rate in 500kb/s */
1166  __le16 rt_channel; /* channel in mhz */
1167  __le16 rt_chbitmask; /* channel bitfield */
1168  s8 rt_dbmsignal; /* signal in dbM, kluged to signed */
1169  s8 rt_dbmnoise;
1170  u8 rt_antenna; /* antenna number */
1171  u8 payload[0]; /* payload... */
1172 } __packed;
1173 #endif
1174 
1175 struct ipw_priv {
1176  /* ieee device used by generic ieee processing code */
1178 
1181  struct mutex mutex;
1182 
1183  /* basic pci-network driver stuff */
1184  struct pci_dev *pci_dev;
1186 
1187 #ifdef CONFIG_IPW2200_PROMISCUOUS
1188  /* Promiscuous mode */
1189  struct ipw_prom_priv *prom_priv;
1190  struct net_device *prom_net_dev;
1191 #endif
1192 
1193  /* pci hardware address support */
1195  unsigned long hw_len;
1196 
1198 
1199  /* result of ucode download */
1201 
1204 
1205  /* Rx and Tx DMA processing queues */
1208  struct clx2_tx_queue txq[4];
1212 
1222 
1225 
1226  unsigned long ts_scan_abort;
1228  struct ipw_rates phy[3];
1229  struct ipw_rates supp;
1233  struct ipw_cmd *hcmd;
1240  /* ordinal interface with firmware */
1247 
1248  /* context information */
1263 
1265 
1266  /* Statistics and counters normalized with each association */
1273 
1279 
1282 
1285  unsigned long last_packet_time;
1287 
1288  /* eeprom */
1289  u8 eeprom[0x100]; /* 256 bytes of eeprom */
1292 
1294 
1296 
1300 
1312  struct work_struct up;
1320 
1322 
1323  /* LED related variables and work_struct */
1331 
1336 
1340 
1341 #define IPW_2200BG 1
1342 #define IPW_2915ABG 2
1344 
1346 
1347  /* Track time in suspend */
1348  unsigned long suspend_at;
1349  unsigned long suspend_time;
1350 
1351 #ifdef CONFIG_PM
1352  u32 pm_state[16];
1353 #endif
1354 
1356 
1357  /* network state */
1358 
1359  /* Used to pass the current INTA value from ISR to Tasklet */
1361 
1362  /* QoS */
1365  /*********************************/
1366 
1367  /* debugging info */
1371 }; /*ipw_priv */
1372 
1373 /* debug macros */
1374 
1375 /* Debug and printf string expansion helpers for printing bitfields */
1376 #define BIT_FMT8 "%c%c%c%c-%c%c%c%c"
1377 #define BIT_FMT16 BIT_FMT8 ":" BIT_FMT8
1378 #define BIT_FMT32 BIT_FMT16 " " BIT_FMT16
1379 
1380 #define BITC(x,y) (((x>>y)&1)?'1':'0')
1381 #define BIT_ARG8(x) \
1382 BITC(x,7),BITC(x,6),BITC(x,5),BITC(x,4),\
1383 BITC(x,3),BITC(x,2),BITC(x,1),BITC(x,0)
1384 
1385 #define BIT_ARG16(x) \
1386 BITC(x,15),BITC(x,14),BITC(x,13),BITC(x,12),\
1387 BITC(x,11),BITC(x,10),BITC(x,9),BITC(x,8),\
1388 BIT_ARG8(x)
1389 
1390 #define BIT_ARG32(x) \
1391 BITC(x,31),BITC(x,30),BITC(x,29),BITC(x,28),\
1392 BITC(x,27),BITC(x,26),BITC(x,25),BITC(x,24),\
1393 BITC(x,23),BITC(x,22),BITC(x,21),BITC(x,20),\
1394 BITC(x,19),BITC(x,18),BITC(x,17),BITC(x,16),\
1395 BIT_ARG16(x)
1396 
1397 
1398 #define IPW_DEBUG(level, fmt, args...) \
1399 do { if (ipw_debug_level & (level)) \
1400  printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \
1401  in_interrupt() ? 'I' : 'U', __func__ , ## args); } while (0)
1402 
1403 #ifdef CONFIG_IPW2200_DEBUG
1404 #define IPW_LL_DEBUG(level, fmt, args...) \
1405 do { if (ipw_debug_level & (level)) \
1406  printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \
1407  in_interrupt() ? 'I' : 'U', __func__ , ## args); } while (0)
1408 #else
1409 #define IPW_LL_DEBUG(level, fmt, args...) do {} while (0)
1410 #endif /* CONFIG_IPW2200_DEBUG */
1411 
1412 /*
1413  * To use the debug system;
1414  *
1415  * If you are defining a new debug classification, simply add it to the #define
1416  * list here in the form of:
1417  *
1418  * #define IPW_DL_xxxx VALUE
1419  *
1420  * shifting value to the left one bit from the previous entry. xxxx should be
1421  * the name of the classification (for example, WEP)
1422  *
1423  * You then need to either add a IPW_xxxx_DEBUG() macro definition for your
1424  * classification, or use IPW_DEBUG(IPW_DL_xxxx, ...) whenever you want
1425  * to send output to that classification.
1426  *
1427  * To add your debug level to the list of levels seen when you perform
1428  *
1429  * % cat /proc/net/ipw/debug_level
1430  *
1431  * you simply need to add your entry to the ipw_debug_levels array.
1432  *
1433  * If you do not see debug_level in /proc/net/ipw then you do not have
1434  * CONFIG_IPW2200_DEBUG defined in your kernel configuration
1435  *
1436  */
1437 
1438 #define IPW_DL_ERROR (1<<0)
1439 #define IPW_DL_WARNING (1<<1)
1440 #define IPW_DL_INFO (1<<2)
1441 #define IPW_DL_WX (1<<3)
1442 #define IPW_DL_HOST_COMMAND (1<<5)
1443 #define IPW_DL_STATE (1<<6)
1444 
1445 #define IPW_DL_NOTIF (1<<10)
1446 #define IPW_DL_SCAN (1<<11)
1447 #define IPW_DL_ASSOC (1<<12)
1448 #define IPW_DL_DROP (1<<13)
1449 #define IPW_DL_IOCTL (1<<14)
1450 
1451 #define IPW_DL_MANAGE (1<<15)
1452 #define IPW_DL_FW (1<<16)
1453 #define IPW_DL_RF_KILL (1<<17)
1454 #define IPW_DL_FW_ERRORS (1<<18)
1455 
1456 #define IPW_DL_LED (1<<19)
1457 
1458 #define IPW_DL_ORD (1<<20)
1459 
1460 #define IPW_DL_FRAG (1<<21)
1461 #define IPW_DL_WEP (1<<22)
1462 #define IPW_DL_TX (1<<23)
1463 #define IPW_DL_RX (1<<24)
1464 #define IPW_DL_ISR (1<<25)
1465 #define IPW_DL_FW_INFO (1<<26)
1466 #define IPW_DL_IO (1<<27)
1467 #define IPW_DL_TRACE (1<<28)
1468 
1469 #define IPW_DL_STATS (1<<29)
1470 #define IPW_DL_MERGE (1<<30)
1471 #define IPW_DL_QOS (1<<31)
1472 
1473 #define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
1474 #define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
1475 #define IPW_DEBUG_INFO(f, a...) IPW_DEBUG(IPW_DL_INFO, f, ## a)
1476 
1477 #define IPW_DEBUG_WX(f, a...) IPW_DEBUG(IPW_DL_WX, f, ## a)
1478 #define IPW_DEBUG_SCAN(f, a...) IPW_DEBUG(IPW_DL_SCAN, f, ## a)
1479 #define IPW_DEBUG_TRACE(f, a...) IPW_LL_DEBUG(IPW_DL_TRACE, f, ## a)
1480 #define IPW_DEBUG_RX(f, a...) IPW_LL_DEBUG(IPW_DL_RX, f, ## a)
1481 #define IPW_DEBUG_TX(f, a...) IPW_LL_DEBUG(IPW_DL_TX, f, ## a)
1482 #define IPW_DEBUG_ISR(f, a...) IPW_LL_DEBUG(IPW_DL_ISR, f, ## a)
1483 #define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a)
1484 #define IPW_DEBUG_LED(f, a...) IPW_LL_DEBUG(IPW_DL_LED, f, ## a)
1485 #define IPW_DEBUG_WEP(f, a...) IPW_LL_DEBUG(IPW_DL_WEP, f, ## a)
1486 #define IPW_DEBUG_HC(f, a...) IPW_LL_DEBUG(IPW_DL_HOST_COMMAND, f, ## a)
1487 #define IPW_DEBUG_FRAG(f, a...) IPW_LL_DEBUG(IPW_DL_FRAG, f, ## a)
1488 #define IPW_DEBUG_FW(f, a...) IPW_LL_DEBUG(IPW_DL_FW, f, ## a)
1489 #define IPW_DEBUG_RF_KILL(f, a...) IPW_DEBUG(IPW_DL_RF_KILL, f, ## a)
1490 #define IPW_DEBUG_DROP(f, a...) IPW_DEBUG(IPW_DL_DROP, f, ## a)
1491 #define IPW_DEBUG_IO(f, a...) IPW_LL_DEBUG(IPW_DL_IO, f, ## a)
1492 #define IPW_DEBUG_ORD(f, a...) IPW_LL_DEBUG(IPW_DL_ORD, f, ## a)
1493 #define IPW_DEBUG_FW_INFO(f, a...) IPW_LL_DEBUG(IPW_DL_FW_INFO, f, ## a)
1494 #define IPW_DEBUG_NOTIF(f, a...) IPW_DEBUG(IPW_DL_NOTIF, f, ## a)
1495 #define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1496 #define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1497 #define IPW_DEBUG_STATS(f, a...) IPW_LL_DEBUG(IPW_DL_STATS, f, ## a)
1498 #define IPW_DEBUG_MERGE(f, a...) IPW_LL_DEBUG(IPW_DL_MERGE, f, ## a)
1499 #define IPW_DEBUG_QOS(f, a...) IPW_LL_DEBUG(IPW_DL_QOS, f, ## a)
1500 
1501 #include <linux/ctype.h>
1502 
1503 /*
1504 * Register bit definitions
1505 */
1506 
1507 #define IPW_INTA_RW 0x00000008
1508 #define IPW_INTA_MASK_R 0x0000000C
1509 #define IPW_INDIRECT_ADDR 0x00000010
1510 #define IPW_INDIRECT_DATA 0x00000014
1511 #define IPW_AUTOINC_ADDR 0x00000018
1512 #define IPW_AUTOINC_DATA 0x0000001C
1513 #define IPW_RESET_REG 0x00000020
1514 #define IPW_GP_CNTRL_RW 0x00000024
1515 
1516 #define IPW_READ_INT_REGISTER 0xFF4
1517 
1518 #define IPW_GP_CNTRL_BIT_INIT_DONE 0x00000004
1519 
1520 #define IPW_REGISTER_DOMAIN1_END 0x00001000
1521 #define IPW_SRAM_READ_INT_REGISTER 0x00000ff4
1522 
1523 #define IPW_SHARED_LOWER_BOUND 0x00000200
1524 #define IPW_INTERRUPT_AREA_LOWER_BOUND 0x00000f80
1525 
1526 #define IPW_NIC_SRAM_LOWER_BOUND 0x00000000
1527 #define IPW_NIC_SRAM_UPPER_BOUND 0x00030000
1528 
1529 #define IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29)
1530 #define IPW_GP_CNTRL_BIT_CLOCK_READY 0x00000001
1531 #define IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002
1532 
1533 /*
1534  * RESET Register Bit Indexes
1535  */
1536 #define CBD_RESET_REG_PRINCETON_RESET (1<<0)
1537 #define IPW_START_STANDBY (1<<2)
1538 #define IPW_ACTIVITY_LED (1<<4)
1539 #define IPW_ASSOCIATED_LED (1<<5)
1540 #define IPW_OFDM_LED (1<<6)
1541 #define IPW_RESET_REG_SW_RESET (1<<7)
1542 #define IPW_RESET_REG_MASTER_DISABLED (1<<8)
1543 #define IPW_RESET_REG_STOP_MASTER (1<<9)
1544 #define IPW_GATE_ODMA (1<<25)
1545 #define IPW_GATE_IDMA (1<<26)
1546 #define IPW_ARC_KESHET_CONFIG (1<<27)
1547 #define IPW_GATE_ADMA (1<<29)
1548 
1549 #define IPW_CSR_CIS_UPPER_BOUND 0x00000200
1550 #define IPW_DOMAIN_0_END 0x1000
1551 #define CLX_MEM_BAR_SIZE 0x1000
1552 
1553 /* Dino/baseband control registers bits */
1554 
1555 #define DINO_ENABLE_SYSTEM 0x80 /* 1 = baseband processor on, 0 = reset */
1556 #define DINO_ENABLE_CS 0x40 /* 1 = enable ucode load */
1557 #define DINO_RXFIFO_DATA 0x01 /* 1 = data available */
1558 #define IPW_BASEBAND_CONTROL_STATUS 0X00200000
1559 #define IPW_BASEBAND_TX_FIFO_WRITE 0X00200004
1560 #define IPW_BASEBAND_RX_FIFO_READ 0X00200004
1561 #define IPW_BASEBAND_CONTROL_STORE 0X00200010
1562 
1563 #define IPW_INTERNAL_CMD_EVENT 0X00300004
1564 #define IPW_BASEBAND_POWER_DOWN 0x00000001
1565 
1566 #define IPW_MEM_HALT_AND_RESET 0x003000e0
1567 
1568 /* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */
1569 #define IPW_BIT_HALT_RESET_ON 0x80000000
1570 #define IPW_BIT_HALT_RESET_OFF 0x00000000
1571 
1572 #define CB_LAST_VALID 0x20000000
1573 #define CB_INT_ENABLED 0x40000000
1574 #define CB_VALID 0x80000000
1575 #define CB_SRC_LE 0x08000000
1576 #define CB_DEST_LE 0x04000000
1577 #define CB_SRC_AUTOINC 0x00800000
1578 #define CB_SRC_IO_GATED 0x00400000
1579 #define CB_DEST_AUTOINC 0x00080000
1580 #define CB_SRC_SIZE_LONG 0x00200000
1581 #define CB_DEST_SIZE_LONG 0x00020000
1582 
1583 /* DMA DEFINES */
1584 
1585 #define DMA_CONTROL_SMALL_CB_CONST_VALUE 0x00540000
1586 #define DMA_CB_STOP_AND_ABORT 0x00000C00
1587 #define DMA_CB_START 0x00000100
1588 
1589 #define IPW_SHARED_SRAM_SIZE 0x00030000
1590 #define IPW_SHARED_SRAM_DMA_CONTROL 0x00027000
1591 #define CB_MAX_LENGTH 0x1FFF
1592 
1593 #define IPW_HOST_EEPROM_DATA_SRAM_SIZE 0xA18
1594 #define IPW_EEPROM_IMAGE_SIZE 0x100
1595 
1596 /* DMA defs */
1597 #define IPW_DMA_I_CURRENT_CB 0x003000D0
1598 #define IPW_DMA_O_CURRENT_CB 0x003000D4
1599 #define IPW_DMA_I_DMA_CONTROL 0x003000A4
1600 #define IPW_DMA_I_CB_BASE 0x003000A0
1601 
1602 #define IPW_TX_CMD_QUEUE_BD_BASE 0x00000200
1603 #define IPW_TX_CMD_QUEUE_BD_SIZE 0x00000204
1604 #define IPW_TX_QUEUE_0_BD_BASE 0x00000208
1605 #define IPW_TX_QUEUE_0_BD_SIZE (0x0000020C)
1606 #define IPW_TX_QUEUE_1_BD_BASE 0x00000210
1607 #define IPW_TX_QUEUE_1_BD_SIZE 0x00000214
1608 #define IPW_TX_QUEUE_2_BD_BASE 0x00000218
1609 #define IPW_TX_QUEUE_2_BD_SIZE (0x0000021C)
1610 #define IPW_TX_QUEUE_3_BD_BASE 0x00000220
1611 #define IPW_TX_QUEUE_3_BD_SIZE 0x00000224
1612 #define IPW_RX_BD_BASE 0x00000240
1613 #define IPW_RX_BD_SIZE 0x00000244
1614 #define IPW_RFDS_TABLE_LOWER 0x00000500
1615 
1616 #define IPW_TX_CMD_QUEUE_READ_INDEX 0x00000280
1617 #define IPW_TX_QUEUE_0_READ_INDEX 0x00000284
1618 #define IPW_TX_QUEUE_1_READ_INDEX 0x00000288
1619 #define IPW_TX_QUEUE_2_READ_INDEX (0x0000028C)
1620 #define IPW_TX_QUEUE_3_READ_INDEX 0x00000290
1621 #define IPW_RX_READ_INDEX (0x000002A0)
1622 
1623 #define IPW_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80)
1624 #define IPW_TX_QUEUE_0_WRITE_INDEX (0x00000F84)
1625 #define IPW_TX_QUEUE_1_WRITE_INDEX (0x00000F88)
1626 #define IPW_TX_QUEUE_2_WRITE_INDEX (0x00000F8C)
1627 #define IPW_TX_QUEUE_3_WRITE_INDEX (0x00000F90)
1628 #define IPW_RX_WRITE_INDEX (0x00000FA0)
1629 
1630 /*
1631  * EEPROM Related Definitions
1632  */
1633 
1634 #define IPW_EEPROM_DATA_SRAM_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x814)
1635 #define IPW_EEPROM_DATA_SRAM_SIZE (IPW_SHARED_LOWER_BOUND + 0x818)
1636 #define IPW_EEPROM_LOAD_DISABLE (IPW_SHARED_LOWER_BOUND + 0x81C)
1637 #define IPW_EEPROM_DATA (IPW_SHARED_LOWER_BOUND + 0x820)
1638 #define IPW_EEPROM_UPPER_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x9E0)
1639 
1640 #define IPW_STATION_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0xA0C)
1641 #define IPW_STATION_TABLE_UPPER (IPW_SHARED_LOWER_BOUND + 0xB0C)
1642 #define IPW_REQUEST_ATIM (IPW_SHARED_LOWER_BOUND + 0xB0C)
1643 #define IPW_ATIM_SENT (IPW_SHARED_LOWER_BOUND + 0xB10)
1644 #define IPW_WHO_IS_AWAKE (IPW_SHARED_LOWER_BOUND + 0xB14)
1645 #define IPW_DURING_ATIM_WINDOW (IPW_SHARED_LOWER_BOUND + 0xB18)
1646 
1647 #define MSB 1
1648 #define LSB 0
1649 #define WORD_TO_BYTE(_word) ((_word) * sizeof(u16))
1650 
1651 #define GET_EEPROM_ADDR(_wordoffset,_byteoffset) \
1652  ( WORD_TO_BYTE(_wordoffset) + (_byteoffset) )
1653 
1654 /* EEPROM access by BYTE */
1655 #define EEPROM_PME_CAPABILITY (GET_EEPROM_ADDR(0x09,MSB)) /* 1 byte */
1656 #define EEPROM_MAC_ADDRESS (GET_EEPROM_ADDR(0x21,LSB)) /* 6 byte */
1657 #define EEPROM_VERSION (GET_EEPROM_ADDR(0x24,MSB)) /* 1 byte */
1658 #define EEPROM_NIC_TYPE (GET_EEPROM_ADDR(0x25,LSB)) /* 1 byte */
1659 #define EEPROM_SKU_CAPABILITY (GET_EEPROM_ADDR(0x25,MSB)) /* 1 byte */
1660 #define EEPROM_COUNTRY_CODE (GET_EEPROM_ADDR(0x26,LSB)) /* 3 bytes */
1661 #define EEPROM_IBSS_CHANNELS_BG (GET_EEPROM_ADDR(0x28,LSB)) /* 2 bytes */
1662 #define EEPROM_IBSS_CHANNELS_A (GET_EEPROM_ADDR(0x29,MSB)) /* 5 bytes */
1663 #define EEPROM_BSS_CHANNELS_BG (GET_EEPROM_ADDR(0x2c,LSB)) /* 2 bytes */
1664 #define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */
1665 
1666 /* NIC type as found in the one byte EEPROM_NIC_TYPE offset */
1667 #define EEPROM_NIC_TYPE_0 0
1668 #define EEPROM_NIC_TYPE_1 1
1669 #define EEPROM_NIC_TYPE_2 2
1670 #define EEPROM_NIC_TYPE_3 3
1671 #define EEPROM_NIC_TYPE_4 4
1672 
1673 /* Bluetooth Coexistence capabilities as found in EEPROM_SKU_CAPABILITY */
1674 #define EEPROM_SKU_CAP_BT_CHANNEL_SIG 0x01 /* we can tell BT our channel # */
1675 #define EEPROM_SKU_CAP_BT_PRIORITY 0x02 /* BT can take priority over us */
1676 #define EEPROM_SKU_CAP_BT_OOB 0x04 /* we can signal BT out-of-band */
1677 
1678 #define FW_MEM_REG_LOWER_BOUND 0x00300000
1679 #define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40)
1680 #define IPW_EVENT_REG (FW_MEM_REG_LOWER_BOUND + 0x04)
1681 #define EEPROM_BIT_SK (1<<0)
1682 #define EEPROM_BIT_CS (1<<1)
1683 #define EEPROM_BIT_DI (1<<2)
1684 #define EEPROM_BIT_DO (1<<4)
1685 
1686 #define EEPROM_CMD_READ 0x2
1687 
1688 /* Interrupts masks */
1689 #define IPW_INTA_NONE 0x00000000
1690 
1691 #define IPW_INTA_BIT_RX_TRANSFER 0x00000002
1692 #define IPW_INTA_BIT_STATUS_CHANGE 0x00000010
1693 #define IPW_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020
1694 
1695 //Inta Bits for CF
1696 #define IPW_INTA_BIT_TX_CMD_QUEUE 0x00000800
1697 #define IPW_INTA_BIT_TX_QUEUE_1 0x00001000
1698 #define IPW_INTA_BIT_TX_QUEUE_2 0x00002000
1699 #define IPW_INTA_BIT_TX_QUEUE_3 0x00004000
1700 #define IPW_INTA_BIT_TX_QUEUE_4 0x00008000
1701 
1702 #define IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000
1703 
1704 #define IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000
1705 #define IPW_INTA_BIT_POWER_DOWN 0x00200000
1706 
1707 #define IPW_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000
1708 #define IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000
1709 #define IPW_INTA_BIT_RF_KILL_DONE 0x04000000
1710 #define IPW_INTA_BIT_FATAL_ERROR 0x40000000
1711 #define IPW_INTA_BIT_PARITY_ERROR 0x80000000
1712 
1713 /* Interrupts enabled at init time. */
1714 #define IPW_INTA_MASK_ALL \
1715  (IPW_INTA_BIT_TX_QUEUE_1 | \
1716  IPW_INTA_BIT_TX_QUEUE_2 | \
1717  IPW_INTA_BIT_TX_QUEUE_3 | \
1718  IPW_INTA_BIT_TX_QUEUE_4 | \
1719  IPW_INTA_BIT_TX_CMD_QUEUE | \
1720  IPW_INTA_BIT_RX_TRANSFER | \
1721  IPW_INTA_BIT_FATAL_ERROR | \
1722  IPW_INTA_BIT_PARITY_ERROR | \
1723  IPW_INTA_BIT_STATUS_CHANGE | \
1724  IPW_INTA_BIT_FW_INITIALIZATION_DONE | \
1725  IPW_INTA_BIT_BEACON_PERIOD_EXPIRED | \
1726  IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \
1727  IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN | \
1728  IPW_INTA_BIT_POWER_DOWN | \
1729  IPW_INTA_BIT_RF_KILL_DONE )
1730 
1731 /* FW event log definitions */
1732 #define EVENT_ELEM_SIZE (3 * sizeof(u32))
1733 #define EVENT_START_OFFSET (1 * sizeof(u32) + 2 * sizeof(u16))
1734 
1735 /* FW error log definitions */
1736 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1737 #define ERROR_START_OFFSET (1 * sizeof(u32))
1738 
1739 /* TX power level (dbm) */
1740 #define IPW_TX_POWER_MIN -12
1741 #define IPW_TX_POWER_MAX 20
1742 #define IPW_TX_POWER_DEFAULT IPW_TX_POWER_MAX
1743 
1744 enum {
1760 };
1761 
1762 #define AUTH_OPEN 0
1763 #define AUTH_SHARED_KEY 1
1764 #define AUTH_LEAP 2
1765 #define AUTH_IGNORE 3
1766 
1767 #define HC_ASSOCIATE 0
1768 #define HC_REASSOCIATE 1
1769 #define HC_DISASSOCIATE 2
1770 #define HC_IBSS_START 3
1771 #define HC_IBSS_RECONF 4
1772 #define HC_DISASSOC_QUIET 5
1773 
1774 #define HC_QOS_SUPPORT_ASSOC cpu_to_le16(0x01)
1775 
1776 #define IPW_RATE_CAPABILITIES 1
1777 #define IPW_RATE_CONNECT 0
1778 
1779 /*
1780  * Rate values and masks
1781  */
1782 #define IPW_TX_RATE_1MB 0x0A
1783 #define IPW_TX_RATE_2MB 0x14
1784 #define IPW_TX_RATE_5MB 0x37
1785 #define IPW_TX_RATE_6MB 0x0D
1786 #define IPW_TX_RATE_9MB 0x0F
1787 #define IPW_TX_RATE_11MB 0x6E
1788 #define IPW_TX_RATE_12MB 0x05
1789 #define IPW_TX_RATE_18MB 0x07
1790 #define IPW_TX_RATE_24MB 0x09
1791 #define IPW_TX_RATE_36MB 0x0B
1792 #define IPW_TX_RATE_48MB 0x01
1793 #define IPW_TX_RATE_54MB 0x03
1794 
1795 #define IPW_ORD_TABLE_ID_MASK 0x0000FF00
1796 #define IPW_ORD_TABLE_VALUE_MASK 0x000000FF
1797 
1798 #define IPW_ORD_TABLE_0_MASK 0x0000F000
1799 #define IPW_ORD_TABLE_1_MASK 0x0000F100
1800 #define IPW_ORD_TABLE_2_MASK 0x0000F200
1801 #define IPW_ORD_TABLE_3_MASK 0x0000F300
1802 #define IPW_ORD_TABLE_4_MASK 0x0000F400
1803 #define IPW_ORD_TABLE_5_MASK 0x0000F500
1804 #define IPW_ORD_TABLE_6_MASK 0x0000F600
1805 #define IPW_ORD_TABLE_7_MASK 0x0000F700
1806 
1807 /*
1808  * Table 0 Entries (all entries are 32 bits)
1809  */
1810 enum {
1821  /* Hole */
1822 
1840  /* Hole */
1841 
1867 };
1868 
1869 #define IPW_RSSI_TO_DBM 112
1870 
1871 /* Table 1 Entries
1872  */
1873 enum {
1875 };
1876 
1877 /*
1878  * Table 2 Entries
1879  *
1880  * FW_VERSION: 16 byte string
1881  * FW_DATE: 16 byte string (only 14 bytes used)
1882  * UCODE_VERSION: 4 byte version code
1883  * UCODE_DATE: 5 bytes code code
1884  * ADDAPTER_MAC: 6 byte MAC address
1885  * RTC: 4 byte clock
1886  */
1887 enum {
1895 };
1896 
1897 /* Table 3 */
1898 enum {
1904 };
1905 
1906 /* Table 4 */
1907 enum {
1909 };
1910 
1911 /* Table 5 */
1912 enum {
1927 };
1928 
1929 /* Table 6 */
1930 enum {
1935 };
1936 
1937 /* Table 7 */
1938 enum {
1944 };
1945 
1946 #define IPW_ERROR_LOG (IPW_SHARED_LOWER_BOUND + 0x410)
1947 #define IPW_EVENT_LOG (IPW_SHARED_LOWER_BOUND + 0x414)
1948 #define IPW_ORDINALS_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0x500)
1949 #define IPW_ORDINALS_TABLE_0 (IPW_SHARED_LOWER_BOUND + 0x180)
1950 #define IPW_ORDINALS_TABLE_1 (IPW_SHARED_LOWER_BOUND + 0x184)
1951 #define IPW_ORDINALS_TABLE_2 (IPW_SHARED_LOWER_BOUND + 0x188)
1952 #define IPW_MEM_FIXED_OVERRIDE (IPW_SHARED_LOWER_BOUND + 0x41C)
1953 
1957 } __packed;
1958 
1959 #define IPW_INDIRECT_ADDR_MASK (~0x3ul)
1960 
1961 struct host_cmd {
1966 } __packed; /* XXX */
1967 
1972  char param[124];
1973 } __packed;
1974 
1975 struct ipw_cmd_log {
1976  unsigned long jiffies;
1977  int retcode;
1979 };
1980 
1981 /* SysConfig command parameters ... */
1982 /* bt_coexistence param */
1983 #define CFG_BT_COEXISTENCE_SIGNAL_CHNL 0x01 /* tell BT our chnl # */
1984 #define CFG_BT_COEXISTENCE_DEFER 0x02 /* defer our Tx if BT traffic */
1985 #define CFG_BT_COEXISTENCE_KILL 0x04 /* kill our Tx if BT traffic */
1986 #define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08 /* multimedia extensions */
1987 #define CFG_BT_COEXISTENCE_OOB 0x10 /* signal BT via out-of-band */
1988 
1989 /* clear-to-send to self param */
1990 #define CFG_CTS_TO_ITSELF_ENABLED_MIN 0x00
1991 #define CFG_CTS_TO_ITSELF_ENABLED_MAX 0x01
1992 #define CFG_CTS_TO_ITSELF_ENABLED_DEF CFG_CTS_TO_ITSELF_ENABLED_MIN
1993 
1994 /* Antenna diversity param (h/w can select best antenna, based on signal) */
1995 #define CFG_SYS_ANTENNA_BOTH 0x00 /* NIC selects best antenna */
1996 #define CFG_SYS_ANTENNA_A 0x01 /* force antenna A */
1997 #define CFG_SYS_ANTENNA_B 0x03 /* force antenna B */
1998 #define CFG_SYS_ANTENNA_SLOW_DIV 0x02 /* consider background noise */
1999 
2000 #define IPW_MAX_CONFIG_RETRIES 10
2001 
2002 #endif /* __ipw2200_h__ */