Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
irq-r7785rp.c
Go to the documentation of this file.
1 /*
2  * Renesas Solutions Highlander R7785RP Support.
3  *
4  * Copyright (C) 2002 Atom Create Engineering Co., Ltd.
5  * Copyright (C) 2006 - 2008 Paul Mundt
6  * Copyright (C) 2007 Magnus Damm
7  *
8  * This file is subject to the terms and conditions of the GNU General Public
9  * License. See the file "COPYING" in the main directory of this archive
10  * for more details.
11  */
12 #include <linux/init.h>
13 #include <linux/irq.h>
14 #include <linux/io.h>
15 #include <mach/highlander.h>
16 
17 enum {
18  UNUSED = 0,
19 
20  /* FPGA specific interrupt sources */
21  CF, /* Compact Flash */
22  SMBUS, /* SMBUS */
23  TP, /* Touch panel */
24  RTC, /* RTC Alarm */
25  TH_ALERT, /* Temperature sensor */
26  AX88796, /* Ethernet controller */
27 
28  /* external bus connector */
30 };
31 
32 static struct intc_vect vectors[] __initdata = {
33  INTC_IRQ(CF, IRQ_CF),
35  INTC_IRQ(TP, IRQ_TP),
38 
41 
44 
46 };
47 
48 static struct intc_mask_reg mask_registers[] __initdata = {
49  { 0xa4000010, 0, 16, /* IRLMCR1 */
50  { 0, 0, 0, 0, CF, AX88796, SMBUS, TP,
51  RTC, 0, TH_ALERT, 0, 0, 0, 0, 0 } },
52  { 0xa4000012, 0, 16, /* IRLMCR2 */
53  { 0, 0, 0, 0, 0, 0, 0, 0,
54  EXT7, EXT6, EXT5, EXT4, EXT3, EXT2, EXT1, EXT0 } },
55 };
56 
57 static unsigned char irl2irq[HL_NR_IRL] __initdata = {
62 };
63 
64 static DECLARE_INTC_DESC(intc_desc, "r7785rp", vectors,
65  NULL, mask_registers, NULL, NULL);
66 
67 unsigned char * __init highlander_plat_irq_setup(void)
68 {
69  if ((__raw_readw(0xa4000158) & 0xf000) != 0x1000)
70  return NULL;
71 
72  printk(KERN_INFO "Using r7785rp interrupt controller.\n");
73 
74  __raw_writew(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */
75 
76  /* Setup the FPGA IRL */
77  __raw_writew(0x0000, PA_IRLPRA); /* FPGA IRLA */
78  __raw_writew(0xe598, PA_IRLPRB); /* FPGA IRLB */
79  __raw_writew(0x7060, PA_IRLPRC); /* FPGA IRLC */
80  __raw_writew(0x0000, PA_IRLPRD); /* FPGA IRLD */
81  __raw_writew(0x4321, PA_IRLPRE); /* FPGA IRLE */
82  __raw_writew(0xdcba, PA_IRLPRF); /* FPGA IRLF */
83 
85  return irl2irq;
86 }