ixgbe_dcb_82598.h File Reference

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Macros
#define	IXGBE_DPMCS_MTSOS_SHIFT   16
#define	IXGBE_DPMCS_TDPAC   0x00000001 /* 0 Round Robin, 1 DFP - Deficit Fixed Priority */
#define	IXGBE_DPMCS_TRM   0x00000010 /* Transmit Recycle Mode */
#define	IXGBE_DPMCS_ARBDIS   0x00000040 /* DCB arbiter disable */
#define	IXGBE_DPMCS_TSOEF   0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */
#define	IXGBE_RUPPBMR_MQA   0x80000000 /* Enable UP to queue mapping */
#define	IXGBE_RT2CR_MCL_SHIFT   12 /* Offset to Max Credit Limit setting */
#define	IXGBE_RT2CR_LSP   0x80000000 /* LSP enable bit */
#define	IXGBE_RDRXCTL_MPBEN   0x00000010 /* DMA config for multiple packet buffers enable */
#define	IXGBE_RDRXCTL_MCEN   0x00000040 /* DMA config for multiple cores (RSS) enable */
#define	IXGBE_TDTQ2TCCR_MCL_SHIFT   12
#define	IXGBE_TDTQ2TCCR_BWG_SHIFT   9
#define	IXGBE_TDTQ2TCCR_GSP   0x40000000
#define	IXGBE_TDTQ2TCCR_LSP   0x80000000
#define	IXGBE_TDPT2TCCR_MCL_SHIFT   12
#define	IXGBE_TDPT2TCCR_BWG_SHIFT   9
#define	IXGBE_TDPT2TCCR_GSP   0x40000000
#define	IXGBE_TDPT2TCCR_LSP   0x80000000
#define	IXGBE_PDPMCS_TPPAC   0x00000020 /* 0 Round Robin, 1 for DFP - Deficit Fixed Priority */
#define	IXGBE_PDPMCS_ARBDIS   0x00000040 /* Arbiter disable */
#define	IXGBE_PDPMCS_TRM   0x00000100 /* Transmit Recycle Mode enable */
#define	IXGBE_DTXCTL_ENDBUBD   0x00000004 /* Enable DBU buffer division */
#define	IXGBE_TXPBSIZE_40KB   0x0000A000 /* 40KB Packet Buffer */
#define	IXGBE_RXPBSIZE_48KB   0x0000C000 /* 48KB Packet Buffer */
#define	IXGBE_RXPBSIZE_64KB   0x00010000 /* 64KB Packet Buffer */
#define	IXGBE_RXPBSIZE_80KB   0x00014000 /* 80KB Packet Buffer */
#define	IXGBE_RDRXCTL_RDMTS_1_2   0x00000000

Functions
s32	ixgbe_dcb_config_pfc_82598 (struct ixgbe_hw *, u8 pfc_en)
s32	ixgbe_dcb_config_rx_arbiter_82598 (struct ixgbe_hw *hw, u16 *refill, u16 *max, u8 *prio_type)
s32	ixgbe_dcb_config_tx_desc_arbiter_82598 (struct ixgbe_hw *hw, u16 *refill, u16 *max, u8 *bwg_id, u8 *prio_type)
s32	ixgbe_dcb_config_tx_data_arbiter_82598 (struct ixgbe_hw *hw, u16 *refill, u16 *max, u8 *bwg_id, u8 *prio_type)
s32	ixgbe_dcb_hw_config_82598 (struct ixgbe_hw *hw, u8 pfc_en, u16 *refill, u16 *max, u8 *bwg_id, u8 *prio_type)

Macro Definition Documentation

#define IXGBE_DPMCS_ARBDIS   0x00000040 /* DCB arbiter disable */

Definition at line 37 of file ixgbe_dcb_82598.h.

#define IXGBE_DPMCS_MTSOS_SHIFT   16

Definition at line 34 of file ixgbe_dcb_82598.h.

#define IXGBE_DPMCS_TDPAC   0x00000001 /* 0 Round Robin, 1 DFP - Deficit Fixed Priority */

Definition at line 35 of file ixgbe_dcb_82598.h.

#define IXGBE_DPMCS_TRM   0x00000010 /* Transmit Recycle Mode */

Definition at line 36 of file ixgbe_dcb_82598.h.

#define IXGBE_DPMCS_TSOEF   0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */

Definition at line 38 of file ixgbe_dcb_82598.h.

#define IXGBE_DTXCTL_ENDBUBD   0x00000004 /* Enable DBU buffer division */

Definition at line 62 of file ixgbe_dcb_82598.h.

#define IXGBE_PDPMCS_ARBDIS   0x00000040 /* Arbiter disable */

Definition at line 59 of file ixgbe_dcb_82598.h.

#define IXGBE_PDPMCS_TPPAC   0x00000020 /* 0 Round Robin, 1 for DFP - Deficit Fixed Priority */

Definition at line 58 of file ixgbe_dcb_82598.h.

#define IXGBE_PDPMCS_TRM   0x00000100 /* Transmit Recycle Mode enable */

Definition at line 60 of file ixgbe_dcb_82598.h.

#define IXGBE_RDRXCTL_MCEN   0x00000040 /* DMA config for multiple cores (RSS) enable */

Definition at line 46 of file ixgbe_dcb_82598.h.

#define IXGBE_RDRXCTL_MPBEN   0x00000010 /* DMA config for multiple packet buffers enable */

Definition at line 45 of file ixgbe_dcb_82598.h.

#define IXGBE_RDRXCTL_RDMTS_1_2   0x00000000

Definition at line 69 of file ixgbe_dcb_82598.h.

#define IXGBE_RT2CR_LSP   0x80000000 /* LSP enable bit */

Definition at line 43 of file ixgbe_dcb_82598.h.

#define IXGBE_RT2CR_MCL_SHIFT   12 /* Offset to Max Credit Limit setting */

Definition at line 42 of file ixgbe_dcb_82598.h.

#define IXGBE_RUPPBMR_MQA   0x80000000 /* Enable UP to queue mapping */

Definition at line 40 of file ixgbe_dcb_82598.h.

#define IXGBE_RXPBSIZE_48KB   0x0000C000 /* 48KB Packet Buffer */

Definition at line 65 of file ixgbe_dcb_82598.h.

#define IXGBE_RXPBSIZE_64KB   0x00010000 /* 64KB Packet Buffer */

Definition at line 66 of file ixgbe_dcb_82598.h.

#define IXGBE_RXPBSIZE_80KB   0x00014000 /* 80KB Packet Buffer */

Definition at line 67 of file ixgbe_dcb_82598.h.

#define IXGBE_TDPT2TCCR_BWG_SHIFT   9

Definition at line 54 of file ixgbe_dcb_82598.h.

#define IXGBE_TDPT2TCCR_GSP   0x40000000

Definition at line 55 of file ixgbe_dcb_82598.h.

#define IXGBE_TDPT2TCCR_LSP   0x80000000

Definition at line 56 of file ixgbe_dcb_82598.h.

#define IXGBE_TDPT2TCCR_MCL_SHIFT   12

Definition at line 53 of file ixgbe_dcb_82598.h.

#define IXGBE_TDTQ2TCCR_BWG_SHIFT   9

Definition at line 49 of file ixgbe_dcb_82598.h.

#define IXGBE_TDTQ2TCCR_GSP   0x40000000

Definition at line 50 of file ixgbe_dcb_82598.h.

#define IXGBE_TDTQ2TCCR_LSP   0x80000000

Definition at line 51 of file ixgbe_dcb_82598.h.

#define IXGBE_TDTQ2TCCR_MCL_SHIFT   12

Definition at line 48 of file ixgbe_dcb_82598.h.

#define IXGBE_TXPBSIZE_40KB   0x0000A000 /* 40KB Packet Buffer */

Definition at line 64 of file ixgbe_dcb_82598.h.

Function Documentation

s32 ixgbe_dcb_config_pfc_82598	(	struct ixgbe_hw *	hw,
		u8	pfc_en
	)

ixgbe_dcb_config_pfc_82598 - Config priority flow control : pointer to hardware structure : pointer to ixgbe_dcb_config structure

Configure Priority Flow Control for each traffic class.

Definition at line 192 of file ixgbe_dcb_82598.c.

s32 ixgbe_dcb_config_rx_arbiter_82598	(	struct ixgbe_hw *	hw,
		u16 *	refill,
		u16 *	max,
		u8 *	prio_type
	)

ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter : pointer to hardware structure : pointer to ixgbe_dcb_config structure

Configure Rx Data Arbiter and credits for each traffic class.

Definition at line 41 of file ixgbe_dcb_82598.c.

s32 ixgbe_dcb_config_tx_data_arbiter_82598	(	struct ixgbe_hw *	hw,
		u16 *	refill,
		u16 *	max,
		u8 *	bwg_id,
		u8 *	prio_type
	)

ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter : pointer to hardware structure : pointer to ixgbe_dcb_config structure

Configure Tx Data Arbiter and credits for each traffic class.

Definition at line 145 of file ixgbe_dcb_82598.c.

s32 ixgbe_dcb_config_tx_desc_arbiter_82598	(	struct ixgbe_hw *	hw,
		u16 *	refill,
		u16 *	max,
		u8 *	bwg_id,
		u8 *	prio_type
	)

ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter : pointer to hardware structure : pointer to ixgbe_dcb_config structure

Configure Tx Descriptor Arbiter and credits for each traffic class.

Definition at line 98 of file ixgbe_dcb_82598.c.

s32 ixgbe_dcb_hw_config_82598	(	struct ixgbe_hw *	hw,
		u8	pfc_en,
		u16 *	refill,
		u16 *	max,
		u8 *	bwg_id,
		u8 *	prio_type
	)

ixgbe_dcb_hw_config_82598 - Config and enable DCB : pointer to hardware structure : pointer to ixgbe_dcb_config structure

Configure dcb settings and enable dcb mode.

Definition at line 277 of file ixgbe_dcb_82598.c.