m32r_mp_fpga.h File Reference

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Macros
#define	M32R_SFR_OFFSET   (0x00E00000) /* 0x03E00000-0x03EFFFFF 1[MB] */
#define	M32R_FPGA_TOP   (0x000F0000+M32R_SFR_OFFSET)
#define	M32R_FPGA_NUM_OF_CPUS_PORTL   (0x00+M32R_FPGA_TOP)
#define	M32R_FPGA_CPU_NAME0_PORTL   (0x10+M32R_FPGA_TOP)
#define	M32R_FPGA_CPU_NAME1_PORTL   (0x14+M32R_FPGA_TOP)
#define	M32R_FPGA_CPU_NAME2_PORTL   (0x18+M32R_FPGA_TOP)
#define	M32R_FPGA_CPU_NAME3_PORTL   (0x1C+M32R_FPGA_TOP)
#define	M32R_FPGA_MODEL_ID0_PORTL   (0x20+M32R_FPGA_TOP)
#define	M32R_FPGA_MODEL_ID1_PORTL   (0x24+M32R_FPGA_TOP)
#define	M32R_FPGA_MODEL_ID2_PORTL   (0x28+M32R_FPGA_TOP)
#define	M32R_FPGA_MODEL_ID3_PORTL   (0x2C+M32R_FPGA_TOP)
#define	M32R_FPGA_VERSION0_PORTL   (0x30+M32R_FPGA_TOP)
#define	M32R_FPGA_VERSION1_PORTL   (0x34+M32R_FPGA_TOP)
#define	M32R_CPM_OFFSET   (0x000F4000+M32R_SFR_OFFSET)
#define	M32R_CPM_CPUCLKCR_PORTL   (0x00+M32R_CPM_OFFSET)
#define	M32R_CPM_CLKMOD_PORTL   (0x04+M32R_CPM_OFFSET)
#define	M32R_CPM_PLLCR_PORTL   (0x08+M32R_CPM_OFFSET)
#define	M32R_BSELC_OFFSET   (0x000F5000+M32R_SFR_OFFSET)
#define	M32R_BSEL0_CR0_PORTL   (0x000+M32R_BSELC_OFFSET)
#define	M32R_BSEL0_CR1_PORTL   (0x004+M32R_BSELC_OFFSET)
#define	M32R_BSEL1_CR0_PORTL   (0x100+M32R_BSELC_OFFSET)
#define	M32R_BSEL1_CR1_PORTL   (0x104+M32R_BSELC_OFFSET)
#define	M32R_BSEL2_CR0_PORTL   (0x200+M32R_BSELC_OFFSET)
#define	M32R_BSEL2_CR1_PORTL   (0x204+M32R_BSELC_OFFSET)
#define	M32R_BSEL3_CR0_PORTL   (0x300+M32R_BSELC_OFFSET)
#define	M32R_BSEL3_CR1_PORTL   (0x304+M32R_BSELC_OFFSET)
#define	M32R_BSEL4_CR0_PORTL   (0x400+M32R_BSELC_OFFSET)
#define	M32R_BSEL4_CR1_PORTL   (0x404+M32R_BSELC_OFFSET)
#define	M32R_BSEL5_CR0_PORTL   (0x500+M32R_BSELC_OFFSET)
#define	M32R_BSEL5_CR1_PORTL   (0x504+M32R_BSELC_OFFSET)
#define	M32R_BSEL6_CR0_PORTL   (0x600+M32R_BSELC_OFFSET)
#define	M32R_BSEL6_CR1_PORTL   (0x604+M32R_BSELC_OFFSET)
#define	M32R_BSEL7_CR0_PORTL   (0x700+M32R_BSELC_OFFSET)
#define	M32R_BSEL7_CR1_PORTL   (0x704+M32R_BSELC_OFFSET)
#define	M32R_MFT_OFFSET   (0x000FC000+M32R_SFR_OFFSET)
#define	M32R_MFTCR_PORTL   (0x000+M32R_MFT_OFFSET) /* MFT control */
#define	M32R_MFTRPR_PORTL   (0x004+M32R_MFT_OFFSET) /* MFT real port */
#define	M32R_MFT0_OFFSET   (0x100+M32R_MFT_OFFSET)
#define	M32R_MFT0MOD_PORTL   (0x00+M32R_MFT0_OFFSET) /* MFT0 mode */
#define	M32R_MFT0BOS_PORTL   (0x04+M32R_MFT0_OFFSET) /* MFT0 b-port output status */
#define	M32R_MFT0CUT_PORTL   (0x08+M32R_MFT0_OFFSET) /* MFT0 count */
#define	M32R_MFT0RLD_PORTL   (0x0C+M32R_MFT0_OFFSET) /* MFT0 reload */
#define	M32R_MFT0CMPRLD_PORTL   (0x10+M32R_MFT0_OFFSET) /* MFT0 compare reload */
#define	M32R_MFT1_OFFSET   (0x200+M32R_MFT_OFFSET)
#define	M32R_MFT1MOD_PORTL   (0x00+M32R_MFT1_OFFSET) /* MFT1 mode */
#define	M32R_MFT1BOS_PORTL   (0x04+M32R_MFT1_OFFSET) /* MFT1 b-port output status */
#define	M32R_MFT1CUT_PORTL   (0x08+M32R_MFT1_OFFSET) /* MFT1 count */
#define	M32R_MFT1RLD_PORTL   (0x0C+M32R_MFT1_OFFSET) /* MFT1 reload */
#define	M32R_MFT1CMPRLD_PORTL   (0x10+M32R_MFT1_OFFSET) /* MFT1 compare reload */
#define	M32R_MFT2_OFFSET   (0x300+M32R_MFT_OFFSET)
#define	M32R_MFT2MOD_PORTL   (0x00+M32R_MFT2_OFFSET) /* MFT2 mode */
#define	M32R_MFT2BOS_PORTL   (0x04+M32R_MFT2_OFFSET) /* MFT2 b-port output status */
#define	M32R_MFT2CUT_PORTL   (0x08+M32R_MFT2_OFFSET) /* MFT2 count */
#define	M32R_MFT2RLD_PORTL   (0x0C+M32R_MFT2_OFFSET) /* MFT2 reload */
#define	M32R_MFT2CMPRLD_PORTL   (0x10+M32R_MFT2_OFFSET) /* MFT2 compare reload */
#define	M32R_MFT3_OFFSET   (0x400+M32R_MFT_OFFSET)
#define	M32R_MFT3MOD_PORTL   (0x00+M32R_MFT3_OFFSET) /* MFT3 mode */
#define	M32R_MFT3BOS_PORTL   (0x04+M32R_MFT3_OFFSET) /* MFT3 b-port output status */
#define	M32R_MFT3CUT_PORTL   (0x08+M32R_MFT3_OFFSET) /* MFT3 count */
#define	M32R_MFT3RLD_PORTL   (0x0C+M32R_MFT3_OFFSET) /* MFT3 reload */
#define	M32R_MFT3CMPRLD_PORTL   (0x10+M32R_MFT3_OFFSET) /* MFT3 compare reload */
#define	M32R_MFT4_OFFSET   (0x500+M32R_MFT_OFFSET)
#define	M32R_MFT4MOD_PORTL   (0x00+M32R_MFT4_OFFSET) /* MFT4 mode */
#define	M32R_MFT4BOS_PORTL   (0x04+M32R_MFT4_OFFSET) /* MFT4 b-port output status */
#define	M32R_MFT4CUT_PORTL   (0x08+M32R_MFT4_OFFSET) /* MFT4 count */
#define	M32R_MFT4RLD_PORTL   (0x0C+M32R_MFT4_OFFSET) /* MFT4 reload */
#define	M32R_MFT4CMPRLD_PORTL   (0x10+M32R_MFT4_OFFSET) /* MFT4 compare reload */
#define	M32R_MFT5_OFFSET   (0x600+M32R_MFT_OFFSET)
#define	M32R_MFT5MOD_PORTL   (0x00+M32R_MFT5_OFFSET) /* MFT4 mode */
#define	M32R_MFT5BOS_PORTL   (0x04+M32R_MFT5_OFFSET) /* MFT4 b-port output status */
#define	M32R_MFT5CUT_PORTL   (0x08+M32R_MFT5_OFFSET) /* MFT4 count */
#define	M32R_MFT5RLD_PORTL   (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */
#define	M32R_MFT5CMPRLD_PORTL   (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */
#define	M32R_MFTCR_MFT0MSK   (1UL<<15) /* b16 */
#define	M32R_MFTCR_MFT1MSK   (1UL<<14) /* b17 */
#define	M32R_MFTCR_MFT2MSK   (1UL<<13) /* b18 */
#define	M32R_MFTCR_MFT3MSK   (1UL<<12) /* b19 */
#define	M32R_MFTCR_MFT4MSK   (1UL<<11) /* b20 */
#define	M32R_MFTCR_MFT5MSK   (1UL<<10) /* b21 */
#define	M32R_MFTCR_MFT0EN   (1UL<<7) /* b24 */
#define	M32R_MFTCR_MFT1EN   (1UL<<6) /* b25 */
#define	M32R_MFTCR_MFT2EN   (1UL<<5) /* b26 */
#define	M32R_MFTCR_MFT3EN   (1UL<<4) /* b27 */
#define	M32R_MFTCR_MFT4EN   (1UL<<3) /* b28 */
#define	M32R_MFTCR_MFT5EN   (1UL<<2) /* b29 */
#define	M32R_MFTMOD_CC_MASK   (1UL<<15) /* b16 */
#define	M32R_MFTMOD_TCCR   (1UL<<13) /* b18 */
#define	M32R_MFTMOD_GTSEL000   (0UL<<8) /* b21-23 : 000 */
#define	M32R_MFTMOD_GTSEL001   (1UL<<8) /* b21-23 : 001 */
#define	M32R_MFTMOD_GTSEL010   (2UL<<8) /* b21-23 : 010 */
#define	M32R_MFTMOD_GTSEL011   (3UL<<8) /* b21-23 : 011 */
#define	M32R_MFTMOD_GTSEL110   (6UL<<8) /* b21-23 : 110 */
#define	M32R_MFTMOD_GTSEL111   (7UL<<8) /* b21-23 : 111 */
#define	M32R_MFTMOD_CMSEL   (1UL<<3) /* b28 */
#define	M32R_MFTMOD_CSSEL000   (0UL<<0) /* b29-b31 : 000 */
#define	M32R_MFTMOD_CSSEL001   (1UL<<0) /* b29-b31 : 001 */
#define	M32R_MFTMOD_CSSEL010   (2UL<<0) /* b29-b31 : 010 */
#define	M32R_MFTMOD_CSSEL011   (3UL<<0) /* b29-b31 : 011 */
#define	M32R_MFTMOD_CSSEL100   (4UL<<0) /* b29-b31 : 100 */
#define	M32R_MFTMOD_CSSEL110   (6UL<<0) /* b29-b31 : 110 */
#define	M32R_SIO_OFFSET   (0x000FD000+M32R_SFR_OFFSET)
#define	M32R_SIO0_CR_PORTL   (0x000+M32R_SIO_OFFSET)
#define	M32R_SIO0_MOD0_PORTL   (0x004+M32R_SIO_OFFSET)
#define	M32R_SIO0_MOD1_PORTL   (0x008+M32R_SIO_OFFSET)
#define	M32R_SIO0_STS_PORTL   (0x00C+M32R_SIO_OFFSET)
#define	M32R_SIO0_TRCR_PORTL   (0x010+M32R_SIO_OFFSET)
#define	M32R_SIO0_BAUR_PORTL   (0x014+M32R_SIO_OFFSET)
#define	M32R_SIO0_RBAUR_PORTL   (0x018+M32R_SIO_OFFSET)
#define	M32R_SIO0_TXB_PORTL   (0x01C+M32R_SIO_OFFSET)
#define	M32R_SIO0_RXB_PORTL   (0x020+M32R_SIO_OFFSET)
#define	M32R_ICU_OFFSET   (0x000FF000+M32R_SFR_OFFSET)
#define	M32R_ICU_ISTS_PORTL   (0x004+M32R_ICU_OFFSET)
#define	M32R_ICU_IREQ0_PORTL   (0x008+M32R_ICU_OFFSET)
#define	M32R_ICU_IREQ1_PORTL   (0x00C+M32R_ICU_OFFSET)
#define	M32R_ICU_SBICR_PORTL   (0x018+M32R_ICU_OFFSET)
#define	M32R_ICU_IMASK_PORTL   (0x01C+M32R_ICU_OFFSET)
#define	M32R_ICU_CR1_PORTL   (0x200+M32R_ICU_OFFSET) /* INT0 */
#define	M32R_ICU_CR2_PORTL   (0x204+M32R_ICU_OFFSET) /* INT1 */
#define	M32R_ICU_CR3_PORTL   (0x208+M32R_ICU_OFFSET) /* INT2 */
#define	M32R_ICU_CR4_PORTL   (0x20C+M32R_ICU_OFFSET) /* INT3 */
#define	M32R_ICU_CR5_PORTL   (0x210+M32R_ICU_OFFSET) /* INT4 */
#define	M32R_ICU_CR6_PORTL   (0x214+M32R_ICU_OFFSET) /* INT5 */
#define	M32R_ICU_CR7_PORTL   (0x218+M32R_ICU_OFFSET) /* INT6 */
#define	M32R_ICU_CR8_PORTL   (0x218+M32R_ICU_OFFSET) /* INT7 */
#define	M32R_ICU_CR32_PORTL   (0x27C+M32R_ICU_OFFSET) /* SIO0 RX */
#define	M32R_ICU_CR33_PORTL   (0x280+M32R_ICU_OFFSET) /* SIO0 TX */
#define	M32R_ICU_CR40_PORTL   (0x29C+M32R_ICU_OFFSET) /* DMAC0 */
#define	M32R_ICU_CR41_PORTL   (0x2A0+M32R_ICU_OFFSET) /* DMAC1 */
#define	M32R_ICU_CR48_PORTL   (0x2BC+M32R_ICU_OFFSET) /* MFT0 */
#define	M32R_ICU_CR49_PORTL   (0x2C0+M32R_ICU_OFFSET) /* MFT1 */
#define	M32R_ICU_CR50_PORTL   (0x2C4+M32R_ICU_OFFSET) /* MFT2 */
#define	M32R_ICU_CR51_PORTL   (0x2C8+M32R_ICU_OFFSET) /* MFT3 */
#define	M32R_ICU_CR52_PORTL   (0x2CC+M32R_ICU_OFFSET) /* MFT4 */
#define	M32R_ICU_CR53_PORTL   (0x2D0+M32R_ICU_OFFSET) /* MFT5 */
#define	M32R_ICU_IPICR0_PORTL   (0x2DC+M32R_ICU_OFFSET) /* IPI0 */
#define	M32R_ICU_IPICR1_PORTL   (0x2E0+M32R_ICU_OFFSET) /* IPI1 */
#define	M32R_ICU_IPICR2_PORTL   (0x2E4+M32R_ICU_OFFSET) /* IPI2 */
#define	M32R_ICU_IPICR3_PORTL   (0x2E8+M32R_ICU_OFFSET) /* IPI3 */
#define	M32R_ICU_IPICR4_PORTL   (0x2EC+M32R_ICU_OFFSET) /* IPI4 */
#define	M32R_ICU_IPICR5_PORTL   (0x2F0+M32R_ICU_OFFSET) /* IPI5 */
#define	M32R_ICU_IPICR6_PORTL   (0x2F4+M32R_ICU_OFFSET) /* IPI6 */
#define	M32R_ICU_IPICR7_PORTL   (0x2FC+M32R_ICU_OFFSET) /* IPI7 */
#define	M32R_ICUISTS_VECB(val)   ((val>>28) & 0xF)
#define	M32R_ICUISTS_ISN(val)   ((val>>22) & 0x3F)
#define	M32R_ICUISTS_PIML(val)   ((val>>16) & 0x7)
#define	M32R_ICUIMASK_IMSK0   (0UL<<16) /* b13-b15: Disable interrupt */
#define	M32R_ICUIMASK_IMSK1   (1UL<<16) /* b13-b15: Enable level 0 interrupt */
#define	M32R_ICUIMASK_IMSK2   (2UL<<16) /* b13-b15: Enable level 0,1 interrupt */
#define	M32R_ICUIMASK_IMSK3   (3UL<<16) /* b13-b15: Enable level 0-2 interrupt */
#define	M32R_ICUIMASK_IMSK4   (4UL<<16) /* b13-b15: Enable level 0-3 interrupt */
#define	M32R_ICUIMASK_IMSK5   (5UL<<16) /* b13-b15: Enable level 0-4 interrupt */
#define	M32R_ICUIMASK_IMSK6   (6UL<<16) /* b13-b15: Enable level 0-5 interrupt */
#define	M32R_ICUIMASK_IMSK7   (7UL<<16) /* b13-b15: Enable level 0-6 interrupt */
#define	M32R_ICUCR_IEN   (1UL<<12) /* b19: Interrupt enable */
#define	M32R_ICUCR_IRQ   (1UL<<8) /* b23: Interrupt request */
#define	M32R_ICUCR_ISMOD00   (0UL<<4) /* b26-b27: Interrupt sense mode Edge HtoL */
#define	M32R_ICUCR_ISMOD01   (1UL<<4) /* b26-b27: Interrupt sense mode Level L */
#define	M32R_ICUCR_ISMOD10   (2UL<<4) /* b26-b27: Interrupt sense mode Edge LtoH*/
#define	M32R_ICUCR_ISMOD11   (3UL<<4) /* b26-b27: Interrupt sense mode Level H */
#define	M32R_ICUCR_ILEVEL0   (0UL<<0) /* b29-b31: Interrupt priority level 0 */
#define	M32R_ICUCR_ILEVEL1   (1UL<<0) /* b29-b31: Interrupt priority level 1 */
#define	M32R_ICUCR_ILEVEL2   (2UL<<0) /* b29-b31: Interrupt priority level 2 */
#define	M32R_ICUCR_ILEVEL3   (3UL<<0) /* b29-b31: Interrupt priority level 3 */
#define	M32R_ICUCR_ILEVEL4   (4UL<<0) /* b29-b31: Interrupt priority level 4 */
#define	M32R_ICUCR_ILEVEL5   (5UL<<0) /* b29-b31: Interrupt priority level 5 */
#define	M32R_ICUCR_ILEVEL6   (6UL<<0) /* b29-b31: Interrupt priority level 6 */
#define	M32R_ICUCR_ILEVEL7   (7UL<<0) /* b29-b31: Disable interrupt */
#define	M32R_ICUCR_ILEVEL_MASK   (7UL)
#define	M32R_IRQ_INT0   (1) /* INT0 */
#define	M32R_IRQ_INT1   (2) /* INT1 */
#define	M32R_IRQ_INT2   (3) /* INT2 */
#define	M32R_IRQ_INT3   (4) /* INT3 */
#define	M32R_IRQ_INT4   (5) /* INT4 */
#define	M32R_IRQ_INT5   (6) /* INT5 */
#define	M32R_IRQ_INT6   (7) /* INT6 */
#define	M32R_IRQ_INT7   (8) /* INT7 */
#define	M32R_IRQ_MFT0   (16) /* MFT0 */
#define	M32R_IRQ_MFT1   (17) /* MFT1 */
#define	M32R_IRQ_MFT2   (18) /* MFT2 */
#define	M32R_IRQ_MFT3   (19) /* MFT3 */
#define	M32R_IRQ_MFT4   (20) /* MFT4 */
#define	M32R_IRQ_MFT5   (21) /* MFT5 */
#define	M32R_IRQ_DMAC0   (32) /* DMAC0 */
#define	M32R_IRQ_DMAC1   (33) /* DMAC1 */
#define	M32R_IRQ_SIO0_R   (48) /* SIO0 receive */
#define	M32R_IRQ_SIO0_S   (49) /* SIO0 send */
#define	M32R_IRQ_SIO1_R   (50) /* SIO1 send */
#define	M32R_IRQ_SIO1_S   (51) /* SIO1 receive */
#define	M32R_IRQ_IPI0   (56) /* IPI0 */
#define	M32R_IRQ_IPI1   (57) /* IPI1 */
#define	M32R_IRQ_IPI2   (58) /* IPI2 */
#define	M32R_IRQ_IPI3   (59) /* IPI3 */
#define	M32R_IRQ_IPI4   (60) /* IPI4 */
#define	M32R_IRQ_IPI5   (61) /* IPI5 */
#define	M32R_IRQ_IPI6   (62) /* IPI6 */
#define	M32R_IRQ_IPI7   (63) /* IPI7 */
#define	M32R_CPUID_PORTL   (0xFFFFFFE0)
#define	M32R_MCICAR_PORTL   (0xFFFFFFF0)
#define	M32R_MCDCAR_PORTL   (0xFFFFFFF4)
#define	M32R_MCCR_PORTL   (0xFFFFFFFC)

Macro Definition Documentation

#define M32R_BSEL0_CR0_PORTL   (0x000+M32R_BSELC_OFFSET)

Definition at line 98 of file m32r_mp_fpga.h.

#define M32R_BSEL0_CR1_PORTL   (0x004+M32R_BSELC_OFFSET)

Definition at line 99 of file m32r_mp_fpga.h.

#define M32R_BSEL1_CR0_PORTL   (0x100+M32R_BSELC_OFFSET)

Definition at line 100 of file m32r_mp_fpga.h.

#define M32R_BSEL1_CR1_PORTL   (0x104+M32R_BSELC_OFFSET)

Definition at line 101 of file m32r_mp_fpga.h.

#define M32R_BSEL2_CR0_PORTL   (0x200+M32R_BSELC_OFFSET)

Definition at line 102 of file m32r_mp_fpga.h.

#define M32R_BSEL2_CR1_PORTL   (0x204+M32R_BSELC_OFFSET)

Definition at line 103 of file m32r_mp_fpga.h.

#define M32R_BSEL3_CR0_PORTL   (0x300+M32R_BSELC_OFFSET)

Definition at line 104 of file m32r_mp_fpga.h.

#define M32R_BSEL3_CR1_PORTL   (0x304+M32R_BSELC_OFFSET)

Definition at line 105 of file m32r_mp_fpga.h.

#define M32R_BSEL4_CR0_PORTL   (0x400+M32R_BSELC_OFFSET)

Definition at line 106 of file m32r_mp_fpga.h.

#define M32R_BSEL4_CR1_PORTL   (0x404+M32R_BSELC_OFFSET)

Definition at line 107 of file m32r_mp_fpga.h.

#define M32R_BSEL5_CR0_PORTL   (0x500+M32R_BSELC_OFFSET)

Definition at line 108 of file m32r_mp_fpga.h.

#define M32R_BSEL5_CR1_PORTL   (0x504+M32R_BSELC_OFFSET)

Definition at line 109 of file m32r_mp_fpga.h.

#define M32R_BSEL6_CR0_PORTL   (0x600+M32R_BSELC_OFFSET)

Definition at line 110 of file m32r_mp_fpga.h.

#define M32R_BSEL6_CR1_PORTL   (0x604+M32R_BSELC_OFFSET)

Definition at line 111 of file m32r_mp_fpga.h.

#define M32R_BSEL7_CR0_PORTL   (0x700+M32R_BSELC_OFFSET)

Definition at line 112 of file m32r_mp_fpga.h.

#define M32R_BSEL7_CR1_PORTL   (0x704+M32R_BSELC_OFFSET)

Definition at line 113 of file m32r_mp_fpga.h.

#define M32R_BSELC_OFFSET   (0x000F5000+M32R_SFR_OFFSET)

Definition at line 96 of file m32r_mp_fpga.h.

#define M32R_CPM_CLKMOD_PORTL   (0x04+M32R_CPM_OFFSET)

Definition at line 90 of file m32r_mp_fpga.h.

#define M32R_CPM_CPUCLKCR_PORTL   (0x00+M32R_CPM_OFFSET)

Definition at line 89 of file m32r_mp_fpga.h.

#define M32R_CPM_OFFSET   (0x000F4000+M32R_SFR_OFFSET)

Definition at line 87 of file m32r_mp_fpga.h.

#define M32R_CPM_PLLCR_PORTL   (0x08+M32R_CPM_OFFSET)

Definition at line 91 of file m32r_mp_fpga.h.

#define M32R_CPUID_PORTL   (0xFFFFFFE0)

Definition at line 308 of file m32r_mp_fpga.h.

#define M32R_FPGA_CPU_NAME0_PORTL   (0x10+M32R_FPGA_TOP)

Definition at line 73 of file m32r_mp_fpga.h.

#define M32R_FPGA_CPU_NAME1_PORTL   (0x14+M32R_FPGA_TOP)

Definition at line 74 of file m32r_mp_fpga.h.

#define M32R_FPGA_CPU_NAME2_PORTL   (0x18+M32R_FPGA_TOP)

Definition at line 75 of file m32r_mp_fpga.h.

#define M32R_FPGA_CPU_NAME3_PORTL   (0x1C+M32R_FPGA_TOP)

Definition at line 76 of file m32r_mp_fpga.h.

#define M32R_FPGA_MODEL_ID0_PORTL   (0x20+M32R_FPGA_TOP)

Definition at line 77 of file m32r_mp_fpga.h.

#define M32R_FPGA_MODEL_ID1_PORTL   (0x24+M32R_FPGA_TOP)

Definition at line 78 of file m32r_mp_fpga.h.

#define M32R_FPGA_MODEL_ID2_PORTL   (0x28+M32R_FPGA_TOP)

Definition at line 79 of file m32r_mp_fpga.h.

#define M32R_FPGA_MODEL_ID3_PORTL   (0x2C+M32R_FPGA_TOP)

Definition at line 80 of file m32r_mp_fpga.h.

#define M32R_FPGA_NUM_OF_CPUS_PORTL   (0x00+M32R_FPGA_TOP)

Definition at line 72 of file m32r_mp_fpga.h.

#define M32R_FPGA_TOP   (0x000F0000+M32R_SFR_OFFSET)

Definition at line 70 of file m32r_mp_fpga.h.

#define M32R_FPGA_VERSION0_PORTL   (0x30+M32R_FPGA_TOP)

Definition at line 81 of file m32r_mp_fpga.h.

#define M32R_FPGA_VERSION1_PORTL   (0x34+M32R_FPGA_TOP)

Definition at line 82 of file m32r_mp_fpga.h.

#define M32R_ICU_CR1_PORTL   (0x200+M32R_ICU_OFFSET) /* INT0 */

Definition at line 219 of file m32r_mp_fpga.h.

#define M32R_ICU_CR2_PORTL   (0x204+M32R_ICU_OFFSET) /* INT1 */

Definition at line 220 of file m32r_mp_fpga.h.

#define M32R_ICU_CR32_PORTL   (0x27C+M32R_ICU_OFFSET) /* SIO0 RX */

Definition at line 227 of file m32r_mp_fpga.h.

#define M32R_ICU_CR33_PORTL   (0x280+M32R_ICU_OFFSET) /* SIO0 TX */

Definition at line 228 of file m32r_mp_fpga.h.

#define M32R_ICU_CR3_PORTL   (0x208+M32R_ICU_OFFSET) /* INT2 */

Definition at line 221 of file m32r_mp_fpga.h.

#define M32R_ICU_CR40_PORTL   (0x29C+M32R_ICU_OFFSET) /* DMAC0 */

Definition at line 229 of file m32r_mp_fpga.h.

#define M32R_ICU_CR41_PORTL   (0x2A0+M32R_ICU_OFFSET) /* DMAC1 */

Definition at line 230 of file m32r_mp_fpga.h.

#define M32R_ICU_CR48_PORTL   (0x2BC+M32R_ICU_OFFSET) /* MFT0 */

Definition at line 231 of file m32r_mp_fpga.h.

#define M32R_ICU_CR49_PORTL   (0x2C0+M32R_ICU_OFFSET) /* MFT1 */

Definition at line 232 of file m32r_mp_fpga.h.

#define M32R_ICU_CR4_PORTL   (0x20C+M32R_ICU_OFFSET) /* INT3 */

Definition at line 222 of file m32r_mp_fpga.h.

#define M32R_ICU_CR50_PORTL   (0x2C4+M32R_ICU_OFFSET) /* MFT2 */

Definition at line 233 of file m32r_mp_fpga.h.

#define M32R_ICU_CR51_PORTL   (0x2C8+M32R_ICU_OFFSET) /* MFT3 */

Definition at line 234 of file m32r_mp_fpga.h.

#define M32R_ICU_CR52_PORTL   (0x2CC+M32R_ICU_OFFSET) /* MFT4 */

Definition at line 235 of file m32r_mp_fpga.h.

#define M32R_ICU_CR53_PORTL   (0x2D0+M32R_ICU_OFFSET) /* MFT5 */

Definition at line 236 of file m32r_mp_fpga.h.

#define M32R_ICU_CR5_PORTL   (0x210+M32R_ICU_OFFSET) /* INT4 */

Definition at line 223 of file m32r_mp_fpga.h.

#define M32R_ICU_CR6_PORTL   (0x214+M32R_ICU_OFFSET) /* INT5 */

Definition at line 224 of file m32r_mp_fpga.h.

#define M32R_ICU_CR7_PORTL   (0x218+M32R_ICU_OFFSET) /* INT6 */

Definition at line 225 of file m32r_mp_fpga.h.

#define M32R_ICU_CR8_PORTL   (0x218+M32R_ICU_OFFSET) /* INT7 */

Definition at line 226 of file m32r_mp_fpga.h.

#define M32R_ICU_IMASK_PORTL   (0x01C+M32R_ICU_OFFSET)

Definition at line 218 of file m32r_mp_fpga.h.

#define M32R_ICU_IPICR0_PORTL   (0x2DC+M32R_ICU_OFFSET) /* IPI0 */

Definition at line 237 of file m32r_mp_fpga.h.

#define M32R_ICU_IPICR1_PORTL   (0x2E0+M32R_ICU_OFFSET) /* IPI1 */

Definition at line 238 of file m32r_mp_fpga.h.

#define M32R_ICU_IPICR2_PORTL   (0x2E4+M32R_ICU_OFFSET) /* IPI2 */

Definition at line 239 of file m32r_mp_fpga.h.

#define M32R_ICU_IPICR3_PORTL   (0x2E8+M32R_ICU_OFFSET) /* IPI3 */

Definition at line 240 of file m32r_mp_fpga.h.

#define M32R_ICU_IPICR4_PORTL   (0x2EC+M32R_ICU_OFFSET) /* IPI4 */

Definition at line 241 of file m32r_mp_fpga.h.

#define M32R_ICU_IPICR5_PORTL   (0x2F0+M32R_ICU_OFFSET) /* IPI5 */

Definition at line 242 of file m32r_mp_fpga.h.

#define M32R_ICU_IPICR6_PORTL   (0x2F4+M32R_ICU_OFFSET) /* IPI6 */

Definition at line 243 of file m32r_mp_fpga.h.

#define M32R_ICU_IPICR7_PORTL   (0x2FC+M32R_ICU_OFFSET) /* IPI7 */

Definition at line 244 of file m32r_mp_fpga.h.

#define M32R_ICU_IREQ0_PORTL   (0x008+M32R_ICU_OFFSET)

Definition at line 215 of file m32r_mp_fpga.h.

#define M32R_ICU_IREQ1_PORTL   (0x00C+M32R_ICU_OFFSET)

Definition at line 216 of file m32r_mp_fpga.h.

#define M32R_ICU_ISTS_PORTL   (0x004+M32R_ICU_OFFSET)

Definition at line 214 of file m32r_mp_fpga.h.

#define M32R_ICU_OFFSET   (0x000FF000+M32R_SFR_OFFSET)

Definition at line 212 of file m32r_mp_fpga.h.

#define M32R_ICU_SBICR_PORTL   (0x018+M32R_ICU_OFFSET)

Definition at line 217 of file m32r_mp_fpga.h.

#define M32R_ICUCR_IEN   (1UL<<12) /* b19: Interrupt enable */

Definition at line 259 of file m32r_mp_fpga.h.

#define M32R_ICUCR_ILEVEL0   (0UL<<0) /* b29-b31: Interrupt priority level 0 */

Definition at line 265 of file m32r_mp_fpga.h.

#define M32R_ICUCR_ILEVEL1   (1UL<<0) /* b29-b31: Interrupt priority level 1 */

Definition at line 266 of file m32r_mp_fpga.h.

#define M32R_ICUCR_ILEVEL2   (2UL<<0) /* b29-b31: Interrupt priority level 2 */

Definition at line 267 of file m32r_mp_fpga.h.

#define M32R_ICUCR_ILEVEL3   (3UL<<0) /* b29-b31: Interrupt priority level 3 */

Definition at line 268 of file m32r_mp_fpga.h.

#define M32R_ICUCR_ILEVEL4   (4UL<<0) /* b29-b31: Interrupt priority level 4 */

Definition at line 269 of file m32r_mp_fpga.h.

#define M32R_ICUCR_ILEVEL5   (5UL<<0) /* b29-b31: Interrupt priority level 5 */

Definition at line 270 of file m32r_mp_fpga.h.

#define M32R_ICUCR_ILEVEL6   (6UL<<0) /* b29-b31: Interrupt priority level 6 */

Definition at line 271 of file m32r_mp_fpga.h.

#define M32R_ICUCR_ILEVEL7   (7UL<<0) /* b29-b31: Disable interrupt */

Definition at line 272 of file m32r_mp_fpga.h.

#define M32R_ICUCR_ILEVEL_MASK   (7UL)

Definition at line 273 of file m32r_mp_fpga.h.

#define M32R_ICUCR_IRQ   (1UL<<8) /* b23: Interrupt request */

Definition at line 260 of file m32r_mp_fpga.h.

#define M32R_ICUCR_ISMOD00   (0UL<<4) /* b26-b27: Interrupt sense mode Edge HtoL */

Definition at line 261 of file m32r_mp_fpga.h.

#define M32R_ICUCR_ISMOD01   (1UL<<4) /* b26-b27: Interrupt sense mode Level L */

Definition at line 262 of file m32r_mp_fpga.h.

#define M32R_ICUCR_ISMOD10   (2UL<<4) /* b26-b27: Interrupt sense mode Edge LtoH*/

Definition at line 263 of file m32r_mp_fpga.h.

#define M32R_ICUCR_ISMOD11   (3UL<<4) /* b26-b27: Interrupt sense mode Level H */

Definition at line 264 of file m32r_mp_fpga.h.

#define M32R_ICUIMASK_IMSK0   (0UL<<16) /* b13-b15: Disable interrupt */

Definition at line 250 of file m32r_mp_fpga.h.

#define M32R_ICUIMASK_IMSK1   (1UL<<16) /* b13-b15: Enable level 0 interrupt */

Definition at line 251 of file m32r_mp_fpga.h.

#define M32R_ICUIMASK_IMSK2   (2UL<<16) /* b13-b15: Enable level 0,1 interrupt */

Definition at line 252 of file m32r_mp_fpga.h.

#define M32R_ICUIMASK_IMSK3   (3UL<<16) /* b13-b15: Enable level 0-2 interrupt */

Definition at line 253 of file m32r_mp_fpga.h.

#define M32R_ICUIMASK_IMSK4   (4UL<<16) /* b13-b15: Enable level 0-3 interrupt */

Definition at line 254 of file m32r_mp_fpga.h.

#define M32R_ICUIMASK_IMSK5   (5UL<<16) /* b13-b15: Enable level 0-4 interrupt */

Definition at line 255 of file m32r_mp_fpga.h.

#define M32R_ICUIMASK_IMSK6   (6UL<<16) /* b13-b15: Enable level 0-5 interrupt */

Definition at line 256 of file m32r_mp_fpga.h.

#define M32R_ICUIMASK_IMSK7   (7UL<<16) /* b13-b15: Enable level 0-6 interrupt */

Definition at line 257 of file m32r_mp_fpga.h.

#define M32R_ICUISTS_ISN

(

val

)

((val>>22) & 0x3F)

Definition at line 247 of file m32r_mp_fpga.h.

#define M32R_ICUISTS_PIML

(

val

)

((val>>16) & 0x7)

Definition at line 248 of file m32r_mp_fpga.h.

#define M32R_ICUISTS_VECB

(

val

)

((val>>28) & 0xF)

Definition at line 246 of file m32r_mp_fpga.h.

#define M32R_IRQ_DMAC0   (32) /* DMAC0 */

Definition at line 289 of file m32r_mp_fpga.h.

#define M32R_IRQ_DMAC1   (33) /* DMAC1 */

Definition at line 290 of file m32r_mp_fpga.h.

#define M32R_IRQ_INT0   (1) /* INT0 */

Definition at line 275 of file m32r_mp_fpga.h.

#define M32R_IRQ_INT1   (2) /* INT1 */

Definition at line 276 of file m32r_mp_fpga.h.

#define M32R_IRQ_INT2   (3) /* INT2 */

Definition at line 277 of file m32r_mp_fpga.h.

#define M32R_IRQ_INT3   (4) /* INT3 */

Definition at line 278 of file m32r_mp_fpga.h.

#define M32R_IRQ_INT4   (5) /* INT4 */

Definition at line 279 of file m32r_mp_fpga.h.

#define M32R_IRQ_INT5   (6) /* INT5 */

Definition at line 280 of file m32r_mp_fpga.h.

#define M32R_IRQ_INT6   (7) /* INT6 */

Definition at line 281 of file m32r_mp_fpga.h.

#define M32R_IRQ_INT7   (8) /* INT7 */

Definition at line 282 of file m32r_mp_fpga.h.

#define M32R_IRQ_IPI0   (56) /* IPI0 */

Definition at line 295 of file m32r_mp_fpga.h.

#define M32R_IRQ_IPI1   (57) /* IPI1 */

Definition at line 296 of file m32r_mp_fpga.h.

#define M32R_IRQ_IPI2   (58) /* IPI2 */

Definition at line 297 of file m32r_mp_fpga.h.

#define M32R_IRQ_IPI3   (59) /* IPI3 */

Definition at line 298 of file m32r_mp_fpga.h.

#define M32R_IRQ_IPI4   (60) /* IPI4 */

Definition at line 299 of file m32r_mp_fpga.h.

#define M32R_IRQ_IPI5   (61) /* IPI5 */

Definition at line 300 of file m32r_mp_fpga.h.

#define M32R_IRQ_IPI6   (62) /* IPI6 */

Definition at line 301 of file m32r_mp_fpga.h.

#define M32R_IRQ_IPI7   (63) /* IPI7 */

Definition at line 302 of file m32r_mp_fpga.h.

#define M32R_IRQ_MFT0   (16) /* MFT0 */

Definition at line 283 of file m32r_mp_fpga.h.

#define M32R_IRQ_MFT1   (17) /* MFT1 */

Definition at line 284 of file m32r_mp_fpga.h.

#define M32R_IRQ_MFT2   (18) /* MFT2 */

Definition at line 285 of file m32r_mp_fpga.h.

#define M32R_IRQ_MFT3   (19) /* MFT3 */

Definition at line 286 of file m32r_mp_fpga.h.

#define M32R_IRQ_MFT4   (20) /* MFT4 */

Definition at line 287 of file m32r_mp_fpga.h.

#define M32R_IRQ_MFT5   (21) /* MFT5 */

Definition at line 288 of file m32r_mp_fpga.h.

#define M32R_IRQ_SIO0_R   (48) /* SIO0 receive */

Definition at line 291 of file m32r_mp_fpga.h.

#define M32R_IRQ_SIO0_S   (49) /* SIO0 send */

Definition at line 292 of file m32r_mp_fpga.h.

#define M32R_IRQ_SIO1_R   (50) /* SIO1 send */

Definition at line 293 of file m32r_mp_fpga.h.

#define M32R_IRQ_SIO1_S   (51) /* SIO1 receive */

Definition at line 294 of file m32r_mp_fpga.h.

#define M32R_MCCR_PORTL   (0xFFFFFFFC)

Definition at line 311 of file m32r_mp_fpga.h.

#define M32R_MCDCAR_PORTL   (0xFFFFFFF4)

Definition at line 310 of file m32r_mp_fpga.h.

#define M32R_MCICAR_PORTL   (0xFFFFFFF0)

Definition at line 309 of file m32r_mp_fpga.h.

#define M32R_MFT0_OFFSET   (0x100+M32R_MFT_OFFSET)

Definition at line 123 of file m32r_mp_fpga.h.

#define M32R_MFT0BOS_PORTL   (0x04+M32R_MFT0_OFFSET) /* MFT0 b-port output status */

Definition at line 125 of file m32r_mp_fpga.h.

#define M32R_MFT0CMPRLD_PORTL   (0x10+M32R_MFT0_OFFSET) /* MFT0 compare reload */

Definition at line 128 of file m32r_mp_fpga.h.

#define M32R_MFT0CUT_PORTL   (0x08+M32R_MFT0_OFFSET) /* MFT0 count */

Definition at line 126 of file m32r_mp_fpga.h.

#define M32R_MFT0MOD_PORTL   (0x00+M32R_MFT0_OFFSET) /* MFT0 mode */

Definition at line 124 of file m32r_mp_fpga.h.

#define M32R_MFT0RLD_PORTL   (0x0C+M32R_MFT0_OFFSET) /* MFT0 reload */

Definition at line 127 of file m32r_mp_fpga.h.

#define M32R_MFT1_OFFSET   (0x200+M32R_MFT_OFFSET)

Definition at line 130 of file m32r_mp_fpga.h.

#define M32R_MFT1BOS_PORTL   (0x04+M32R_MFT1_OFFSET) /* MFT1 b-port output status */

Definition at line 132 of file m32r_mp_fpga.h.

#define M32R_MFT1CMPRLD_PORTL   (0x10+M32R_MFT1_OFFSET) /* MFT1 compare reload */

Definition at line 135 of file m32r_mp_fpga.h.

#define M32R_MFT1CUT_PORTL   (0x08+M32R_MFT1_OFFSET) /* MFT1 count */

Definition at line 133 of file m32r_mp_fpga.h.

#define M32R_MFT1MOD_PORTL   (0x00+M32R_MFT1_OFFSET) /* MFT1 mode */

Definition at line 131 of file m32r_mp_fpga.h.

#define M32R_MFT1RLD_PORTL   (0x0C+M32R_MFT1_OFFSET) /* MFT1 reload */

Definition at line 134 of file m32r_mp_fpga.h.

#define M32R_MFT2_OFFSET   (0x300+M32R_MFT_OFFSET)

Definition at line 137 of file m32r_mp_fpga.h.

#define M32R_MFT2BOS_PORTL   (0x04+M32R_MFT2_OFFSET) /* MFT2 b-port output status */

Definition at line 139 of file m32r_mp_fpga.h.

#define M32R_MFT2CMPRLD_PORTL   (0x10+M32R_MFT2_OFFSET) /* MFT2 compare reload */

Definition at line 142 of file m32r_mp_fpga.h.

#define M32R_MFT2CUT_PORTL   (0x08+M32R_MFT2_OFFSET) /* MFT2 count */

Definition at line 140 of file m32r_mp_fpga.h.

#define M32R_MFT2MOD_PORTL   (0x00+M32R_MFT2_OFFSET) /* MFT2 mode */

Definition at line 138 of file m32r_mp_fpga.h.

#define M32R_MFT2RLD_PORTL   (0x0C+M32R_MFT2_OFFSET) /* MFT2 reload */

Definition at line 141 of file m32r_mp_fpga.h.

#define M32R_MFT3_OFFSET   (0x400+M32R_MFT_OFFSET)

Definition at line 144 of file m32r_mp_fpga.h.

#define M32R_MFT3BOS_PORTL   (0x04+M32R_MFT3_OFFSET) /* MFT3 b-port output status */

Definition at line 146 of file m32r_mp_fpga.h.

#define M32R_MFT3CMPRLD_PORTL   (0x10+M32R_MFT3_OFFSET) /* MFT3 compare reload */

Definition at line 149 of file m32r_mp_fpga.h.

#define M32R_MFT3CUT_PORTL   (0x08+M32R_MFT3_OFFSET) /* MFT3 count */

Definition at line 147 of file m32r_mp_fpga.h.

#define M32R_MFT3MOD_PORTL   (0x00+M32R_MFT3_OFFSET) /* MFT3 mode */

Definition at line 145 of file m32r_mp_fpga.h.

#define M32R_MFT3RLD_PORTL   (0x0C+M32R_MFT3_OFFSET) /* MFT3 reload */

Definition at line 148 of file m32r_mp_fpga.h.

#define M32R_MFT4_OFFSET   (0x500+M32R_MFT_OFFSET)

Definition at line 151 of file m32r_mp_fpga.h.

#define M32R_MFT4BOS_PORTL   (0x04+M32R_MFT4_OFFSET) /* MFT4 b-port output status */

Definition at line 153 of file m32r_mp_fpga.h.

#define M32R_MFT4CMPRLD_PORTL   (0x10+M32R_MFT4_OFFSET) /* MFT4 compare reload */

Definition at line 156 of file m32r_mp_fpga.h.

#define M32R_MFT4CUT_PORTL   (0x08+M32R_MFT4_OFFSET) /* MFT4 count */

Definition at line 154 of file m32r_mp_fpga.h.

#define M32R_MFT4MOD_PORTL   (0x00+M32R_MFT4_OFFSET) /* MFT4 mode */

Definition at line 152 of file m32r_mp_fpga.h.

#define M32R_MFT4RLD_PORTL   (0x0C+M32R_MFT4_OFFSET) /* MFT4 reload */

Definition at line 155 of file m32r_mp_fpga.h.

#define M32R_MFT5_OFFSET   (0x600+M32R_MFT_OFFSET)

Definition at line 158 of file m32r_mp_fpga.h.

#define M32R_MFT5BOS_PORTL   (0x04+M32R_MFT5_OFFSET) /* MFT4 b-port output status */

Definition at line 160 of file m32r_mp_fpga.h.

#define M32R_MFT5CMPRLD_PORTL   (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */

Definition at line 163 of file m32r_mp_fpga.h.

#define M32R_MFT5CUT_PORTL   (0x08+M32R_MFT5_OFFSET) /* MFT4 count */

Definition at line 161 of file m32r_mp_fpga.h.

#define M32R_MFT5MOD_PORTL   (0x00+M32R_MFT5_OFFSET) /* MFT4 mode */

Definition at line 159 of file m32r_mp_fpga.h.

#define M32R_MFT5RLD_PORTL   (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */

Definition at line 162 of file m32r_mp_fpga.h.

#define M32R_MFT_OFFSET   (0x000FC000+M32R_SFR_OFFSET)

Definition at line 118 of file m32r_mp_fpga.h.

#define M32R_MFTCR_MFT0EN   (1UL<<7) /* b24 */

Definition at line 171 of file m32r_mp_fpga.h.

#define M32R_MFTCR_MFT0MSK   (1UL<<15) /* b16 */

Definition at line 165 of file m32r_mp_fpga.h.

#define M32R_MFTCR_MFT1EN   (1UL<<6) /* b25 */

Definition at line 172 of file m32r_mp_fpga.h.

#define M32R_MFTCR_MFT1MSK   (1UL<<14) /* b17 */

Definition at line 166 of file m32r_mp_fpga.h.

#define M32R_MFTCR_MFT2EN   (1UL<<5) /* b26 */

Definition at line 173 of file m32r_mp_fpga.h.

#define M32R_MFTCR_MFT2MSK   (1UL<<13) /* b18 */

Definition at line 167 of file m32r_mp_fpga.h.

#define M32R_MFTCR_MFT3EN   (1UL<<4) /* b27 */

Definition at line 174 of file m32r_mp_fpga.h.

#define M32R_MFTCR_MFT3MSK   (1UL<<12) /* b19 */

Definition at line 168 of file m32r_mp_fpga.h.

#define M32R_MFTCR_MFT4EN   (1UL<<3) /* b28 */

Definition at line 175 of file m32r_mp_fpga.h.

#define M32R_MFTCR_MFT4MSK   (1UL<<11) /* b20 */

Definition at line 169 of file m32r_mp_fpga.h.

#define M32R_MFTCR_MFT5EN   (1UL<<2) /* b29 */

Definition at line 176 of file m32r_mp_fpga.h.

#define M32R_MFTCR_MFT5MSK   (1UL<<10) /* b21 */

Definition at line 170 of file m32r_mp_fpga.h.

#define M32R_MFTCR_PORTL   (0x000+M32R_MFT_OFFSET) /* MFT control */

Definition at line 120 of file m32r_mp_fpga.h.

#define M32R_MFTMOD_CC_MASK   (1UL<<15) /* b16 */

Definition at line 178 of file m32r_mp_fpga.h.

#define M32R_MFTMOD_CMSEL   (1UL<<3) /* b28 */

Definition at line 186 of file m32r_mp_fpga.h.

#define M32R_MFTMOD_CSSEL000   (0UL<<0) /* b29-b31 : 000 */

Definition at line 187 of file m32r_mp_fpga.h.

#define M32R_MFTMOD_CSSEL001   (1UL<<0) /* b29-b31 : 001 */

Definition at line 188 of file m32r_mp_fpga.h.

#define M32R_MFTMOD_CSSEL010   (2UL<<0) /* b29-b31 : 010 */

Definition at line 189 of file m32r_mp_fpga.h.

#define M32R_MFTMOD_CSSEL011   (3UL<<0) /* b29-b31 : 011 */

Definition at line 190 of file m32r_mp_fpga.h.

#define M32R_MFTMOD_CSSEL100   (4UL<<0) /* b29-b31 : 100 */

Definition at line 191 of file m32r_mp_fpga.h.

#define M32R_MFTMOD_CSSEL110   (6UL<<0) /* b29-b31 : 110 */

Definition at line 192 of file m32r_mp_fpga.h.

#define M32R_MFTMOD_GTSEL000   (0UL<<8) /* b21-23 : 000 */

Definition at line 180 of file m32r_mp_fpga.h.

#define M32R_MFTMOD_GTSEL001   (1UL<<8) /* b21-23 : 001 */

Definition at line 181 of file m32r_mp_fpga.h.

#define M32R_MFTMOD_GTSEL010   (2UL<<8) /* b21-23 : 010 */

Definition at line 182 of file m32r_mp_fpga.h.

#define M32R_MFTMOD_GTSEL011   (3UL<<8) /* b21-23 : 011 */

Definition at line 183 of file m32r_mp_fpga.h.

#define M32R_MFTMOD_GTSEL110   (6UL<<8) /* b21-23 : 110 */

Definition at line 184 of file m32r_mp_fpga.h.

#define M32R_MFTMOD_GTSEL111   (7UL<<8) /* b21-23 : 111 */

Definition at line 185 of file m32r_mp_fpga.h.

#define M32R_MFTMOD_TCCR   (1UL<<13) /* b18 */

Definition at line 179 of file m32r_mp_fpga.h.

#define M32R_MFTRPR_PORTL   (0x004+M32R_MFT_OFFSET) /* MFT real port */

Definition at line 121 of file m32r_mp_fpga.h.

#define M32R_SFR_OFFSET   (0x00E00000) /* 0x03E00000-0x03EFFFFF 1[MB] */

Definition at line 65 of file m32r_mp_fpga.h.

#define M32R_SIO0_BAUR_PORTL   (0x014+M32R_SIO_OFFSET)

Definition at line 204 of file m32r_mp_fpga.h.

#define M32R_SIO0_CR_PORTL   (0x000+M32R_SIO_OFFSET)

Definition at line 199 of file m32r_mp_fpga.h.

#define M32R_SIO0_MOD0_PORTL   (0x004+M32R_SIO_OFFSET)

Definition at line 200 of file m32r_mp_fpga.h.

#define M32R_SIO0_MOD1_PORTL   (0x008+M32R_SIO_OFFSET)

Definition at line 201 of file m32r_mp_fpga.h.

#define M32R_SIO0_RBAUR_PORTL   (0x018+M32R_SIO_OFFSET)

Definition at line 205 of file m32r_mp_fpga.h.

#define M32R_SIO0_RXB_PORTL   (0x020+M32R_SIO_OFFSET)

Definition at line 207 of file m32r_mp_fpga.h.

#define M32R_SIO0_STS_PORTL   (0x00C+M32R_SIO_OFFSET)

Definition at line 202 of file m32r_mp_fpga.h.

#define M32R_SIO0_TRCR_PORTL   (0x010+M32R_SIO_OFFSET)

Definition at line 203 of file m32r_mp_fpga.h.

#define M32R_SIO0_TXB_PORTL   (0x01C+M32R_SIO_OFFSET)

Definition at line 206 of file m32r_mp_fpga.h.

#define M32R_SIO_OFFSET   (0x000FD000+M32R_SFR_OFFSET)

Definition at line 197 of file m32r_mp_fpga.h.