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m525xsim.h
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1 /****************************************************************************/
2 
3 /*
4  * m525xsim.h -- ColdFire 525x System Integration Module support.
5  *
6  * (C) Copyright 2012, Steven king <[email protected]>
7  * (C) Copyright 2002, Greg Ungerer ([email protected])
8  */
9 
10 /****************************************************************************/
11 #ifndef m525xsim_h
12 #define m525xsim_h
13 /****************************************************************************/
14 
15 #define CPU_NAME "COLDFIRE(m525x)"
16 #define CPU_INSTR_PER_JIFFY 3
17 #define MCF_BUSCLK (MCF_CLK / 2)
18 
19 #include <asm/m52xxacr.h>
20 
21 /*
22  * The 525x has a second MBAR region, define its address.
23  */
24 #define MCF_MBAR2 0x80000000
25 
26 /*
27  * Define the 525x SIM register set addresses.
28  */
29 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
30 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
31 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
32 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
33 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
34 #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
35 #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
36 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
37 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
38 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
39 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
40 #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
41 #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
42 #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
43 #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
44 #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
45 #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
46 #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
47 #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
48 
49 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
50 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
51 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
52 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
53 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
54 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
55 #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
56 #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
57 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
58 #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
59 #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
60 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
61 #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
62 #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
63 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
64 
65 #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
66 #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
67 #define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
68 
69 /*
70  * Secondary Interrupt Controller (in MBAR2)
71 */
72 #define MCFINTC2_INTBASE (MCF_MBAR2 + 0x168) /* Base Vector Reg */
73 #define MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */
74 #define MCFINTC2_INTPRI2 (MCF_MBAR2 + 0x144) /* 8-15 priority */
75 #define MCFINTC2_INTPRI3 (MCF_MBAR2 + 0x148) /* 16-23 priority */
76 #define MCFINTC2_INTPRI4 (MCF_MBAR2 + 0x14c) /* 24-31 priority */
77 #define MCFINTC2_INTPRI5 (MCF_MBAR2 + 0x150) /* 32-39 priority */
78 #define MCFINTC2_INTPRI6 (MCF_MBAR2 + 0x154) /* 40-47 priority */
79 #define MCFINTC2_INTPRI7 (MCF_MBAR2 + 0x158) /* 48-55 priority */
80 #define MCFINTC2_INTPRI8 (MCF_MBAR2 + 0x15c) /* 56-63 priority */
81 
82 #define MCFINTC2_INTPRI_REG(i) (MCFINTC2_INTPRI1 + \
83  ((((i) - MCFINTC2_VECBASE) / 8) * 4))
84 #define MCFINTC2_INTPRI_BITS(b, i) ((b) << (((i) % 8) * 4))
85 
86 /*
87  * Timer module.
88  */
89 #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
90 #define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
91 
92 /*
93  * UART module.
94  */
95 #define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
96 #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
97 
98 /*
99  * QSPI module.
100  */
101 #define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */
102 #define MCFQSPI_SIZE 0x40 /* Register set size */
103 
104 
105 #define MCFQSPI_CS0 15
106 #define MCFQSPI_CS1 16
107 #define MCFQSPI_CS2 24
108 #define MCFQSPI_CS3 28
109 
110 /*
111  * I2C module.
112  */
113 #define MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base addreess I2C0 */
114 #define MCFI2C_SIZE0 0x20 /* Register set size */
115 
116 #define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base addreess I2C1 */
117 #define MCFI2C_SIZE1 0x20 /* Register set size */
118 /*
119  * DMA unit base addresses.
120  */
121 #define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
122 #define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
123 #define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
124 #define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
125 
126 /*
127  * Some symbol defines for the above...
128  */
129 #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
130 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
131 #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
132 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
133 #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
134 #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
135 #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
136 #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
137 #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
138 #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
139 #define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
140 
141 /*
142  * Define system peripheral IRQ usage.
143  */
144 #define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
145 #define MCF_IRQ_I2C0 29
146 #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
147 #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
148 
149 #define MCF_IRQ_UART0 73 /* UART0 */
150 #define MCF_IRQ_UART1 74 /* UART1 */
151 
152 /*
153  * Define the base interrupt for the second interrupt controller.
154  * We set it to 128, out of the way of the base interrupts, and plenty
155  * of room for its 64 interrupts.
156  */
157 #define MCFINTC2_VECBASE 128
158 
159 #define MCF_IRQ_GPIO0 (MCFINTC2_VECBASE + 32)
160 #define MCF_IRQ_GPIO1 (MCFINTC2_VECBASE + 33)
161 #define MCF_IRQ_GPIO2 (MCFINTC2_VECBASE + 34)
162 #define MCF_IRQ_GPIO3 (MCFINTC2_VECBASE + 35)
163 #define MCF_IRQ_GPIO4 (MCFINTC2_VECBASE + 36)
164 #define MCF_IRQ_GPIO5 (MCFINTC2_VECBASE + 37)
165 #define MCF_IRQ_GPIO6 (MCFINTC2_VECBASE + 38)
166 
167 #define MCF_IRQ_USBWUP (MCFINTC2_VECBASE + 40)
168 #define MCF_IRQ_I2C1 (MCFINTC2_VECBASE + 62)
169 
170 /*
171  * General purpose IO registers (in MBAR2).
172  */
173 #define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
174 #define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
175 #define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
176 #define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
177 #define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
178 #define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
179 #define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
180 #define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
181 
182 #define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */
183 #define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
184 #define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
185 
186 /*
187  * Generic GPIO support
188  */
189 #define MCFGPIO_PIN_MAX 64
190 #define MCFGPIO_IRQ_MAX 7
191 #define MCFGPIO_IRQ_VECBASE MCF_IRQ_GPIO0
192 
193 /****************************************************************************/
194 #endif /* m525xsim_h */
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