m52xxacr.h File Reference

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Macros
#define	CACR_CENB   0x80000000 /* Enable cache */
#define	CACR_CDPI   0x10000000 /* Disable invalidation by CPUSHL */
#define	CACR_CFRZ   0x08000000 /* Cache freeze mode */
#define	CACR_CINV   0x01000000 /* Invalidate cache */
#define	CACR_DISI   0x00800000 /* Disable instruction cache */
#define	CACR_DISD   0x00400000 /* Disable data cache */
#define	CACR_INVI   0x00200000 /* Invalidate instruction cache */
#define	CACR_INVD   0x00100000 /* Invalidate data cache */
#define	CACR_CEIB   0x00000400 /* Non-cachable instruction burst */
#define	CACR_DCM   0x00000200 /* Default cache mode */
#define	CACR_DBWE   0x00000100 /* Buffered write enable */
#define	CACR_DWP   0x00000020 /* Write protection */
#define	CACR_EUSP   0x00000010 /* Enable separate user a7 */
#define	ACR_BASE_POS   24 /* Address Base (upper 8 bits) */
#define	ACR_MASK_POS   16 /* Address Mask (next 8 bits) */
#define	ACR_ENABLE   0x00008000 /* Enable this ACR */
#define	ACR_USER   0x00000000 /* Allow only user accesses */
#define	ACR_SUPER   0x00002000 /* Allow supervisor access only */
#define	ACR_ANY   0x00004000 /* Allow any access type */
#define	ACR_CENB   0x00000000 /* Caching of region enabled */
#define	ACR_CDIS   0x00000040 /* Caching of region disabled */
#define	ACR_BWE   0x00000020 /* Write buffer enabled */
#define	ACR_WPROTECT   0x00000004 /* Write protect region */
#define	CACHE_TYPE   0
#define	CACHE_INVTYPEI   0
#define	CACHE_INIT   (CACR_CINV + CACHE_TYPE)
#define	CACHE_MODE   (CACR_CENB + CACHE_TYPE + CACR_DCM)
#define	CACHE_INVALIDATE   (CACHE_MODE + CACR_CINV)
#define	CACHE_INVALIDATEI   (CACHE_MODE + CACR_CINV + CACHE_INVTYPEI)
#define	ACR0_MODE
#define	ACR1_MODE   0

Macro Definition Documentation

#define ACR0_MODE

Value:

((CONFIG_RAMBASE & 0xff000000) + \
             (0x000f0000) + \
             (ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE))

Definition at line 88 of file m52xxacr.h.

#define ACR1_MODE   0

Definition at line 91 of file m52xxacr.h.

#define ACR_ANY   0x00004000 /* Allow any access type */

Definition at line 49 of file m52xxacr.h.

#define ACR_BASE_POS   24 /* Address Base (upper 8 bits) */

Definition at line 44 of file m52xxacr.h.

#define ACR_BWE   0x00000020 /* Write buffer enabled */

Definition at line 52 of file m52xxacr.h.

#define ACR_CDIS   0x00000040 /* Caching of region disabled */

Definition at line 51 of file m52xxacr.h.

#define ACR_CENB   0x00000000 /* Caching of region enabled */

Definition at line 50 of file m52xxacr.h.

#define ACR_ENABLE   0x00008000 /* Enable this ACR */

Definition at line 46 of file m52xxacr.h.

#define ACR_MASK_POS   16 /* Address Mask (next 8 bits) */

Definition at line 45 of file m52xxacr.h.

#define ACR_SUPER   0x00002000 /* Allow supervisor access only */

Definition at line 48 of file m52xxacr.h.

#define ACR_USER   0x00000000 /* Allow only user accesses */

Definition at line 47 of file m52xxacr.h.

#define ACR_WPROTECT   0x00000004 /* Write protect region */

Definition at line 53 of file m52xxacr.h.

#define CACHE_INIT   (CACR_CINV + CACHE_TYPE)

Definition at line 77 of file m52xxacr.h.

#define CACHE_INVALIDATE   (CACHE_MODE + CACR_CINV)

Definition at line 80 of file m52xxacr.h.

#define CACHE_INVALIDATEI   (CACHE_MODE + CACR_CINV + CACHE_INVTYPEI)

Definition at line 82 of file m52xxacr.h.

#define CACHE_INVTYPEI   0

Definition at line 74 of file m52xxacr.h.

#define CACHE_MODE   (CACR_CENB + CACHE_TYPE + CACR_DCM)

Definition at line 78 of file m52xxacr.h.

#define CACHE_TYPE   0

Definition at line 73 of file m52xxacr.h.

#define CACR_CDPI   0x10000000 /* Disable invalidation by CPUSHL */

Definition at line 28 of file m52xxacr.h.

#define CACR_CEIB   0x00000400 /* Non-cachable instruction burst */

Definition at line 35 of file m52xxacr.h.

#define CACR_CENB   0x80000000 /* Enable cache */

Definition at line 27 of file m52xxacr.h.

#define CACR_CFRZ   0x08000000 /* Cache freeze mode */

Definition at line 29 of file m52xxacr.h.

#define CACR_CINV   0x01000000 /* Invalidate cache */

Definition at line 30 of file m52xxacr.h.

#define CACR_DBWE   0x00000100 /* Buffered write enable */

Definition at line 37 of file m52xxacr.h.

#define CACR_DCM   0x00000200 /* Default cache mode */

Definition at line 36 of file m52xxacr.h.

#define CACR_DISD   0x00400000 /* Disable data cache */

Definition at line 32 of file m52xxacr.h.

#define CACR_DISI   0x00800000 /* Disable instruction cache */

Definition at line 31 of file m52xxacr.h.

#define CACR_DWP   0x00000020 /* Write protection */

Definition at line 38 of file m52xxacr.h.

#define CACR_EUSP   0x00000010 /* Enable separate user a7 */

Definition at line 39 of file m52xxacr.h.

#define CACR_INVD   0x00100000 /* Invalidate data cache */

Definition at line 34 of file m52xxacr.h.

#define CACR_INVI   0x00200000 /* Invalidate instruction cache */

Definition at line 33 of file m52xxacr.h.