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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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#include <asm/m52xxacr.h>Go to the source code of this file.
Macros | |
| #define | CPU_NAME "COLDFIRE(m525x)" |
| #define | CPU_INSTR_PER_JIFFY 3 |
| #define | MCF_BUSCLK (MCF_CLK / 2) |
| #define | MCF_MBAR2 0x80000000 |
| #define | MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ |
| #define | MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ |
| #define | MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ |
| #define | MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */ |
| #define | MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */ |
| #define | MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */ |
| #define | MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ |
| #define | MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ |
| #define | MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ |
| #define | MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */ |
| #define | MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */ |
| #define | MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */ |
| #define | MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */ |
| #define | MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */ |
| #define | MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */ |
| #define | MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */ |
| #define | MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */ |
| #define | MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */ |
| #define | MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */ |
| #define | MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */ |
| #define | MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */ |
| #define | MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */ |
| #define | MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */ |
| #define | MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */ |
| #define | MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */ |
| #define | MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */ |
| #define | MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */ |
| #define | MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ |
| #define | MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */ |
| #define | MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */ |
| #define | MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ |
| #define | MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */ |
| #define | MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */ |
| #define | MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ |
| #define | MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ |
| #define | MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ |
| #define | MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */ |
| #define | MCFINTC2_INTBASE (MCF_MBAR2 + 0x168) /* Base Vector Reg */ |
| #define | MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */ |
| #define | MCFINTC2_INTPRI2 (MCF_MBAR2 + 0x144) /* 8-15 priority */ |
| #define | MCFINTC2_INTPRI3 (MCF_MBAR2 + 0x148) /* 16-23 priority */ |
| #define | MCFINTC2_INTPRI4 (MCF_MBAR2 + 0x14c) /* 24-31 priority */ |
| #define | MCFINTC2_INTPRI5 (MCF_MBAR2 + 0x150) /* 32-39 priority */ |
| #define | MCFINTC2_INTPRI6 (MCF_MBAR2 + 0x154) /* 40-47 priority */ |
| #define | MCFINTC2_INTPRI7 (MCF_MBAR2 + 0x158) /* 48-55 priority */ |
| #define | MCFINTC2_INTPRI8 (MCF_MBAR2 + 0x15c) /* 56-63 priority */ |
| #define | MCFINTC2_INTPRI_REG(i) |
| #define | MCFINTC2_INTPRI_BITS(b, i) ((b) << (((i) % 8) * 4)) |
| #define | MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ |
| #define | MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ |
| #define | MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ |
| #define | MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ |
| #define | MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */ |
| #define | MCFQSPI_SIZE 0x40 /* Register set size */ |
| #define | MCFQSPI_CS0 15 |
| #define | MCFQSPI_CS1 16 |
| #define | MCFQSPI_CS2 24 |
| #define | MCFQSPI_CS3 28 |
| #define | MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base addreess I2C0 */ |
| #define | MCFI2C_SIZE0 0x20 /* Register set size */ |
| #define | MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base addreess I2C1 */ |
| #define | MCFI2C_SIZE1 0x20 /* Register set size */ |
| #define | MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ |
| #define | MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ |
| #define | MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ |
| #define | MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ |
| #define | MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ |
| #define | MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ |
| #define | MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ |
| #define | MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */ |
| #define | MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ |
| #define | MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ |
| #define | MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ |
| #define | MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ |
| #define | MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ |
| #define | MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ |
| #define | MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */ |
| #define | MCF_IRQ_QSPI 28 /* QSPI, Level 4 */ |
| #define | MCF_IRQ_I2C0 29 |
| #define | MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ |
| #define | MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ |
| #define | MCF_IRQ_UART0 73 /* UART0 */ |
| #define | MCF_IRQ_UART1 74 /* UART1 */ |
| #define | MCFINTC2_VECBASE 128 |
| #define | MCF_IRQ_GPIO0 (MCFINTC2_VECBASE + 32) |
| #define | MCF_IRQ_GPIO1 (MCFINTC2_VECBASE + 33) |
| #define | MCF_IRQ_GPIO2 (MCFINTC2_VECBASE + 34) |
| #define | MCF_IRQ_GPIO3 (MCFINTC2_VECBASE + 35) |
| #define | MCF_IRQ_GPIO4 (MCFINTC2_VECBASE + 36) |
| #define | MCF_IRQ_GPIO5 (MCFINTC2_VECBASE + 37) |
| #define | MCF_IRQ_GPIO6 (MCFINTC2_VECBASE + 38) |
| #define | MCF_IRQ_USBWUP (MCFINTC2_VECBASE + 40) |
| #define | MCF_IRQ_I2C1 (MCFINTC2_VECBASE + 62) |
| #define | MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */ |
| #define | MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */ |
| #define | MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */ |
| #define | MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */ |
| #define | MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */ |
| #define | MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */ |
| #define | MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */ |
| #define | MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */ |
| #define | MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */ |
| #define | MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */ |
| #define | MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */ |
| #define | MCFGPIO_PIN_MAX 64 |
| #define | MCFGPIO_IRQ_MAX 7 |
| #define | MCFGPIO_IRQ_VECBASE MCF_IRQ_GPIO0 |
| #define CPU_INSTR_PER_JIFFY 3 |
Definition at line 16 of file m525xsim.h.
| #define CPU_NAME "COLDFIRE(m525x)" |
Definition at line 15 of file m525xsim.h.
| #define MCF_BUSCLK (MCF_CLK / 2) |
Definition at line 17 of file m525xsim.h.
| #define MCF_IRQ_GPIO0 (MCFINTC2_VECBASE + 32) |
Definition at line 159 of file m525xsim.h.
| #define MCF_IRQ_GPIO1 (MCFINTC2_VECBASE + 33) |
Definition at line 160 of file m525xsim.h.
| #define MCF_IRQ_GPIO2 (MCFINTC2_VECBASE + 34) |
Definition at line 161 of file m525xsim.h.
| #define MCF_IRQ_GPIO3 (MCFINTC2_VECBASE + 35) |
Definition at line 162 of file m525xsim.h.
| #define MCF_IRQ_GPIO4 (MCFINTC2_VECBASE + 36) |
Definition at line 163 of file m525xsim.h.
| #define MCF_IRQ_GPIO5 (MCFINTC2_VECBASE + 37) |
Definition at line 164 of file m525xsim.h.
| #define MCF_IRQ_GPIO6 (MCFINTC2_VECBASE + 38) |
Definition at line 165 of file m525xsim.h.
| #define MCF_IRQ_I2C0 29 |
Definition at line 145 of file m525xsim.h.
| #define MCF_IRQ_I2C1 (MCFINTC2_VECBASE + 62) |
Definition at line 168 of file m525xsim.h.
| #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ |
Definition at line 147 of file m525xsim.h.
| #define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */ |
Definition at line 144 of file m525xsim.h.
| #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ |
Definition at line 146 of file m525xsim.h.
| #define MCF_IRQ_UART0 73 /* UART0 */ |
Definition at line 149 of file m525xsim.h.
| #define MCF_IRQ_UART1 74 /* UART1 */ |
Definition at line 150 of file m525xsim.h.
| #define MCF_IRQ_USBWUP (MCFINTC2_VECBASE + 40) |
Definition at line 167 of file m525xsim.h.
| #define MCF_MBAR2 0x80000000 |
Definition at line 24 of file m525xsim.h.
| #define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ |
Definition at line 121 of file m525xsim.h.
| #define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ |
Definition at line 122 of file m525xsim.h.
| #define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ |
Definition at line 123 of file m525xsim.h.
| #define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ |
Definition at line 124 of file m525xsim.h.
| #define MCFGPIO_IRQ_MAX 7 |
Definition at line 190 of file m525xsim.h.
| #define MCFGPIO_IRQ_VECBASE MCF_IRQ_GPIO0 |
Definition at line 191 of file m525xsim.h.
| #define MCFGPIO_PIN_MAX 64 |
Definition at line 189 of file m525xsim.h.
| #define MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base addreess I2C0 */ |
Definition at line 113 of file m525xsim.h.
| #define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base addreess I2C1 */ |
Definition at line 116 of file m525xsim.h.
| #define MCFI2C_SIZE0 0x20 /* Register set size */ |
Definition at line 114 of file m525xsim.h.
| #define MCFI2C_SIZE1 0x20 /* Register set size */ |
Definition at line 117 of file m525xsim.h.
| #define MCFINTC2_INTBASE (MCF_MBAR2 + 0x168) /* Base Vector Reg */ |
Definition at line 72 of file m525xsim.h.
| #define MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */ |
Definition at line 73 of file m525xsim.h.
| #define MCFINTC2_INTPRI2 (MCF_MBAR2 + 0x144) /* 8-15 priority */ |
Definition at line 74 of file m525xsim.h.
| #define MCFINTC2_INTPRI3 (MCF_MBAR2 + 0x148) /* 16-23 priority */ |
Definition at line 75 of file m525xsim.h.
| #define MCFINTC2_INTPRI4 (MCF_MBAR2 + 0x14c) /* 24-31 priority */ |
Definition at line 76 of file m525xsim.h.
| #define MCFINTC2_INTPRI5 (MCF_MBAR2 + 0x150) /* 32-39 priority */ |
Definition at line 77 of file m525xsim.h.
| #define MCFINTC2_INTPRI6 (MCF_MBAR2 + 0x154) /* 40-47 priority */ |
Definition at line 78 of file m525xsim.h.
| #define MCFINTC2_INTPRI7 (MCF_MBAR2 + 0x158) /* 48-55 priority */ |
Definition at line 79 of file m525xsim.h.
| #define MCFINTC2_INTPRI8 (MCF_MBAR2 + 0x15c) /* 56-63 priority */ |
Definition at line 80 of file m525xsim.h.
Definition at line 84 of file m525xsim.h.
| #define MCFINTC2_INTPRI_REG | ( | i | ) |
Definition at line 82 of file m525xsim.h.
| #define MCFINTC2_VECBASE 128 |
Definition at line 157 of file m525xsim.h.
| #define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */ |
Definition at line 101 of file m525xsim.h.
| #define MCFQSPI_CS0 15 |
Definition at line 105 of file m525xsim.h.
| #define MCFQSPI_CS1 16 |
Definition at line 106 of file m525xsim.h.
| #define MCFQSPI_CS2 24 |
Definition at line 107 of file m525xsim.h.
| #define MCFQSPI_CS3 28 |
Definition at line 108 of file m525xsim.h.
| #define MCFQSPI_SIZE 0x40 /* Register set size */ |
Definition at line 102 of file m525xsim.h.
| #define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */ |
Definition at line 179 of file m525xsim.h.
| #define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */ |
Definition at line 180 of file m525xsim.h.
| #define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */ |
Definition at line 177 of file m525xsim.h.
| #define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */ |
Definition at line 178 of file m525xsim.h.
| #define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */ |
Definition at line 175 of file m525xsim.h.
| #define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */ |
Definition at line 176 of file m525xsim.h.
| #define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */ |
Definition at line 183 of file m525xsim.h.
| #define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */ |
Definition at line 184 of file m525xsim.h.
| #define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */ |
Definition at line 182 of file m525xsim.h.
| #define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */ |
Definition at line 173 of file m525xsim.h.
| #define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */ |
Definition at line 174 of file m525xsim.h.
| #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */ |
Definition at line 49 of file m525xsim.h.
| #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */ |
Definition at line 52 of file m525xsim.h.
| #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */ |
Definition at line 55 of file m525xsim.h.
| #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */ |
Definition at line 58 of file m525xsim.h.
| #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */ |
Definition at line 61 of file m525xsim.h.
| #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */ |
Definition at line 51 of file m525xsim.h.
| #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */ |
Definition at line 54 of file m525xsim.h.
| #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ |
Definition at line 57 of file m525xsim.h.
| #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ |
Definition at line 60 of file m525xsim.h.
| #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ |
Definition at line 63 of file m525xsim.h.
| #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */ |
Definition at line 50 of file m525xsim.h.
| #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */ |
Definition at line 53 of file m525xsim.h.
| #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */ |
Definition at line 56 of file m525xsim.h.
| #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */ |
Definition at line 59 of file m525xsim.h.
| #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */ |
Definition at line 62 of file m525xsim.h.
| #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ |
Definition at line 66 of file m525xsim.h.
| #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ |
Definition at line 65 of file m525xsim.h.
| #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ |
Definition at line 135 of file m525xsim.h.
| #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ |
Definition at line 136 of file m525xsim.h.
| #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ |
Definition at line 137 of file m525xsim.h.
| #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ |
Definition at line 138 of file m525xsim.h.
| #define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */ |
Definition at line 67 of file m525xsim.h.
| #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */ |
Definition at line 132 of file m525xsim.h.
| #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ |
Definition at line 36 of file m525xsim.h.
| #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ |
Definition at line 37 of file m525xsim.h.
| #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */ |
Definition at line 46 of file m525xsim.h.
| #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */ |
Definition at line 47 of file m525xsim.h.
| #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */ |
Definition at line 38 of file m525xsim.h.
| #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */ |
Definition at line 39 of file m525xsim.h.
| #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */ |
Definition at line 40 of file m525xsim.h.
| #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */ |
Definition at line 41 of file m525xsim.h.
| #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */ |
Definition at line 42 of file m525xsim.h.
| #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */ |
Definition at line 43 of file m525xsim.h.
| #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */ |
Definition at line 44 of file m525xsim.h.
| #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */ |
Definition at line 45 of file m525xsim.h.
| #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ |
Definition at line 35 of file m525xsim.h.
| #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */ |
Definition at line 34 of file m525xsim.h.
| #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */ |
Definition at line 33 of file m525xsim.h.
| #define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */ |
Definition at line 139 of file m525xsim.h.
| #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ |
Definition at line 29 of file m525xsim.h.
| #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ |
Definition at line 129 of file m525xsim.h.
| #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ |
Definition at line 31 of file m525xsim.h.
| #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */ |
Definition at line 32 of file m525xsim.h.
| #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ |
Definition at line 30 of file m525xsim.h.
| #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ |
Definition at line 130 of file m525xsim.h.
| #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ |
Definition at line 131 of file m525xsim.h.
| #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ |
Definition at line 133 of file m525xsim.h.
| #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ |
Definition at line 134 of file m525xsim.h.
| #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ |
Definition at line 89 of file m525xsim.h.
| #define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ |
Definition at line 90 of file m525xsim.h.
| #define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ |
Definition at line 95 of file m525xsim.h.
| #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ |
Definition at line 96 of file m525xsim.h.
1.8.2