Linux Kernel  3.7.1
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m527x.c
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1 /***************************************************************************/
2 
3 /*
4  * linux/arch/m68knommu/platform/527x/config.c
5  *
6  * Sub-architcture dependent initialization code for the Freescale
7  * 5270/5271 CPUs.
8  *
9  * Copyright (C) 1999-2004, Greg Ungerer ([email protected])
10  * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
11  */
12 
13 /***************************************************************************/
14 
15 #include <linux/kernel.h>
16 #include <linux/param.h>
17 #include <linux/init.h>
18 #include <linux/io.h>
19 #include <asm/machdep.h>
20 #include <asm/coldfire.h>
21 #include <asm/mcfsim.h>
22 #include <asm/mcfuart.h>
23 
24 /***************************************************************************/
25 
26 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
27 
28 static void __init m527x_qspi_init(void)
29 {
30 #if defined(CONFIG_M5271)
31  u16 par;
32 
33  /* setup QSPS pins for QSPI with gpio CS control */
34  writeb(0x1f, MCFGPIO_PAR_QSPI);
35  /* and CS2 & CS3 as gpio */
36  par = readw(MCFGPIO_PAR_TIMER);
37  par &= 0x3f3f;
38  writew(par, MCFGPIO_PAR_TIMER);
39 #elif defined(CONFIG_M5275)
40  /* setup QSPS pins for QSPI with gpio CS control */
41  writew(0x003e, MCFGPIO_PAR_QSPI);
42 #endif
43 }
44 
45 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
46 
47 /***************************************************************************/
48 
49 static void __init m527x_uarts_init(void)
50 {
51  u16 sepmask;
52 
53  /*
54  * External Pin Mask Setting & Enable External Pin for Interface
55  */
56  sepmask = readw(MCFGPIO_PAR_UART);
57  sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
58  writew(sepmask, MCFGPIO_PAR_UART);
59 }
60 
61 /***************************************************************************/
62 
63 static void __init m527x_fec_init(void)
64 {
65  u16 par;
66  u8 v;
67 
68  /* Set multi-function pins to ethernet mode for fec0 */
69 #if defined(CONFIG_M5271)
70  v = readb(MCFGPIO_PAR_FECI2C);
71  writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
72 #else
73  par = readw(MCFGPIO_PAR_FECI2C);
74  writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
75  v = readb(MCFGPIO_PAR_FEC0HL);
76  writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
77 
78  /* Set multi-function pins to ethernet mode for fec1 */
79  par = readw(MCFGPIO_PAR_FECI2C);
80  writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
81  v = readb(MCFGPIO_PAR_FEC1HL);
82  writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
83 #endif
84 }
85 
86 /***************************************************************************/
87 
88 void __init config_BSP(char *commandp, int size)
89 {
90  mach_sched_init = hw_timer_init;
91  m527x_uarts_init();
92  m527x_fec_init();
93 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
94  m527x_qspi_init();
95 #endif
96 }
97 
98 /***************************************************************************/
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