|
Linux Kernel
3.7.1
|
All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
|
Linux Kernel
3.7.1
|
#include <asm/m52xxacr.h>Go to the source code of this file.
Macros | |
| #define | CPU_NAME "COLDFIRE(m523x)" |
| #define | CPU_INSTR_PER_JIFFY 3 |
| #define | MCF_BUSCLK (MCF_CLK / 2) |
| #define | MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ |
| #define | MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */ |
| #define | MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
| #define | MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ |
| #define | MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ |
| #define | MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ |
| #define | MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ |
| #define | MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ |
| #define | MCFINTC_IRLR 0x18 /* */ |
| #define | MCFINTC_IACKL 0x19 /* */ |
| #define | MCFINTC_ICR0 0x40 /* Base ICR register */ |
| #define | MCFINT_VECBASE 64 /* Vector base number */ |
| #define | MCFINT_UART0 13 /* Interrupt number for UART0 */ |
| #define | MCFINT_UART1 14 /* Interrupt number for UART1 */ |
| #define | MCFINT_UART2 15 /* Interrupt number for UART2 */ |
| #define | MCFINT_QSPI 18 /* Interrupt number for QSPI */ |
| #define | MCFINT_FECRX0 23 /* Interrupt number for FEC */ |
| #define | MCFINT_FECTX0 27 /* Interrupt number for FEC */ |
| #define | MCFINT_FECENTC0 29 /* Interrupt number for FEC */ |
| #define | MCFINT_PIT1 36 /* Interrupt number for PIT1 */ |
| #define | MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) |
| #define | MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) |
| #define | MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) |
| #define | MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) |
| #define | MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) |
| #define | MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) |
| #define | MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) |
| #define | MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) |
| #define | MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ |
| #define | MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ |
| #define | MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */ |
| #define | MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */ |
| #define | MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ |
| #define | MCF_RCR (MCF_IPSBAR + 0x110000) |
| #define | MCF_RSR (MCF_IPSBAR + 0x110001) |
| #define | MCF_RCR_SWRESET 0x80 /* Software reset bit */ |
| #define | MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ |
| #define | MCFUART_BASE0 (MCF_IPSBAR + 0x200) |
| #define | MCFUART_BASE1 (MCF_IPSBAR + 0x240) |
| #define | MCFUART_BASE2 (MCF_IPSBAR + 0x280) |
| #define | MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) |
| #define | MCFFEC_SIZE0 0x800 |
| #define | MCFQSPI_BASE (MCF_IPSBAR + 0x340) |
| #define | MCFQSPI_SIZE 0x40 |
| #define | MCFQSPI_CS0 91 |
| #define | MCFQSPI_CS1 92 |
| #define | MCFQSPI_CS2 103 |
| #define | MCFQSPI_CS3 99 |
| #define | MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) |
| #define | MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) |
| #define | MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) |
| #define | MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) |
| #define | MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) |
| #define | MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) |
| #define | MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) |
| #define | MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) |
| #define | MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) |
| #define | MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) |
| #define | MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) |
| #define | MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) |
| #define | MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C) |
| #define | MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) |
| #define | MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) |
| #define | MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) |
| #define | MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) |
| #define | MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) |
| #define | MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) |
| #define | MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) |
| #define | MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) |
| #define | MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) |
| #define | MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) |
| #define | MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) |
| #define | MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) |
| #define | MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C) |
| #define | MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) |
| #define | MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) |
| #define | MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) |
| #define | MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) |
| #define | MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) |
| #define | MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) |
| #define | MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) |
| #define | MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) |
| #define | MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) |
| #define | MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) |
| #define | MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) |
| #define | MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) |
| #define | MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C) |
| #define | MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) |
| #define | MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) |
| #define | MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) |
| #define | MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) |
| #define | MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) |
| #define | MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) |
| #define | MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) |
| #define | MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) |
| #define | MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) |
| #define | MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) |
| #define | MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) |
| #define | MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) |
| #define | MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C) |
| #define | MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) |
| #define | MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) |
| #define | MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) |
| #define | MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) |
| #define | MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) |
| #define | MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) |
| #define | MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) |
| #define | MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) |
| #define | MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) |
| #define | MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) |
| #define | MCFGPIO_PODR MCFGPIO_PODR_ADDR |
| #define | MCFGPIO_PDDR MCFGPIO_PDDR_ADDR |
| #define | MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR |
| #define | MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR |
| #define | MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR |
| #define | MCFGPIO_PIN_MAX 107 |
| #define | MCFGPIO_IRQ_MAX 8 |
| #define | MCFGPIO_IRQ_VECBASE MCFINT_VECBASE |
| #define | MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040) |
| #define | MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042) |
| #define | MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044) |
| #define | MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045) |
| #define | MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046) |
| #define | MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047) |
| #define | MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048) |
| #define | MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) |
| #define | MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) |
| #define | MCFGPIO_PAR_ETPU (MCF_IPSBAR + 0x10004E) |
| #define | MCFDMA_BASE0 (MCF_IPSBAR + 0x100) |
| #define | MCFDMA_BASE1 (MCF_IPSBAR + 0x140) |
| #define | MCFDMA_BASE2 (MCF_IPSBAR + 0x180) |
| #define | MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) |
| #define CPU_INSTR_PER_JIFFY 3 |
Definition at line 15 of file m523xsim.h.
| #define CPU_NAME "COLDFIRE(m523x)" |
Definition at line 14 of file m523xsim.h.
| #define MCF_BUSCLK (MCF_CLK / 2) |
Definition at line 16 of file m523xsim.h.
| #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) |
Definition at line 52 of file m523xsim.h.
| #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) |
Definition at line 50 of file m523xsim.h.
| #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) |
Definition at line 51 of file m523xsim.h.
| #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) |
Definition at line 55 of file m523xsim.h.
| #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) |
Definition at line 54 of file m523xsim.h.
| #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) |
Definition at line 46 of file m523xsim.h.
| #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) |
Definition at line 47 of file m523xsim.h.
| #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) |
Definition at line 48 of file m523xsim.h.
| #define MCF_RCR (MCF_IPSBAR + 0x110000) |
Definition at line 69 of file m523xsim.h.
| #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ |
Definition at line 73 of file m523xsim.h.
| #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ |
Definition at line 72 of file m523xsim.h.
| #define MCF_RSR (MCF_IPSBAR + 0x110001) |
Definition at line 70 of file m523xsim.h.
| #define MCFDMA_BASE0 (MCF_IPSBAR + 0x100) |
Definition at line 206 of file m523xsim.h.
| #define MCFDMA_BASE1 (MCF_IPSBAR + 0x140) |
Definition at line 207 of file m523xsim.h.
| #define MCFDMA_BASE2 (MCF_IPSBAR + 0x180) |
Definition at line 208 of file m523xsim.h.
| #define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) |
Definition at line 209 of file m523xsim.h.
| #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) |
Definition at line 170 of file m523xsim.h.
| #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) |
Definition at line 172 of file m523xsim.h.
| #define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) |
Definition at line 174 of file m523xsim.h.
| #define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) |
Definition at line 171 of file m523xsim.h.
| #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) |
Definition at line 169 of file m523xsim.h.
| #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) |
Definition at line 173 of file m523xsim.h.
| #define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) |
Definition at line 85 of file m523xsim.h.
| #define MCFFEC_SIZE0 0x800 |
Definition at line 86 of file m523xsim.h.
| #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR |
Definition at line 183 of file m523xsim.h.
| #define MCFGPIO_IRQ_MAX 8 |
Definition at line 186 of file m523xsim.h.
| #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE |
Definition at line 187 of file m523xsim.h.
| #define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040) |
Definition at line 192 of file m523xsim.h.
| #define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044) |
Definition at line 194 of file m523xsim.h.
| #define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042) |
Definition at line 193 of file m523xsim.h.
| #define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045) |
Definition at line 195 of file m523xsim.h.
| #define MCFGPIO_PAR_ETPU (MCF_IPSBAR + 0x10004E) |
Definition at line 201 of file m523xsim.h.
| #define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047) |
Definition at line 197 of file m523xsim.h.
| #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) |
Definition at line 199 of file m523xsim.h.
| #define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046) |
Definition at line 196 of file m523xsim.h.
| #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) |
Definition at line 200 of file m523xsim.h.
| #define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048) |
Definition at line 198 of file m523xsim.h.
| #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) |
Definition at line 144 of file m523xsim.h.
| #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) |
Definition at line 148 of file m523xsim.h.
| #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) |
Definition at line 147 of file m523xsim.h.
| #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) |
Definition at line 149 of file m523xsim.h.
| #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) |
Definition at line 145 of file m523xsim.h.
| #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) |
Definition at line 146 of file m523xsim.h.
| #define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C) |
Definition at line 156 of file m523xsim.h.
| #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) |
Definition at line 151 of file m523xsim.h.
| #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) |
Definition at line 154 of file m523xsim.h.
| #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) |
Definition at line 150 of file m523xsim.h.
| #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) |
Definition at line 155 of file m523xsim.h.
| #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) |
Definition at line 152 of file m523xsim.h.
| #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) |
Definition at line 153 of file m523xsim.h.
| #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR |
Definition at line 180 of file m523xsim.h.
| #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) |
Definition at line 116 of file m523xsim.h.
| #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) |
Definition at line 120 of file m523xsim.h.
| #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) |
Definition at line 119 of file m523xsim.h.
| #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) |
Definition at line 121 of file m523xsim.h.
| #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) |
Definition at line 117 of file m523xsim.h.
| #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) |
Definition at line 118 of file m523xsim.h.
| #define MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C) |
Definition at line 128 of file m523xsim.h.
| #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) |
Definition at line 123 of file m523xsim.h.
| #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) |
Definition at line 126 of file m523xsim.h.
| #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) |
Definition at line 122 of file m523xsim.h.
| #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) |
Definition at line 127 of file m523xsim.h.
| #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) |
Definition at line 124 of file m523xsim.h.
| #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) |
Definition at line 125 of file m523xsim.h.
| #define MCFGPIO_PIN_MAX 107 |
Definition at line 185 of file m523xsim.h.
| #define MCFGPIO_PODR MCFGPIO_PODR_ADDR |
Definition at line 179 of file m523xsim.h.
| #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) |
Definition at line 102 of file m523xsim.h.
| #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) |
Definition at line 106 of file m523xsim.h.
| #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) |
Definition at line 105 of file m523xsim.h.
| #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) |
Definition at line 107 of file m523xsim.h.
| #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) |
Definition at line 103 of file m523xsim.h.
| #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) |
Definition at line 104 of file m523xsim.h.
| #define MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C) |
Definition at line 114 of file m523xsim.h.
| #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) |
Definition at line 109 of file m523xsim.h.
| #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) |
Definition at line 112 of file m523xsim.h.
| #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) |
Definition at line 108 of file m523xsim.h.
| #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) |
Definition at line 113 of file m523xsim.h.
| #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) |
Definition at line 110 of file m523xsim.h.
| #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) |
Definition at line 111 of file m523xsim.h.
| #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR |
Definition at line 181 of file m523xsim.h.
| #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) |
Definition at line 130 of file m523xsim.h.
| #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) |
Definition at line 134 of file m523xsim.h.
| #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) |
Definition at line 133 of file m523xsim.h.
| #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) |
Definition at line 135 of file m523xsim.h.
| #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) |
Definition at line 131 of file m523xsim.h.
| #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) |
Definition at line 132 of file m523xsim.h.
| #define MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C) |
Definition at line 142 of file m523xsim.h.
| #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) |
Definition at line 137 of file m523xsim.h.
| #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) |
Definition at line 140 of file m523xsim.h.
| #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) |
Definition at line 136 of file m523xsim.h.
| #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) |
Definition at line 141 of file m523xsim.h.
| #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) |
Definition at line 138 of file m523xsim.h.
| #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) |
Definition at line 139 of file m523xsim.h.
| #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR |
Definition at line 182 of file m523xsim.h.
| #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ |
Definition at line 23 of file m523xsim.h.
| #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */ |
Definition at line 24 of file m523xsim.h.
Definition at line 43 of file m523xsim.h.
Definition at line 41 of file m523xsim.h.
Definition at line 42 of file m523xsim.h.
Definition at line 44 of file m523xsim.h.
Definition at line 40 of file m523xsim.h.
Definition at line 37 of file m523xsim.h.
Definition at line 38 of file m523xsim.h.
Definition at line 39 of file m523xsim.h.
Definition at line 36 of file m523xsim.h.
| #define MCFINTC_IACKL 0x19 /* */ |
Definition at line 33 of file m523xsim.h.
| #define MCFINTC_ICR0 0x40 /* Base ICR register */ |
Definition at line 34 of file m523xsim.h.
| #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ |
Definition at line 28 of file m523xsim.h.
| #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ |
Definition at line 29 of file m523xsim.h.
| #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ |
Definition at line 30 of file m523xsim.h.
| #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ |
Definition at line 31 of file m523xsim.h.
| #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
Definition at line 26 of file m523xsim.h.
| #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ |
Definition at line 27 of file m523xsim.h.
| #define MCFINTC_IRLR 0x18 /* */ |
Definition at line 32 of file m523xsim.h.
| #define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) |
Definition at line 161 of file m523xsim.h.
| #define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) |
Definition at line 162 of file m523xsim.h.
| #define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) |
Definition at line 163 of file m523xsim.h.
| #define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) |
Definition at line 164 of file m523xsim.h.
| #define MCFQSPI_BASE (MCF_IPSBAR + 0x340) |
Definition at line 91 of file m523xsim.h.
| #define MCFQSPI_CS0 91 |
Definition at line 94 of file m523xsim.h.
| #define MCFQSPI_CS1 92 |
Definition at line 95 of file m523xsim.h.
| #define MCFQSPI_CS2 103 |
Definition at line 96 of file m523xsim.h.
| #define MCFQSPI_CS3 99 |
Definition at line 97 of file m523xsim.h.
| #define MCFQSPI_SIZE 0x40 |
Definition at line 92 of file m523xsim.h.
| #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ |
Definition at line 61 of file m523xsim.h.
| #define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */ |
Definition at line 63 of file m523xsim.h.
| #define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ |
Definition at line 60 of file m523xsim.h.
| #define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */ |
Definition at line 62 of file m523xsim.h.
| #define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ |
Definition at line 64 of file m523xsim.h.
| #define MCFUART_BASE0 (MCF_IPSBAR + 0x200) |
Definition at line 78 of file m523xsim.h.
| #define MCFUART_BASE1 (MCF_IPSBAR + 0x240) |
Definition at line 79 of file m523xsim.h.
| #define MCFUART_BASE2 (MCF_IPSBAR + 0x280) |
Definition at line 80 of file m523xsim.h.
1.8.2