m53xxacr.h File Reference

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Macros
#define	CACR_EC   0x80000000 /* Enable cache */
#define	CACR_ESB   0x20000000 /* Enable store buffer */
#define	CACR_DPI   0x10000000 /* Disable invalidation by CPUSHL */
#define	CACR_HLCK   0x08000000 /* Half cache lock mode */
#define	CACR_CINVA   0x01000000 /* Invalidate cache */
#define	CACR_DNFB   0x00000400 /* Inhibited fill buffer */
#define	CACR_DCM_WT   0x00000000 /* Cacheable write-through */
#define	CACR_DCM_CB   0x00000100 /* Cacheable copy-back */
#define	CACR_DCM_PRE   0x00000200 /* Cache inhibited, precise */
#define	CACR_DCM_IMPRE   0x00000300 /* Cache inhibited, imprecise */
#define	CACR_WPROTECT   0x00000020 /* Write protect*/
#define	CACR_EUSP   0x00000010 /* Eanble separate user a7 */
#define	ACR_BASE_POS   24 /* Address Base (upper 8 bits) */
#define	ACR_MASK_POS   16 /* Address Mask (next 8 bits) */
#define	ACR_ENABLE   0x00008000 /* Enable this ACR */
#define	ACR_USER   0x00000000 /* Allow only user accesses */
#define	ACR_SUPER   0x00002000 /* Allow supervisor access only */
#define	ACR_ANY   0x00004000 /* Allow any access type */
#define	ACR_CM_WT   0x00000000 /* Cacheable, write-through */
#define	ACR_CM_CB   0x00000020 /* Cacheable, copy-back */
#define	ACR_CM_PRE   0x00000040 /* Cache inhibited, precise */
#define	ACR_CM_IMPRE   0x00000060 /* Cache inhibited, imprecise */
#define	ACR_WPROTECT   0x00000004 /* Write protect region */
#define	CACHE_LINE_SIZE   16 /* 16 byte line size */
#define	CACHE_WAYS   4 /* 4 ways - set associative */
#define	CACHE_TYPE   ACR_CM_WT
#define	CACHE_MODE   (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP)
#define	CACHE_INIT   CACR_CINVA
#define	CACHE_INVALIDATE   CACR_CINVA
#define	CACHE_INVALIDATED   CACR_CINVA
#define	ACR0_MODE
#define	ACR1_MODE   0

Macro Definition Documentation

#define ACR0_MODE

Value:

((CONFIG_RAMBASE & 0xff000000) + \
             (0x000f0000) + \
             (ACR_ENABLE + ACR_ANY + CACHE_TYPE))

Definition at line 95 of file m53xxacr.h.

#define ACR1_MODE   0

Definition at line 98 of file m53xxacr.h.

#define ACR_ANY   0x00004000 /* Allow any access type */

Definition at line 44 of file m53xxacr.h.

#define ACR_BASE_POS   24 /* Address Base (upper 8 bits) */

Definition at line 39 of file m53xxacr.h.

#define ACR_CM_CB   0x00000020 /* Cacheable, copy-back */

Definition at line 46 of file m53xxacr.h.

#define ACR_CM_IMPRE   0x00000060 /* Cache inhibited, imprecise */

Definition at line 48 of file m53xxacr.h.

#define ACR_CM_PRE   0x00000040 /* Cache inhibited, precise */

Definition at line 47 of file m53xxacr.h.

#define ACR_CM_WT   0x00000000 /* Cacheable, write-through */

Definition at line 45 of file m53xxacr.h.

#define ACR_ENABLE   0x00008000 /* Enable this ACR */

Definition at line 41 of file m53xxacr.h.

#define ACR_MASK_POS   16 /* Address Mask (next 8 bits) */

Definition at line 40 of file m53xxacr.h.

#define ACR_SUPER   0x00002000 /* Allow supervisor access only */

Definition at line 43 of file m53xxacr.h.

#define ACR_USER   0x00000000 /* Allow only user accesses */

Definition at line 42 of file m53xxacr.h.

#define ACR_WPROTECT   0x00000004 /* Write protect region */

Definition at line 49 of file m53xxacr.h.

#define CACHE_INIT   CACR_CINVA

Definition at line 91 of file m53xxacr.h.

#define CACHE_INVALIDATE   CACR_CINVA

Definition at line 92 of file m53xxacr.h.

#define CACHE_INVALIDATED   CACR_CINVA

Definition at line 93 of file m53xxacr.h.

#define CACHE_LINE_SIZE   16 /* 16 byte line size */

Definition at line 64 of file m53xxacr.h.

#define CACHE_MODE   (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP)

Definition at line 82 of file m53xxacr.h.

#define CACHE_TYPE   ACR_CM_WT

Definition at line 76 of file m53xxacr.h.

#define CACHE_WAYS   4 /* 4 ways - set associative */

Definition at line 65 of file m53xxacr.h.

#define CACR_CINVA   0x01000000 /* Invalidate cache */

Definition at line 27 of file m53xxacr.h.

#define CACR_DCM_CB   0x00000100 /* Cacheable copy-back */

Definition at line 30 of file m53xxacr.h.

#define CACR_DCM_IMPRE   0x00000300 /* Cache inhibited, imprecise */

Definition at line 32 of file m53xxacr.h.

#define CACR_DCM_PRE   0x00000200 /* Cache inhibited, precise */

Definition at line 31 of file m53xxacr.h.

#define CACR_DCM_WT   0x00000000 /* Cacheable write-through */

Definition at line 29 of file m53xxacr.h.

#define CACR_DNFB   0x00000400 /* Inhibited fill buffer */

Definition at line 28 of file m53xxacr.h.

#define CACR_DPI   0x10000000 /* Disable invalidation by CPUSHL */

Definition at line 25 of file m53xxacr.h.

#define CACR_EC   0x80000000 /* Enable cache */

Definition at line 23 of file m53xxacr.h.

#define CACR_ESB   0x20000000 /* Enable store buffer */

Definition at line 24 of file m53xxacr.h.

#define CACR_EUSP   0x00000010 /* Eanble separate user a7 */

Definition at line 34 of file m53xxacr.h.

#define CACR_HLCK   0x08000000 /* Half cache lock mode */

Definition at line 26 of file m53xxacr.h.

#define CACR_WPROTECT   0x00000020 /* Write protect*/

Definition at line 33 of file m53xxacr.h.